IEDM 2017: Intel’s 10nm Platform Process

By Dick James

IEDM this year was its usual mixture of academic exotica and industrial pragmatica (to use a very broad-brush description), but the committee chose to keep us all waiting until the Wednesday morning before we got to the CMOS platform papers. Of course, the talk we were all anticipating was Intel’s Chris Auth on “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects”.

Deliberate or not, Intel has been teasing us with release dates for their 10-nm products, and as yet there have not been any out in the market for the analysts to get their hands on and expose the secrets. TSMC and Samsung we have seen, but not Intel (and arguably, they are closer to 14-nm technology). Needless to say, the room was full, and Chris did the usual Intel preamble about being ahead of the 2x shrink trend, and achieving 100M transistors/mm2.

Intel 10-1


The claim is that density increases by a factor of 2.7 from the 14nm generation, using the metric announced by Mark Bohr at the Technology and Manufacturing Day (TMD) earlier this year:

Intel 10-2


The paper states that this was achieved by “use of SAQP w/193nm immersion lithography, improved transistor matching to enable fewer fins in the standard cell library and novel process features to enable tighter layout.”

The table below shows the design rules and shrink from the 14-nm process:

Intel 10-3

Any pitch 40 nm or below needs quad-patterning (or LELELE), so the fins, M0 and M1 use SAQP. Compared with SADP, Intel’s SAQP needs four additional steps, one deposition on the sidewall spacers from the original mandrel, and three etch steps. In addition to the feature shrinks, there are technology changes in the standard cell layout. The dummy gates at the cell boundaries have gone, replaced by a single gate spacing; and the gate contact is now over the active gate, ending the need for isolation space to fit in the contact.

The 14-nm process had a dummy gate at the edge of each cell, on the end of adjacent fins, similar to this image of a 22-nm device;

Intel 10-4

The 10-nm cell uses a dummy gate spacing between fin ends, which saves a gate pitch when packing two cells together, a claimed 20% cell area saving.


Intel 10-5


In actual fact there is no dummy gate in the finished product, just the fin etched where a single dummy gate would be. This was shown in the presentation, but it is not in the paper, but Samsung did something very similar in their 10-nm offering:

Intel 10-6_Samsung 10 SDG


In fact, a dummy polySi gate is used, allowing source/drain formation without risking the fin edge; but for these particular gates the polySi removal etch goes a bit further, and etches the fin to separate the cells.

The second layout change is to shift the gate contact into the active transistor area, over the functional part of the gate (see below).

Intel 10-7


Such tight alignment with the source/drain (diffusion) contacts requires the development of self-aligned contacts to the gate, and modification of the self-aligned diffusion contacts that were already in use at 14-nm and 22-nm.

Diffusion contacts (left) and gate contacts

Diffusion contacts (left) and gate contacts

To do this, two etch-stop materials and two selective etches are used. After gate formation it is etched back and the cavity is filled with silicon nitride, as in earlier generations; the contact is then put in and also etched back, and the cavity is filled with silicon carbide. Then there is a selective etch to open the gate contact, which does not touch the SiC in the contact cavity, and a second selective etch removes the SiC from the contact cavity, but does not affect the gate contact periphery. Clearly this sequence is reliant on excellent etch selectivity between the different materials.

There are other innovations in the contact stack – the contacts themselves are cobalt, giving >60% line resistance reduction, and there is a conformal titanium layer wrapped around the source drain epi, as well as a thin nickel silicide layer on the PMOS epi. This is claimed to give ~1.5x contact resistance reduction.

The fins are SAQP-defined with a 34-nm pitch, 7 nm width (at ½-height), and 46 nm height. Intel appeared to have backed off on the 53-nm fin height that they announced back in March. 46 nm is still an increase from the 42 nm of the 14-nm process, just not as ambitious; if memory is accurate, that is the same as the 14+ fin height. I guess the taller fin could be looking forward to the 10+ or 10++ generation. In the Q&A we were told that the fin height is tunable with a range of ~10 nm, and 46 nm is at “the low end of the mid-range”.

In fact, if you use the fin pitch as calibration, the fin height in Intel’s image is ~52 nm, and close examination reveals that it is the same image as that shown in Kaizad Mistry’s TMD talk last March.

Intel 10-12m

And if we compare this pic with the 14-nm device, it appears that the solid-source punch-stop diffusions introduced at 14-nm are present, since we can see the seal layer(s).

Intel 10-10


This allows the fin to be un-doped in the channel, with options for four or six Vts (low, standard and optional high Vts) with differing work-function metals. Source/drain epis are in-situ doped and provide strain enhancement, though we are not told if that is N- or P-MOS or both, nor is SiGe mentioned, though I would assume it is still used for PMOS stress. NMOS drive is also enhanced by interlayer dielectric stress, giving a ~10% improvement (from my notes – the paper says 5%).

With a smaller fin pitch the implant angle needed for doping is also shrinking; I measured it as less than 30o, compared with the 52o and 41o of the 22- and 14-nm processes, but I am told that if the implant has a twist (i.e. angled with respect to the fin orientation), then it is till feasible to get implants into the right location.

Additionally, the k-value of the sidewall spacers has been lowered, to reduce the parasitic contact-gate capacitance by 10%, and my notes also say that the gate fill has been changed to cobalt.

With a 46-nm fin height the gate width should be ~97 nm, compared with the ~85 nm of the previous generation (or the same as the 14+). If the 53-nm fin height is used, gate width is likely ~110 nm. Minimum gate length was stated to be 18 nm.

All of this transistor engineering leads to a NMOS Idsat of 1.78 mA/µm and Idlin of 0.475 mA/µm at 0.7 V and 10 nA/µm, increases of 71% and 100% compared to 14-nm FINFET transistors, for minimum Lg devices. Similarly, PMOS shows drive current gains of 35% Idsat and 55% Idlin. Steep subthreshold slopes (~70 mV/dec.) and very low DIBL (~70 mV/V) are also found.

TEM cross-section of NMOS(?) gates

TEM cross-section of NMOS(?) gates

The middle- and back-end stack has thirteen metal layers (including M0), with cobalt used in M0 and M1 to replace copper. This gives a 2x resistance reduction, and 5 – 10x electromigration improvement. Self-aligned double patterning (SADP) is used at Metal 2 – Metal 5, and a cobalt cap (no liner, as in TSMC) is also used on M2 – M5 to improve electromigration. Low-k dielectrics are used on eleven layers out of the thirteen, and in the Q&A it was noted that it is the same low-k as in the 14-nm process.

The SRAM cells are scaled by a factor of ~0.6, so that the low-voltage 1:2:1 (fins in Pull-Up:Pass-Gate:Pull-Down transistors) cell goes from ~0.059 µm2 to ~0.0367 µm2, and the high-density 1:1:1 cell shrinks from ~0.050 µm2 to ~0.0312 µm2. (The TSMC and GF/IBM/Samsung 7-nm cells announced at IEDM16, presumably 1:1:1 cells, were 0.027 µm2.) There is also a high performance 0.0441 µm2 cell. Ring oscillator performance at 0.7 V was 20% better than the 14-nm device.

The cell height is 272 nm, so with a 34 nm fin pitch, we have eight fin spacings per cell; but we tend to lose two fins in the centre to allow for well boundaries, and one each at top and bottom under the Vdd/Vss lines, implying 2x two-fin transistors in the minimum standard cell. That agrees well with the comments in the paper about “aggressive reduction in fin usage, improving transistor density.”

Back in March we were told that the 10-nm process shrinks beyond the usual 50% to 37% of the 14nm technology:

Intel 10-13
And that this actually brings them back on to a two-year cadence from the 45-nm node, assuming high-volume production as of the second half of this year.

It’s a bit close to the end of the year for that to happen, but if we see product in the New Year they won’t be too far off – we look forward to it!

I had hoped to fit in some commentary about the GLOBALFOUNDRIES 7nm paper given in the same session, but in the interest of brevity I will have to make a separate blog, maybe in the New Year.

Intel 10-14


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2 thoughts on “IEDM 2017: Intel’s 10nm Platform Process

  1. Ajay

    Wow, amazing article. Intel always came up with new technologies. Recently, Intel lists four ME vulnerabilities (CVE-2017-5705, CVE-2017-5708, CVE-2017-5711, CVE-2017-5712), affecting a swathe of recent processors running ME Firmware v11.x onwards as well as Server Platform Services v4.0 and TXE v3.0.

  2. Venkateswarlu

    I would like to know the equivalent oxide thickness (EOT) used in 14nm & 10 nm node FinFETs by Intel. Can anyone suggest in this regard?


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