Siliconica

Monthly Archives: April 2015

Apple Watch Launch Confirms WiFi and NFC Inside

1 Reply
By Dick James, Senior Technology Analyst, Chipworks
Today (April 10) is the day that the Apple Watch becomes available for order, and of course we will be buying some to see what’s inside. We won’t be going for the gold Edition model, even so some of us here would like to; the Sport version should be quite good enough.
At the Apple event back on March 9 it was almost a case of last and least for the Apple Watch, after listening through the ResearchKit and new MacBook launches, and more Apple Pay demos. The Watch presentation was almost a case of déjà vu, since we got most of the details last year in the announcement last September.
The one new technical detail that I did pick up on was that the use of WiFi was confirmed – there was no mention of that last year (time 74.00 in the March 9 video). There was also much emphasis on the ability to use Apple Pay and make calls through the Watch, so we know that there are microphones in there, and it has NFC (near-field communications) capability, but we knew that after the initial launch last year.
The WiFi news was interesting to us, since we did a pseudo-teardown back then, based on Apple’s promo video, and we came to the conclusion that the Broadcom BCM4334 was in the Watch. But no mention of WiFi – what gives? I guess they just forgot, and even in the new launch it was just a passing reference.
We identified the BCM4334 from a layout image of the board inside the Watch that we took from a screen capture of the video, and the characteristic footprint of a flip-chip component.

Screen shot of PCB from Apple Watch – source: Apple film “Introducing Apple Watch”

Broadcom BCM4334 die and position on Apple Watch PCB

 

According to Broadcom, “The BCM4334 is a single-chip dual-band combo device supporting 802.11n, bluetooth 4.0+HS & FM receiver. It provides a complete wireless connectivity system with ultra-low power consumption for mass market smartphone devices. Using advanced design techniques and 40nm process technology to reduce active and idle power, the BCM4334 is designed to address the needs of highly mobile devices that require minimal power consumption and compact size while delivering dual-band Wi-Fi connectivity.”
So we have WiFi confirmed! In the meantime we’ve been looking at that board a little more, and we have also confirmed that the NFC and NFC booster chips used in the iPhone 6 and 6 Plus are also present.
Again, we looked at the footprints on the board – nothing quite as characteristic as the Broadcom chip, but knowing the size of the chip package and the solder ball array density gives us a good clue. And knowing the size of the BCM4334, we can work out the sizes of the other chips on the board.
In the iPhone 6 the NFC controller was a NXP 65V10, which contained the PN548 die, and an AMS AS3923 NFC power booster; so it’s at least a possibility that Apple will be using them in the Watch.
Below is the AS3923 from the iPhone, showing the 5 x 4 solder ball grid on the bottom of the part. Like the Broadcom chip, it is also a flip-chip-on-board (FCOB), so the die size will be characteristic, and while a 5 x 4 grid is certainly not unique, the combination of the two gives us reasonable confidence that a matching footprint on the Watch board indicates the presence of an AS3923.
Top and bottom images of AMS AS3923
Similarly with the NXP 65V10:
Top and bottom images of NXP 65V10 
Here we have a 7 x 7 array, but it and the die size coincide with a footprint on the PCB.
Lastly, a business contact pointed out that the motion sensing is likely done by the same Invensense sensor that was used in the iPhones, the MP67B (probably the MPU6700), and when we looked, again the size and solder pads match. We wrote about this after the iPhone analysis,and in its lowest power mode, it can draw less than 10 µA.

Top and bottom images of Invensense MP67B

Putting these three together, we see below:

PCB from Apple Watch showing Invensense, AMS, and NXP die positions

Come April 24 we will know what else is in there, as you can see that board is quite packed. In the meantime, we’ll be looking for some more recognizable components.

 

Samsung’s FinFETs ARE in the Galaxy S6!

4 Replies

By Dick James, Senior Technology Analyst, Chipworks

The much anticipated Samsung Galaxy S6 made an early appearance in our teardown labs last week,  thanks to the diligent skills of our trusted logistics guru. We got our hands on the 4G+ version, the SM-G920I, with what Samsung claims is the world’s first octa-core 64 bit operating system. There is a wide array of industry buzz surrounding this flagship smartphone, but from my process-oriented point of view the focal point has to be on the Exynos 7420 application processor.

Samsung Galaxy S6 Teardown
Galaxy S6 Motherboard

Samsung Exynos 7420 Application Processor

The Samsung Exynos 7420 application processor is reportedly fabbed in Samsung’s 14 nm FinFET process. This is what Samsung has shown so far.

Which is not exactly specific! To start with, here’s the package marking of the package-on-package:

The layout of this is quite unusual – normally the memory marking (SEC 507 etc.) is in lines of text above the APU marking (7420 etc.), not in a diagonally opposed block. Which leads me into the speculation that maybe the 7420 is out of GLOBALFOUNDRIES, rather than a Samsung fab in Korea or Texas. Could ALB be short for Albany (NY)? Is the G in the lot code short for GLOBALFOUNDRIES? That all seems rather unlikely, but if Samsung wants to switch on the volume quickly in anticipation of huge volumes for the S6, what better way than to use three fabs? They did sound very confident in their last quarterly analyst call, saying that they expect 14-nm to be 30% of the LSI line capacity by year end. And there are lots of rumours about Qualcomm using the Samsung 14-nm process.

The die photograph and the die mark confirm the use of the Exynos 7420:

The functional die size is ~78 mm2, which compares well with the ~118.3 mm^2 of the Snapdragon chip used in the Galaxy S5, and the 113 mm^2 size of the 20-nm Exynos 5433. If the 7420 was a straight shrink of the 5433, we’d expect it to be 55 – 60 mm^2, but the back-end metallization stack is reported to be similar to the 20-nm planar process, so a full 50% shrink is unlikely (and the analog regions never shrink as well as digital anyway). We’ll have to wait until we see the floorplan to see how much functionality the two parts have in common.

Our guys in the lab made their usual exceptional effort in enabling us to see what the process looks like – within a few hours of getting the phone in-house, we have a decapsulated part and a cross-sectional sample under the microscope.

The Exynos 7420 uses 11 layers of metal, as you can see from the die seal cross-section above. Now let’s look at the transistors:

And we do have finFETs! This section is parallel to the fins, and across the gates. The bottoms of the contacts approximately indicate the top edge of the fin, and we are seeing the gates wrapped over and further down the sidewalls of the fin than the contacts appear to go. We will need another section orthogonal to this one to see if we have the type of epi growth in the source-drains that Intel uses.

This makes Samsung the second in line to get finFETs into volume production; they have successfully taken their 20-nm, first-generation, gate-last, high-k, metal-gate stack and adapted it to a first generation fin structure. We will need more detailed images to see whether the fins have vertical or sloped sidewalls, and how close to the Intel model they are, but those will come in the fullness of time when we have completed our full analysis and published our report.

Meanwhile, keep an eye on the blog!