Monthly Archives: November 2016

IEDM 2016 Next Week! (Part 2)

By Dick James, Senior Technology Analyst, Chipworks

Read Part 1 here.

Now for the second part of the preview, starting with the Tuesday afternoon sessions:

Session 17: Process and Manufacturing Technology — Silicon Based Advanced CMOS

Here we look ahead a little, considering how silicon will evolve rather than using other higher-mobility materials. First up is a joint IBM/GF report of air spacers in 10nm finFET structures (17.1), between the gate and the contacts, to reduce the parasitic capacitance.

Schematic of partial air spacers (left), and TEM cross-section of finFET gates, showing spacers between gates and contacts (17.1)

Schematic of partial air spacers (left), and TEM cross-section of finFET gates, showing spacers between gates and contacts (17.1)

IBM/GF also study (17.2) the use of laser-induced liquid- or solid-phase epitaxy in contact trenches, to form semi-metallic, semiconductor-dopant (Si:P and Ge: group III metals) metastable alloys to reduce contact resistance.

17.3 also considers contact resistance, this time looking at Ni(Pt) silicide on fin-on-insulator (FOI) finFETs. IBM/GF are up again in 17.4, discussing low Ge-content SiGe finFETs; imec and Applied Materials are collaborating in the usage of high-temperature ion implantation in bulk finFET technology (17.5); next we look at vertically-stacked horizontal nanowires with replacement metal gates (RMG), inner spacers, and SiGe source/drain stress for p-FETs (17.6); and finally we have an FD-SOI paper, discussing a dual-isolation process (STI and local oxidation) to maximize both SiGe-channel stress and back-biasing performance(17.7). 

Session 18: Sensors, MEMS, and BioMEMS Enhanced Sensing, Heterogeneous Integration and Wearables

We start this session with a report (18.1) on using pre-bias to improve the sensitivity of a silicon FET gas detector which has ZnO as a sensing layer. Then Fujitsu describes a graphene-based gas sensor capable of detecting 7 ppb of nitric oxide (18.2), and in 18.3 laser-patterned graphene is used for strain sensing.

Graphene shows up again as a transparent epidermal sensor in 18.4, measuring skin temperature, hydration and electrophysiological signals (ECG, EEG, EMG). Prof. Shuji Tanaka of Tohoku University gives an invited talk on “Heterogeneously-Integrated Microdevices” in 18.5, then flexible (i.e. thin) bulk silicon is used for the system-level monolithic integration of multiple sensor types using CMOS processing, including a wearable version (18.6).

The session finishes (18.7) with an invited review by Raji Baskaran of Intel, on “Sensors and Haptics Technologies for User Interface Design in Wearables”. 

Session 19: Nano Device Technology — Tunnel and Nanowire FETs

The first paper combines both themes of the session – we have a vertical nanowire InAs/GaAsSb/GaSb tunnel FET (19.1) with a record high on-current of 10.6μA/μm.

Schematic of InAs/GaAsSb/GaSb TFET (left), and a colorized SEM image of a nanowire with W gate metal applied (19.1)

Schematic of InAs/GaAsSb/GaSb TFET (left), and a colorized SEM image of a nanowire with W gate metal applied (19.1)

19.2 is an invited review of a “Two-dimensional Heterojunction Interlayer Tunnel FET (Thin-TFET): From Theory to Applications” by Mingda Li from Cornell. The ThinFET was formed from WSe2/SnSe2 stacked heterostructures, which intrinsically has a smaller gate-drain capacitance due to its vertical stack.

Next we have the first hybrid Phase-Change-Tunnel FET (PC-TFET) device (19.3). Experimental digital and analog benchmarking of the new device was performed, and it was compared with Tunnel FETs and CMOS; it was also included into a neuromorphic computing cell, taking advantage of the phase-change mechanism.

Isoelectronic trap technology (IET) is used to improve the performance of silicon-based TFETs in 19.4, and Shinichi Takagi of U. Tokyo gives an invited review (19.5) of “Tunneling MOSFET Technologies using III-V/Ge Materials”.

The next paper details InGaAs/GaAs and Ge/GeSn p-TFETs on GaAsSb and GeSn substrates (19.6), and the last paper harks back to nanowires, this time vertical silicon GAA-NW transistors with a dual work-function, high-k last RMG process (19.7).

Session 20: Power Devices — Focus Session: System-level Impact of Power Devices

This session focuses on the use of GaN and SiC power devices and how they have expanded the spectrum of applications to very high voltages, temperatures and power levels, compared to existing silicon-based devices.

It comprises a sequence of invited talks:

  • Wide Bandgap (WBG) Power Devices and Their Impacts On Power Delivery Systems,” by Alex Huang, North Carolina State University
  • Si, SiC and GaN Power Devices: An Unbiased View on Key Performance Indicators,” by G. Deboy et al, Infineon/ETH-Zurich
  • System-Level Impact of GaN Power Devices in Server Architectures,” by A. Lidow et al, Efficient Power Conversion Corp.
  • GaN-based Semiconductor Devices for Future Power Switching Systems,” by H. Ishida et at, Panasonic
  • Application Reliability Validation of GaN Power Devices,” by S. Bahl et al, Texas Instruments
  • Horizon Beyond Ideal Power Devices,” by H. Ohashi, NPERC-J (Japan’s New-Generation Power Electronics & System Research Consortium)

 Session 21: Characterization, Reliability and Yield — Reliability and Characterization of Memory Devices, Contacts and Interfaces

This session starts with a reliability study of a 128 Mb GaSbGe PCM device (21.1), followed by an examination of the effect of filament shape on Cu/Al2O3 CBRAMs (21.2).

21.3 investigates the microsecond transient thermal behavior of HfOx-based RRAMs, and 21.4 identifies the switching/failure mechanisms in non-filamentary RRAM.

Back in September GLOBALFOUNDRIES and Everspin announced production of Everspin’s 256 Mb DDR3 perpendicular magnetic tunnel junction (pMTJ) product, and availability of the embedded version of the technology on GF’s 22FDX platform. Jon Slaughter of Everspin is giving an invited talk (21.5) “Technology for Reliable Spin-Torque MRAM Products”, which will include a review of the performance of the 256 Mb, DDR3 ST-MRAM chip.

In 21.6 we have an endurance study of perpendicular spin-transfer torque (p-STT) memory, and 21.7 describes Schottky contacts between silicon and graphene, to finish the session. 

Session 22: Optoelectronics, Displays, and Imagers — Optoelectronic Integration

We start with GeSn thin-film transistors (TFTs) formed on a quartz substrate, which have high carrier mobility and luminescence (22.1). The second paper utilizes the optical properties of SOI wafers to couple an InGaAsP laser to a pair of distributed Bragg reflectors (DBRs) and a grating coupler diffracting the light to an optical fiber (22.2).

Schematic of a heterogeneous hybrid III-V/Si DBR laser cavity with the gain zone, two DBRs and a grating coupler at one side diffracting the light to an optical fiber (22.2)

Schematic of a heterogeneous hybrid III-V/Si DBR laser cavity with the gain zone, two DBRs and a grating coupler at one side diffracting the light to an optical fiber (22.2)

22.3 is an invited presentation by Dan Buca of Forschungszentrum Julich, “GeSn Lasers for CMOS Integration”, followed by a description of a high-gain optical amplifier, monolithically integrated with an InGaN-based laser diode (22.4).

A germanium-on-silicon Zener emitter is detailed in 22.5, and NXP and A*STAR come up with a surprising method of optically sensing the states of flash memory in the last paper (22.6); they demonstrate it with the on-chip integration of an optical micro-ring resonator and a memory array, and claim 1200× sensing speed improvement.

That is numerically the last paper of the afternoon, if not chronologically – the sessions with seven papers finish at ~5.15 pm.

In the evening at 8 pm we have the panel sessions in the Continental Ballrooms:

  • How Will the Semiconductor Industry Change to Enable 50 Billion Connected Devices? Moderator: Prof. Aaron Thean, University of Singapore
  • Challenges and Opportunities for Neuromorphic and Machine Learning, Moderator: Marc Duranton, Sr. Member of the Embedded Computing Lab, CEA

But, if you have the stamina after a day-full of technology, Applied Materials, Coventor and Synopsys are holding seminar/receptions between 5 and 8 pm. The Applied Materials event is at the Parc 55 hotel just around the corner from the Hilton, on “Rethinking Scaling: New Paradigms, New Approaches”, and Coventor is looking at the back-end “BEOL Barricades: Navigating Future Semiconductor Yield, Reliability and Cost Challenges”, in the Union Square rooms on the 4th floor of the Hilton. The Synopsys reception is around the corner at the Serrano Hotel from 6 – 8 pm.


Session 25: Process and Manufacturing Technology — Beyond Conventional CMOS

25.1 looks at the contribution to source/drain resistance made by interfaces such as the p-SiGe/p-Si interface, and also studies the n-Si/n-Ge, n-InAs/n-Si and n-InAs/n-Ge interfaces.

The second paper examines the effects of doping HfO2 with different ions, both cations and anions, in order to influence and predict ferroelectric properties; and demonstrates an N-doped dielectric layer in a ferroelectric FET (25.2).

Next up is a description of an AgTe/TiO2-based threshold switching (TS) device that can be integrated with a conventional BEOL (25.3). When switched on, a conductive silver filament forms, and when switched off, the filament dissolves and conduction stops. A TiN liner is put between the AgTe and the TiO2 to prevent silver diffusing into the TiO2 during BEOL processing; a steep subthreshold slope of less than 5 mV/decade is claimed.

Schematic and TEM image of the integrated TS transistor (25.3)

Schematic and TEM image of the integrated TS transistor (25.3)

We live up to the theme of “Beyond Conventional CMOS” in 25.4; here we have InGaAs-on-insulator MOSFETs, fabricated by direct wafer bonding (DWB)and epitaxial lift-off techniques, aimed at monolithic 3D integration; and in addition, the InP donor wafer can be re-used.

We stay with wafer bonding in 25.5, but in the photonics realm; an InGaAsP/Si hybrid MOS-based phase shifter formed on a Si photonics platform by using DWB is described.

The last talk of the session is an invited one, by Janos Veres of Xerox PARC; “Additive Manufacturing for Electronics “Beyond Moore””. The ability of additive manufacturing and 3D to change the paradigm of electronics production will be discussed. 

Session 26: Sensors, MEMS, and BioMEMS — N/MEMS for Physical, Chemical, and Bio-sensing

A solid-state pH and chloride sensor is formed from iridium oxide (IrOx) and silver chloride (AgCl) electrodes fabricated on a Si substrate in 26.1, with a microfluidic reference electrode incorporated. 26.2 describes the use of a spin-transfer torque operated magnetic tunnel junction (STT-MTJ) to make a thermal sensor more than 0 times faster than a traditional CMOS thermal sensor.

Next Chae Ahn from Stanford gives an invited talk (26.3) on the challenges of encapsulating MEMS timing reference devices, with particular reference to those produced by SiTime Inc; and the influence of the thickness of a tribo-dielectric layer on the performance of a tribo-electric energy harvester is described in 26.4.

In 26.5 we look at a brain probe which uses neuron-sized LEDs to stimulate the neuronal proteins with light instead of electrically. Micro-LEDs and electrodes are integrated on thin silicon probes formed by micro-machining to give a four-probe opto-electrode which can be inserted into the target area of the brain.

The four shanks of an optoelectrode with its tips are shown (26.5), with the LEDs illuminating. The inset (left) shows a SEM view of a tip.

The four shanks of an optoelectrode with its tips are shown (26.5), with the LEDs illuminating. The inset (left) shows a SEM view of a tip.

The effect of Lamb waves (sound waves confined to a thin layer) on the two-dimensional electron gas (2DEG) in an AlGaN/GaN heterostructure are studied in 26.6, generating an acousto-electrical effect that results in DC current flow between contacts on the acoustic layer.

In 26.7 a micro-oven is used to control a CMOS-MEMS oscillator, with a built-in temperature detector for self-test and resonator temperature monitoring; and in the last talk (26.8), self-assembled perfluorodecyl-triethoxysilane (PFDTES) is used as an anti-stiction coating on the contacting parts of a nano-electro-mechanical relay. 

Session 27: Memory Technology — MRAM

Hynix and Toshiba kick off the session with a joint paper (27.1) on a 4-Gb perpendicular SST-MRAM (spin-transfer-torque magnetic random access memory) with a 9F2 cell area. The vertical stack and a plan-view SEM image of the MTJ array are shown below, clearly using some of the techniques used in DRAMs, such as buried wordlines.


Just eyeballing the scale bar on the SEM image, it looks like the MTJ cell diameter is ~50 nm, which compares with ~60 nm in a 20-nm DRAM.

This is followed by a Samsung exposition (27.2) of an 8-Mb STT-MRAM embedded into the BEOL of their 28-nm logic process, again using a perpendicular MTJ (pMTJ). Third up (27.3) is a study of data extraction methods for perpendicular SST-MRAM, to evaluate retention as cell size decreases from 250 nm to 50 nm in diameter.

Qualcomm and Applied Materials shrink the pMTJ cell size even further in 27.4, down to 25 nm, studying the properties in 1-Gb arrays. 27.5 is an examination of a voltage-torque MTJ MRAM; and in the last paper (27.6) Toshiba describes another voltage-controlled MTJ, with volts used to select bits, and spin-torque to write.

Session 28: Circuit and Device Interaction — Technology Elements for 5nm Logic Platform and Advanced Automotive/IoT Applications

Samsung manages to integrate strained Si-channel NMOS and SiGe-channel PMOS finFETs in 28.1, using a buried strain-relaxed SiGe buffer layer to create tensile-strained NMOS and compressively-strained PMOS devices. The gate stack uses a common interfacial layer, high-k, and metal gate, without dual-work-function metals, and a simplified multi-Vt module.

Imec (28.2) discusses a 5-track standard cell (Intel’s 14-nm uses 7.5-T cells) optimized for finFETs and horizontal nanowires, using single-fin design and air-gap spacers. Stanford and ARM analyse a 32-bit processor core designed with 5-nm design rules (28.3), looking at transistor and interconnect technologies.

In the next paper (28.4), a new method of near-threshold-voltage (NTV) design optimization for FinFETs is developed, and demonstrated based on silicon data using Vdds of 199 and 145 mV.

In 28.5 Xilinx looks at high-speed analog circuits, and presents an optimized MOS varactor design and finFET model; both were validated in a 16-nm finFET process in a high-speed transceiver design.

The final talk is an invited review of “Embedded Flash Technology for Automotive Applications”, by T (Tadashi?) Yamauchi from Renesas, including the integration of their split-gate MONOS eFlash into a 28-nm HKMG process.

Session 29: Compound Semiconductor and High Speed Devices — Ultra-High Speed Electronics

This session is a special focus session, again consisting of invited papers on TeraHertz technology and applications:

  • 29.1InP HEMT Integrated Circuits Operating Above 1,000 GHz,” by W.R. Deal et al, Northrop Grumman
  • 29.2A 130 nm InP HBT Integrated Circuit Technology for THz Electronics,” by M. Urteaga et al, Teledyne Scientific Co./SungKyunKwan University
  • 29.3Resonant-Tunneling-Diode Terahertz Oscillators and Applications,” by M. Asada and S. Suzuki, Tokyo Institute of Technology
  • 29.4Physics of Ultrahigh Speed Electronic Devices,” by M. Shur, Rensselaer Polytechnic Institute
  • 29.5InP/GaAsSb DHBTs for THz Applications and Improved Extraction of their Cutoff Frequencies,” by C.R. Bolognesi et al, ETH-Zurich
  • 29.6On-Chip Terahertz Electronics: From Device-Electromagnetic Integration to Energy-Efficient, Large-Scale Microsystems,” by R. Han et al, MIT/Office of Naval Research/Cornell University/University of Michigan/STMicroelectronics/University of Texas at Dallas/Naval Research Lab
  • 29.7Active Terahertz Metasurface Devices,” by H.T. Chen, Los Alamos National Laboratory
  • 29.8Devices and Circuits in CMOS for THz Applications,” by Z. Ahmad et al, University of Texas at Dallas/NXP Semiconductors/MIT/SeoulTech/Texas Instruments/MediaTek/IDT/Wright State University /UT Southwestern Medical Center/Ohio State University/ UConn Health

Session 30: Modeling and Simulation — Steep Slope Devices and Nanowires

The first paper is a TSMC study of III-V ‘broken gap’ nanowire TFETs (30.1), claiming a 58x gain increase over a Si MOSFET; followed by simulations of TFETs at Vdds of 0.08 – 0.18V (30.2).

Then we have more TFET analyses, this time of the band-tails in 2D devices (30.3), and resonant tunnelling characteristics of inter-layer TFETs with multiple tunnel barrier layers (30.4).

30.5 demonstrates models of ferroelectric negative capacitance finFETS; 30.6 examines the performance of ultra-thin body III-V finFETS and nanowires with 15 and 10.4 nm gate lengths, confirming that GAA-NWs is the only viable architecture below 10.4 nm; and the final paper is a look at vertically-stacked NW-FETs for sub-10 nm nodes (30.7).

Session 31: Characterization, Reliability and Yield — Reliability Modeling and Characterization of Dielectrics and Interfaces

In 31.1 IBM Research studies the electronic defect states at the interface between a compress SiGe channel and the interlayer dielectric of p-FETs. Samsung also looks at SiGe p-FETs (31.2), assessing the effects of acceptor traps on negative-bias temperature instability (NBTI), and coming to the conclusion that they can lower the oxide electric field and improve the NBTI performance.

Next up is a characterization of Ge p- and n-MOSFETs with an Al2O3/GeOx/Ge gate stack (31.3), followed by the presentation of a new model for looking at NBTI and PBTI (31.4). SMIC and Peking U. review the gate dielectric reliability of TFETs in 31.5, and IBM Research is back (31.6) with a model for gate oxide progressive breakdown in n- and p-FETs

We switch topics to the back-end in an investigation by TSMC (31.7) of AC TDDB (time-dependent dielectric breakdown) in BEOL extreme low-k (ELK) dielectric in (presumably) their 10nm technology.

The final talk is a presentation on the use of self-healing in gate electrodes in silicon GAA-NW FETs (31.8), aiming at electronics for deep space missions.

Session 32: Optoelectronics, Displays, and Imagers — Thin Film Transistors for Imaging and Displays

We start the session with a demonstration of an active artificial iris (32.1) built on a contact lens, and formed solely of thin-film components. It comprises an organic thin-film photovoltaic mini-module as a power supply/integrated illumination sensor; a flexible thin-film a-IGZO circuit as a driver chip; and a liquid crystal display which acts as the iris. Such a device can help with iris deficiencies that can bring great discomfort and extreme photosensitivity for sufferers.

A “smart” contact lens system, comprising an integrated display, energy harvesting components, communication antenna, sensors and more (32.1).

A “smart” contact lens system, comprising an integrated display, energy harvesting components, communication antenna, sensors and more (32.1).

In 32.2 an elevated-metal metal-oxide (EMMO) thin-film transistor (TFT) is proposed that can also act as an etch-stop layer in a high-resolution display stack. 32.3 is a proof-of-concept study, forming polysilicon TFTs on paper, sintering a liquid silicon solution at 100 oC or below.

Next up in 32.4 is Adrien Pierre of UCal. Berkeley, giving an invited talk on “High-detectivity Printed Organic Photodiodes for Large Area Flexible Imagers”, followed by a report on dual-gate a-Si:H fin-TFTs (32.5), which have photosensitivity when operated sub-threshold.

While not conventional TFTs, FD-SOI n- and p-FETs can be light-sensitized by putting a diode in the substrate below the transistors (32.6). The photo-generated carriers in the diode can create a back-bias, shifting the threshold voltage of the transistors. This capability was used to demonstrate a light-controlled SRAM.

Then – lunch! IEDM and IEEE Women in Engineering have organised their annual Entrepreneurs Luncheon, which will feature Vamsee Pamula, co-founder of Baebies, Inc. a company developing digital microfluidics technology for newborn screening and pediatric testing.

In parallel, ASM is hosting their usual Wednesday lunchtime seminar at the Nikko Hotel across the street from the Hilton, this year the topic is “Covering 3D Devices”.

And be back in the Hilton for the afternoon sessions, beginning at 1.30 pm.

Session 33: Process and Manufacturing Technology — Ge Channel Devices

We start with CVD-grown Ge/GeSn/Ge quantum well (QW) p-MOSFETs with transverse uniaxial tensile strain, reportedly giving ~7% mobility enhancement leading to a record high mobility (33.1). The CVD process enables a low thermal budget of 400oC.

The second presentation is invited – Seiichi Miyazaki of Nagoya U. is speaking on “Processing and Characterization of Si/Ge Quantum Dots” (33.2), detailing their research on silicon quantum dots with a germanium core.

Then we explore (33.3) high performance Ge CMOS with quantum well-structured channels a single MoS2 capping layer. The MoS2 confines the carriers within the Ge layer, reducing scattering at the dielectric interface and improving performance.

33.4 demonstrates a silicon-passivated Ge NMOS gate stack, with LaSiO doping at the HfO2/SiO2 interface, that is compatible with 3D structures and has improved PBTI reliability and electron mobility.

The fifth paper of the session discusses Ge finFETs fabricated by neutral beam etching and oxidation, which gives low-defect, smooth surfaces and improved performance compared with conventional reactive ion etching (33.5).

Lastly, there is a description of junction-less GAA n-FETs that use selective laser annealing on epi-Ge on SOI (33.6).

Session 34: Nano Device Technology — Devices Based on Quantum and Resistive Switching Phenomena

Now we get into the realm of quantum dots and qubits; in 34.1 we hear a study of coupled phosphorus donors with MOS quantum dots, giving two-axis control of a two-electron spin logical qubit. 34.2 deals with silicon-based charge qubits with coherence times and operating temperatures two orders of magnitude larger than other reported semiconductor systems.

Nanomagnet networks are explored in 34.3, which are apparently ideal for Ising computing (a method of solving combinatorial optimization problems). VO2 is used for a two-terminal hysteretic voltage switch in 34.4, since it can be voltage-induced to change from metal to insulator and back; in this case it is applied to analogue signal processing.

The same phenomenon is utilised to make low-voltage artificial neurons, that can be voltage-scaled down to 0.3 V (34.5), and threshold switches made with Ag/HfO2 are used as selector switches for PCM-based cross-point memory in 34.6.

Atom-switches (atomic-scale metal-filament switches) are integrated with silicon MOSFETs (34.7) to give ‘atom-switch FETS’ with extremely low leakage current, low operating bias, and sub-threshold swing of less than 5 mV/decade.

The last paper of the day (34.8) presents two dimensional (2D) RRAM devices using multilayer hexagonal boron nitride (h-BN) as the active switching layer; the cyclical release and diffusion of B ions are the key physical mechanisms responsible for switching, forming a boron (B)-deficient conductive filament.

Session 35: Circuit Device Interaction — 3D Systems, Enabling Technologies and Characterizations

This session starts with an invited talk by Fabien Clermidy from CEA-LETI (35.1), reviewing “New Perspectives for Multicore Architectures using Advanced Technologies”, showing how back-end NVM, monolithic 3D integration (CEA-LETI’s CoolCube), and 3D stacking can be used to build more power-efficient systems.

TSMC expands on their InFO (integrated fan-out) technology to build inductors into the stack for integrated voltage regulators to couple with their 16-nm finFET devices (35.2). The InFO substrate was used in volume in the iPhone 7 series, so it will be interesting to see how it has evolved – we already have silicon-based trench capacitors included in the package.

35.3 discusses on-chip high-Q magnetic inductors for power conversion efficiency greater than 90%; 35.4 examines ESD diodes in a bulk GAA-NW process; 35.5 characterizes the hold-time margins of flip-flop arrays across a range of process/temperatures/voltage/aging conditions in Intel’s 22-nm finFET process.

The last presentation models the thermal resistance of the back-end interconnect and finFETs in face-up and face-down formats (35.6).

Session 36: Modeling and Simulation — Materials and Interfaces

The effects of surface roughness scattering (SRS) and how it limits carrier mobility in finFETs and GAA-NW FETs are modelled in 36.1, and the performance improvement in GaN devices given by nitridation is investigated in 36.2.

Manipulating Spin Polarization and Carrier Mobility in Zigzag Graphene Ribbons using an Electric Field” is the topic of an invited lecture by Christophe Delerue of IEMN (36.3). Density functional theory simulations were performed on HfO2/SiOxNy/SiGe stacks with a range of Si/O/N compositions (36.4), and measured experimentally, confirming that lower defect density results from a sub-stoichiometric SiON layer.

36.5 examines PBTI in InGaAs NW-FETS with Al2O3 and LaAlO3 gate dielectrics; simulations seem to show that Al2O3 performs better than LaAlO3.

Contact resistivities in n-type III-V materials are given more extensive modelling in 36.6, indicating higher contact resistivity than earlier models. The last paper (36.7) investigates the transport mechanisms of diamond-like carbon films, since these are now becoming of interest for high-voltage devices. A polarization effect was modelled in a TCAD tool, giving good agreement with experiments.
Chronologically the last paper is due at 4.30 pm – by then a lot of attendees will have headed for home, especially West-coasters who want to get home today.

We should not forget the exhibitors, either – at the time of writing we have:

Cambridge Press

Celadon Systems



Global TCAD

GMW Associates

Park Systems


Proplus Design Solutions




The exhibits are open all three days of the conference, with free coffee available – seeing as there are no coffee breaks during the sessions, it might be good to take time out and change pace in the exhibit area.

I will definitely be suffering from information overload at the end, and becoming brain-numb; but with 233 papers and an average of six parallel sessions at any one time, plus the offsite events, that’s not really surprising. On the other hand, where else do we go to get all this amazing stuff?

Time to unwind, maybe do a little holiday shopping, and go for an indulgent meal.



  • -J. Cho et al., “Si FinFET Based 10nm Technology with Multi Vt Gate Stack for Low Power and High Performance Applications”, VLSI 2016, pp. 12 -13.

IEDM 2016 Next Week!

By Dick James, Senior Technology Analyst, Chipworks

On December 3rd – 7th , the good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2016 IEEE International Electron Devices Meeting. To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.”

That’s a pretty broad range of topics, but from my perspective at Chipworks, focused on the analysis of chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy.

In the last few weeks I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.


Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorials on a range of leading-edge topics:

The first three are from 2.45 – 4.15, and the remainder from 4.30 – 6.00. This year I hope to make it to the Physical Characterization session, and possibly the IoT talk at 4.30.

On Sunday December 14th, we start with the short courses, “Technology Options at the 5-Nanometer Node” and “Design/Technology Enablers for Computing Applications”.

Last year the process short course was “Emerging CMOS Technology at 5 nm and Beyond”, so I guess we will see how things have evolved at 5 nm.

The course has been organized by An Steegen and Dan Mocuta of Imec. They introduce it bright and early, at 8.30 a.m.

The first session is “Nano Patterning Challenges at the 5nm Node”, given byAkihisa Sekiguchi of Tokyo Electron. Next up is Nadine Collaert from imec, discussing “Novel Channel Materials for High-Performance and Low-Power CMOS”, followed by Aaron Thean, of the National University of Singapore (and formerly imec),who is presenting on “Options beyond FinFETs at 5nm node”.

Contacts are the next topic, “Low Resistance Contacts to Enable 5nm Node Technology: Patterning, Etch, Clean, Metallization and Device Performance”, by Reza Arghavani of Lam Research.

The back-end stack gets more critical as dimensions shrink, so we have a review of “Parasitic R and C Mitigation Options for BEOL and MOL in N5 Technology”, by Theodorus Standaert from IBM.

The last session covers off “Metrology Challenges for 5nm Technology”, by Applied Materials’ Ofer Adan – given that we are now counting atoms, challenging is a good way to describe it.

John Chen of Nvidia set up the Design/Technology short course, which takes a fairly high-level look at the technologies involved in processing Big Data, discussing the different processors themselves, the effects of memory, managing the power and connectivity, and where advanced packaging fits in.

So we have:

  • The Rise of Massively Parallel Processing: Why the Demands of Big Data and Power Efficiency are Changing the Computing Landscape” – Liam Madden, Xilinx
  • Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: a Design and Technology Perspective” – Gabriel Molas, Leti
  • Power Management with Integrated Power Devices…and how GaN Changes the Story” –Alberto Doronzo, Texas Instruments
  • Interconnect Challenges for Future Computing” – William J. Dally, NVIDIA/ Stanford U
  • Advanced Packaging Technologies for System Integration” – Douglas Yu, TSMC

I would call both courses a full day, seeing as we finish at ~5.30 p.m., but it’s worth sticking around to the end.

If you have the stamina, at 6.00 CEA-Leti is hosting a Devices Workshop at the Nikko Hotel, across the street from the Hilton.


Monday morning we have the plenary session, with three pertinent talks on the challenges and potential of contemporary electronics:

  • “Technology Scaling Challenges and Opportunities of Memory Devices” – Seok-Hee Lee, Hynix
  • “Brain-Inspired Computing” Dharmendra S. Modha – IBM
  • “Symbiotic Low-Power, Smart and Secure Technologies in the age of Hyperconnectivity” – Marie-Noëlle Semeria, Leti

Three quality presentations in three hours, but beware of numb bum if you take in all of them – get up and have a stretch in between, and take a walk before lunch!

After lunch, in keeping with IEDM’s tradition of intellectual overload, we have seven parallel sessions!

Session 2: Circuit and Device Interaction — Advanced Platform Technologies – including 7 nm finFETs!

Session 2 starts a track on Circuit and Device Interaction, in this case with papers on Advanced Platform Technologies – for me a highlight session, since the session ends with duelling 7-nm late-news papers from TSMC (2.6) and the Samsung/GLOBALFOUNDRIES (GF)/IBM consortium (2.7).

In addition, we have a GF/Leti discussion of the GF 22FDX SOI technology (2.2) announced last year; paper 2.3 is a research paper on 3D monolithic integration of ultra-thin body MOSFETs into a VCO and power management circuit, with a 4-layer Vertical ReRAM, by Taiwan’s National Nano Device Laboratories and National Chiao Tung University.

GF co-authors the next two papers, detailing a high-resistance SOI technology for RF front-end modules (2.4), integrating a power MOSFET with a RF switch by using selective silicon thinning; and (2.5) a look at monolithic 3D IC design partitioning to mitigate the performance limits set by the limited thermal budget of the upper transistor level in the 3D IC stack.

In 2.6, TSMC announces the “world’s first 7nm CMOS platform technology for mobile system-on-a-chip (SoC) applications, featuring FinFET transistors”. They claim the world’s smallest-ever SRAM cell at 0.27 µm2, and 3x the gate density of the 16-nm process, together with a 35 – 40% speed gain or over 65% power reduction.

In addition, the process uses 93nm immersion lithography, raised source/drain epi, a novel contact technique, and a 12-layer copper/low-k interconnect stack.

By contrast, the finFETs in 2.7 from the GF/IBM/Samsung group consortium (presumably at Albany, NY) were manufactured using EUV, with contacted polysilicon pitch (CPP) of 44/48nm, and metallization pitch of 36nm. It also features dual-strained channels formed on a thick strain-relaxed buffer (SRB) virtual substrate to give tensile-strained NMOS and compressively strained SiGE PMOS for the enhancement of drive current by 11% and 20%,  respectively, when compared with a common planar (my italics) HKMG process. Epitaxy is used in the contact trenches to minimize resistance.

Schematic (center) of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with TEM images of (a) the tensile-strained silicon fin and (b) the compressively-strained SiGe fin on a common SRB (2.7).

Schematic (center) of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with TEM images of (a) the tensile-strained silicon fin and (b) the compressively-strained SiGe fin on a common SRB (2.7).

Session 3: Compound Semiconductor and High Speed Devices — Compound Semiconductors for High Speed RF and Low Power Logic Applications

The session starts with a paper (3.1) from Germany’s IHP Institute, on their (claimed) fastest silicon-based heterojunction bipolar transistor (HBT), with an fT/fmax of 505 GHz/720 GHz, respectively, at 1.6 V; they attribute this to optimized vertical profiles of the emitter-base-collector regions, the use of “flash” annealing and low-temperature backend processing to lower base and emitter resistance, and lateral device scaling.

TEM image of a cross-section of an optimized Si HBT device (3.1).

TEM image of a cross-section of an optimized Si HBT device (3.1).

Lund University is up next (3.2), discussing InGaAs tri-gate MOSFETs with record on-current of 650 µA/µm at 0.5 V. Paper 3.3 is an invited talk on “High Frequency GaN HEMTs for RF MMIC Applications”, from HRL Labs.

In paper 3.4, MIT studies a new form of instability due to F- migration and the passivation/depassivation of Si dopants in a n-InAlAs cap layer in InGaAs MOSFETs; it turns out that removing the cap layer gets rid of the instability!

MIT also presents paper 3.7, on using a physical compact model to improve the RF circuit linearity performance of GaN HEMTs, in both device and circuit design techniques. GaN HEMTs are again discussed in 3.5, this time W-band N-polar devices; UCal Santa Barbera claims a record high efficiency of 27.8% at 94 GHz.

And to fill in the gap at 3.40 pm (3.6), IBM gives an invited talk on “Monolithic Integration of Multiple III-V Semiconductors on Si for MOSFETs and TFETs”, using template-assisted selective epitaxy (TASE) for a number of III-V compounds.

Session 4: Memory Technology — RRAM, PRAM and Applications

We start with an invited talk “Towards Ultimate Scaling Limits of Phase-Change Memory” (4.1) by Feng Xiong of Stanford U., reviewing advances in phase-change memory (PCM), which is now down to sub-10 nm scale, with switching energies approaching femtojoules per bit.

Paper 4.2 discusses confined ALD-based PCM with a metallic liner, which is reported to have record endurance of 2e12 cycles; and 4.3 looks at SiOx-based RRAM (Resistive Random-Access Memory) in crossbar memory arrays, and also as select devices in the arrays.

Oxygen implantation into Ta2O5 and HfO2 is used to form RRAM devices in the ON state (4.4), which subsequently switch similarly to regularly made reference devices. The correlation between endurance, window margin and retention of RRAM types (oxide RAM and conductive bridge RAM) is studied in 4.5, and the effect of programming parameters on oxide RAM retention is the topic in 4.6.

The intrinsic variability factors of RRAM are quantified in 4.7, to identify the fundamental variability limits of the technology, and the last paper (4.8) details a random number generator fabricated in Panasonic’s 40-nm embedded ReRAM process.

Session 5: Nano Device Technology — 1D and 2D Devices

This session (not surprisingly) is a set of research papers, starting with a pair of carbon nanotube (CNT) transistor studies; 5.1 details CNT-FETs with nickel contacts alloyed into the ends of the CNTs to reduce contact resistance and give scalability to the contact process.

Schematic of a CNT-based CMOS inverter with entirely Ni end-bonded contacts (5.1)

Schematic of a CNT-based CMOS inverter with entirely Ni end-bonded contacts (5.1)

We look at vertically suspended CNT-FETs in 5.2, which allows a fully gate-all-around (GAA) structure with multiple channels, optimising gate controllability and enhancing charge transport.

In 5.3 we move to graphene FETs, again examining ways of reducing contact resistance, this time using “atomic orbital overlap engineering”.

Paper 5.4 is an invited talk from Mathieu Luisier of ETH Zurich on simulations of 2-D devices, reviewing mobility, I-V characteristics, and contact resistance, with extra detail on contacts to molybdenum disulphide (MoS2).

Black phosphorus is another potential 2-D transistor material, and PMOSFETs with a boron nitride/alumina gate dielectric are discussed in 5.5.

The last three papers focus on MoS2, examining 10-nm top-gated transistors in 5.6, and we go beyond transistor studies in 5.7 to develop guidelines for co-optimisation of material, devices, and circuits, to get the yield up and move towards manufacturability. The final paper (5.8) gets back into the detail of the MoS2 MOS interface trap density created by S vacancies in the MoS2.

Session 6: Sensors, MEMS, and BioMEMS — Focus Session: Wearables for the Internet-of-Things (IoT)

As a focus session, this features a series of seven invited presentations;

  • High Performance, Flexible CMOS Circuits and Sensors Toward Wearable Healthcare Applications,” by K. Takei, Osaka Prefecture University (6.1)
  • Circuits and Systems for Energy-Efficient Smart Wearables,” by A. Sharma, Texas Instruments (6.2)
  • Flexible Metal-Oxide Thin-Film Transistor Circuits for RFID and Health Patches,” by P. Heremans et al, Imec/University of Leuven/Holst Centre (Belgium)/National Centre for Flexible Electronics (India) (6.3)
  • Challenges and Opportunities in Flexible Electronics,” by R. D. Bringans and J. Veres, Xerox PARC (6.4)
  • Advanced Integrated Sensor and Layer Transfer Technologies for Wearable Bioelectronics,” by D. Shahrjerdi et al, New York University (6.5)
  • Wearable Sweat Biosensors,” by A. Javey et al, University of California, Berkeley (6.6)
  • Flexible Metamaterials, Comprising Multiferroic Films,” by Y. P. Lee et al, Hanyang University (6.7)
Schematics and example of wearable sweat sensor from paper 6.6

Schematics and example of wearable sweat sensor from paper 6.6

Session 7: Modeling and Simulation — Advanced Numerical and Compact Models

The first paper details an electro-thermal compact model for self-heating ICs, including the BEOL, that can predict front-and back-end reliability, and takes account of interconnect layout and geometry (7.1).

In 7.2 we hear about a model that considers the percolation path of the channel current in a transistor to help understand the statistical variability and reliability in nanoscale devices, and compares the different features of 3-D finFETs with planar transistors.

HfOx-based analog synaptic devices are considered in 7.3; the SET, RESET, and retention loss processes are simulated and given experimental verification, capturing the key material parameters and forming optimization guidelines.

P-channel GaN MOSHFETs are the topic in 7.4, examining the electric field distribution to determine why a higher threshold voltage needs reduced channel and oxide layer thicknesses. This led to the introduction of an AlGaN cap layer to modulate the field and increase the on-current.

We move to GAA-MOSFETs in the next presentation, modelling stacked-planar and vertical transistors of circular, square, and rectangular cross-sections (7.5). Then we change technologies again and look at the resistive switching behaviours of CBRAM devices (7.6).

CBRAMs use the property that if amorphous insulating materials contain a relatively large amount of metal, the metal ions they contain can form a conductive path when voltage is applied; this can be reversible, enabling the storage of data as the conductor appears and disappears. The paper studies three modes of filament formation.

3-D cross-point memory cells formed using germanium-selenium telluride (GST) are discussed in the last paper of the session (7.7), extending the model to simulate memory array circuits.

Session 8: Optoelectronics, Displays, and Imagers — Imaging and Photon Counting Sensors

The first paper in the session presents a backside-illuminated (BSI) single photon avalanche diode (SPAD) image sensor (8.1), a claimed first in the field. Most of the CMOS image sensors (CIS) in smartphone cameras these days are BSI, usually with stacked dies and through-silicon vias (TSVs), although the very latest use face-to-face wafer bonding of the metal interconnects.

It looks as though this device also uses stacked dies, since the SPADs are fabbed in a 65-nm process, and the processor is 40-nm.

SPADs are getting attention lately since they are also appearing in mobile phones in time-of-flight auto-focusing devices for the cameras, and in the latest iPhone they are doing double duty as a proximity sensor and autofocus for the selfie camera; see my last blog for more details.

STMicroelectronics time-of-flight sensor from iPhone 7

STMicroelectronics time-of-flight sensor from iPhone 7

Paper 8.2 is also focused on SPADs, in this case a 256 x 256 image sensor with 16 µm pixel pitch and a 61% fill factor. Then we have an invited talk from M.Mori of Panasonic (8.3), discussing “An APD-CMOS Image Sensor Toward High Sensitivity and Wide Dynamic Range”; followed by Sony (8.4) showing off their latest die stacking using copper/copper hybrid bonding connecting the image sensor to the image processor (also known as direct bond interconnect (DBI).

We at Chipworks actually found this technology in the Samsung Galaxy S7 Edge back in March, so it is definitely in volume production.

SEM cross-section of Sony image sensor from Samsung Galaxy S7 Edge, showing copper/copper direct bonding

SEM cross-section of Sony image sensor from Samsung Galaxy S7 Edge, showing copper/copper direct bonding

Next up is a global shutter CIS (8.5) which somehow has 480 analog memories/pixel integrated using vertical analog memory technology, which enables 1 Mfps.

In 8.6, Canon exhibits one of their huge 35-mm full-frame sensors, this time a low-noise global shutter device with a 6.4 µm pixel size. Apparently, most CMOS imagers use a rolling shutter, which reads the pixels at different times at different parts of the imager, leading to image artifacts, especially for moving targets (see image below of vibrating ukulele strings).

8.6 Canon

The last paper is another from Sony (8.7), this time detailing a “Four-Directional Pixel-Wise Polarization CMOS Image Sensor Using Air-Gap Wire Grid on 2.5-µm Back-Illuminated Pixels”. If I understand the abstract correctly, this sensor has a wire grid with 150-nm pitch over the pixels which acts as a polarizer, presumably in the four directions of the grid sides.

That is the end of the Monday afternoon sessions, and the reception will start at 6.30 pm in the Grand Ballroom; but if you have links to Stanford U, there is a gathering at 5 before then.


Session 9: Process and Manufacturing Technology — 3D Integration and BEOL

The session starts (9.1) with a discussion of 3D-stackable finFETs compatible with back-end processing, using single-grained silicon fins and laser spike anneal to keep the thermal budget down.

We have seen the use of liquid surface tension for die positioning and self-assembly in years past; in 9.2 we have it applied to 2.5/3D integration of multiple types of die, even those with uneven surfaces and bottom topography.

Next we have an invited presentation (9.3) by Ruth Brain of Intel, on “Interconnect Scaling: Challenges and Opportunities”, focusing on the transistor/interconnect optimization that is necessary now that interconnect delay is dominating circuit performance.

Paper 9.4 looks at a high-k MIM decoupling capacitor aimed at the 7-nm node; and 9.5 discusses graphene-on-copper for improved interconnectivity and enhanced electro-migration lifetime. The last paper (9.6) explores the intriguing concept of vertical-channel devices gated by TSVs.

Session 10: Power Devices — Power Semiconductor Device Technologies

We get into the world of GaN devices in the first four papers – 10.1 details a normally-off V-trench GaN transistor formed on a GaN substrate, with a record 1.7 kV breakdown voltage and on-state resistance of 1.0 mΩcm2; 10.2 describes a vertical GaN Schottky rectifier incorporating trench MIS structures and field rings; 10.3 is about GaN gate injection transistors with high-speed switching, again built on a GaN substrate; and 10.4 presents on high-performance enhancement-mode GaN MIS-FETs with a recessed-gate structure and a SiNx gate dielectric.

Schematic cross-section of lateral p-type GaN transistor with slanted channel (10.1)

Schematic cross-section of lateral p-type GaN transistor with slanted channel (10.1)

Next we have an invited talk (10.5) on “Superior Performance of SiC Power Devices and Its Limitation by Self-heating” by T. Terashima of Mitsubishi Electric, followed by a paper looking at the 3D scaling of IGBTs (10.6), giving lower on-resistance.

The last two papers go back to SiC devices, with a description of a vertical p-type SiC MOSFET with enhanced breakdown voltage (10.7), and 10.8 is a study of hysteresis in subthreshold drain current in SiC n-MOSFETs, caused by hole capture in border traps.

Session 11: Memory Technology — Charge Based Memories and Scaling

In this second session of the Memory track, we move to other forms of memory and embedded memory. Renesas and Hitachi have worked out a way to build split-gate MONOS flash on finFETs (11.1); then Samsung gives an invited review “A New Ruler on the Storage Market: 3D-NAND Flash for High-density Memory and its Technology Evolutions and Challenges on the Future” (11.2). We have seen 3D-NAND flash go from 24 – 32 – 48 – 64 layers in the last four years, and all four of the flash manufacturers are now in volume production; this review should cover off that evolution, as well as discuss some of the challenges as the process complexity increases.

Macronix has stated that they plan to join the 3D-NAND business, and in 11.3 they study instability caused by the grain boundaries in the polysilicon channel of vertical flash structures. Another invited talk is next, this time by Bosch (11.4), discussing the qualification of non-volatile memories (NVM) for automotive applications, and the resulting requirements for the NVM supplier, and the implications for design and technology of NVMs.

Paper 11.5 is a study of a ferroelectric transistor (FeFET) based eNVM retrofitted into GLOBALFOUNDRIES’ 28SLP HKMG process using an extra layer of SiHFO inserted into the transistor gate stack.

TEM cross-sections of GF 28SLP transistors (left), and FeFET device (right), showing the extra SiHfO layer (11.5)

TEM cross-sections of GF 28SLP transistors (left), and FeFET device (right), showing the extra SiHfO layer (11.5)

The next paper (11.6) has an intriguing abstract – how to convert ZrO2-based DRAMs (i.e. most DRAMs) into NVMs – I look forward to the details! The last talk details a tantalum-oxide based selector device that can be formed in a crossbar array, and fitted into the back-end process sequence (11.7).

Session 12: Nano Device Technology — Negative Capacitance and New Material MOSFETs

In this session we have a series of papers on ferroelectric negative capacitance (NC) devices, mostly using HfZrOx. The first describes a NC-finFET with a 1.5-nm thick HfZrOx layer (12.1), then we have HfZrOx germanium (Ge) and Ge-tin p-MOSFETs (12.2), followed by a study on a HfO2 NC-FET, looking at its polarization-limited operating speed (12.3).

12.4 simulates sub-10-nm NC-finFETs, showing excellent short-channel performance; 12.5 examines InGaAs MOSFETs with a La2O3 dielectric, revealing that La2O3 can have ferroelectric properties, and can be used to form NC-FETs; and 12.6 analyzes the hole and electron effective masses in the inversion layers of Ge (100), (110) and (111) p- and n-MOSFETs.

Session 13: Optoelectronics, Displays, and Imagers — Focus Session: Quantum Computing

This Focus Session features invited papers describing several technologies to fabricate quantum bits (qubits), including transmon qubits, spin qubits in silicon, and FDSOI qubit technology with silicon nanowire field-effect transistors. There are also discussions of quantum technologies based on luminescent crystalline defects in diamond, and the prospects of scalability, considering the potential fabrication of large-scale systems with millions of qubits.

  • Quantum Computing Within the Framework of Advanced Semiconductor Manufacturing,” by J. S. Clarke et al, Intel/TU Delft
  • Spin-Based Quantum Computing in Silicon CMOS-Compatible Platforms,” by A.S. Dzurak, University of New South Wales
  • Coupled Quantum Dots on SOI as Highly Integrated Si Qubits,” S.Oda, Tokyo Institute of Technology
  • SOI Technology for Quantum Information Processing,” by S. De Franceschi et al, CEA/University Grenoble Alpes
  • Cryo-CMOS for Quantum Computing,” by E. Charbon et al, Delft University of Technology/EPFL/Institut Superieur d’Electronique de Paris/Tsinghua University/Univ. California, Berkeley
  • Diamond–A Quantum Engineer’s Best Friend,” by Marko Lončar, Harvard University
  • Large-Scale Quantum Technology Based on Luminescent Centers in Crystals,” by M. Trupke et al, TU Wien/University of Vienna/Nippon Telegraph and Telephone/National Institute of Informatics (Japan)

Session 14: Modeling and Simulation — 2D Materials and Organic Electronics

Back in session 5 we had some MoS2 papers, and 14.1 is a study on two MoS2 transistor types, a lateral heterostructure FET and a “planar barristor”; then we have an invited review (14.2) of “Physics of Electronic Transport in Two-dimensional Materials for Future FETs” by Massimo Fischetti from U. Texas (Dallas).

Next up is an atomic-scale simulation of silicon contact with MoS2 (14.3), and 14.4 is an examination of graphene/semiconductor contacts for a range of materials. Paper 14.5 predicts the performance of InAs, InN, InP and InSb double-gate, single-layer n- and p-type transistors; and 14.6 is an invited review of the “Current Status and Challenges of the Modeling of Organic Photodiodes and Solar Cells”, by R.R. Clerc of the Institut d’Optique Graduate School.

The session finishes with a discussion of ultra-thin nanowire gated 2D-FETs, focusing on dielectric growth and channel formation (14.7). In one example, a thin (6nm) conformal Al2O3 dielectric was formed around Co2Si nanowires on a carrier wafer, and were then gently pressed against a MoS2 substrate to transfer them – this avoids having to deposit the dielectric on the MoS2. The curvature of the nanowire ensures that only a short section of it is in contact with the 2D layer, creating a short channel length.

Schematic illustration of a nanowire-gated 2D FET (left), and TEM cross-section of a fabricated device (14.7)

Schematic illustration of a nanowire-gated 2D FET (left), and TEM cross-section of a fabricated device (14.7)

Session 15: Characterization, Reliability and Yield – FINFET and Nanowire Device Reliability

Samsung is first up this session, characterizing the reliability of their 10-nm process technology (15.1). They presented the basics of it at VLSI at VLSI this year [1]; they described it as:

“Fin and dummy Si gate were defined by sidewall image transfer using a mandrel and sidewall space. 3rd generation Fin features more vertical and thinner shape than previous technologies, which allows for stronger control of the short channel effect. Highly doped S/D with 3rd generation epitaxial process is combined with advanced contact process to boost performance. Copper interconnects were fabricated using conventional immersion bi-directional patterning and CVD-liner process.”

And these are some of the design rules:

Samsung VLSI

In addition to reliability studies, the paper will describe describe process optimizations that overcome problems such as self-heating effects caused by the taller and narrower fin shape.

TSMC contributes an invited talk (15.2) on a similar topic “Consideration of BTI Variability and Product Level Reliability to Expedite Advanced FinFET Process Development”, and we get into serious detail in 15.3 with a statistical model of NBTI degradation of p-finFETs.

IBM reports on hot-carrier reliability in gate-last SiGe-channel p-finFETs in 15.4, and we have a post-mortem study of dielectric breakdown in finFETs in 15.5, including TEM/EELS/EDX analysis; and, according to the abstract “The assumption that the kinetics of failure would remain the same for both planar and FinFET devices is proved to be untrue.”

15.6 is an imec review of self-heating in finFETS and gate-all-around nanowires (GAA-NWs), and 15.7 continues the theme, exploring thermally-aware transistor design to reduce self-heating of floating-body devices such as FD-SOI, SOI-finFETS, and GAA-NWs.

We finish with an invited presentation (15.8) on nano-thermometry, using an AFM-based tool to look at localized hot spots in nano devices.

Session 16: Circuit and Device Interaction – Resistive Device Designs for von-Neumann Computing and Beyond

One of the trends in recent years has been the application of resistive RAM for neuromorphic computing; it appears that RRAM memories have the advantage in that they can hold a range of resistive states that can correspond to the “shades of grey” in human thinking.

The second session in this track continues that theme. The first paper examines the use of vertical RRAM for language recognition (16.1). Here, the RRAM is vertically oriented, whose physical structure corresponds to the team’s hyper-dimensional computing algorithm. This 3D-VRRAM allowed the computing framework to recognize words in 21 different languages from sample texts.

The next paper (16.2) details a binary neural network using 16-Mb RRAM devices for image recognition; 16.3 discusses a novel non-volatile flip-flop with a single RRAM NVM included; 16.4 describes a 50 x 20 crossbar switch block with two a-Si/SiN/a-Si varistors for non-volatile FPGAs; and a 4-transistor NV-SRAM with two RRAMs (4T2R, instead of the usual 6T SRAM cell) is fabricated in TSMC’s 40-nm process in 16.5.

16.6 is a higher-level study of a fully connected neural network using arrays of OxRAM devices, and applying short- and long-term plasticity rules, suitable for (e.g.) visual pattern extraction from highly noisy data.

Image reconstruction is used as a diagnostic tool to evaluate the device variability in memristor crossbar arrays in 16.7, and 16.8 demonstrates unsupervised learning by spike-time dependent plasticity (STDP) and spike-rate dependent plasticity (SRDP) in neural networks using CMOS-based RRAM synapses.

Finally, it’s time for lunch! This year’s speaker at the conference lunch is Prof. Roberto Cingolani from the Istituto Italiano di Tecnologia in Genoa, Italy, presenting on “Translating evolution into technology: from biochemical robots to autonomous anthropomorphic machines”. We are used to the concept of living creatures evolving over time – here we will have a comparison between living and artificial systems, and the attempts to reproduce the characteristics of living things using technology.

Tickets are available online when you register – if you haven’t, there are usually some at the conference front desk. The afternoon sessions start again at 2.15.

Part 2 of the preview will be up in a few days, before the conference!