Monthly Archives: November 2011

IEDM 2011 Preview

Next week the researchers and practitioners of the electron device world will be gathering in Washington D.C. for the 2011 IEEE International Electron Devices Meeting. To quote the conference web front page, “IEDM is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. The conference scope not only encompasses devices in silicon, compound and organic semiconductors, but also in emerging material systems.”

From my perspective at Chipworks, focused on chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

In the last few days I’ve gone through the advance program, and here’s my pick of what I want to try and get to, in more or less chronological order. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.

For the first time the conference starts on the Saturday afternoon, with a set of six 90-minute tutorials on a range of leading-edge topics:

  • Microresonator Filters and Oscillators: Technology and Applications, Roy H. Olsson III, Sandia
  • Graphene Nanoelectronics, Walter De Heer, Georgia Tech
  • Modeling and Characterization of Noise in Advanced CMOS, Andries Scholten, NXP
  • Technology CAD for Modeling and Design of Bio-Devices, Yang Liu and Robert Dutton, Stanford University
  • Kinetic Energy Harvesting – Technologies and Applications, Tomasz Zawada, Meggitt
  • IGBT and Superjunction – Leading Power Device Technologies, Florin Udrea, University of Cambridge  

The first three are from 2.45 – 4.15, and the remainder from 4.30 – 6.00. I won’t make it to any of them; dedicated nerd I may be, but I want at least some of my weekend!

On Sunday December 4th, we start with the short courses, “VLSI Technology Beyond 14nm Node” and “Advanced Memory Technology”. Philip Wong of Stanford of has organised the former, and we have some impressive speakers – Jeff Sleight, (IBM – Nanowires), Shinichi Takagi, (U Tokyo – High Mobility Materials), Alan Seabaugh, (U Notre Dame – Tunnel FETs), Ian Young, (Intel – MOSFET extrinsic R-C parasitics), and long-time attendee Bill Arnold (ASML – Lithography).

As I said last year, having started in the business on 10-micron geometries, 14-nm devices seem crazy to me, but on the Intel clock it’s only two – three years away! I’m starting to tell folks to think about the end of silicon, at least as we know it, since my brain will not wrap around the idea of 11- and 8-nm gates, and 11-nm is only five years away (and 30 – 40 atoms across, depending on orientation!). The guys in the R&D labs have been thinking about that for the last decade or more (as we’ve seen at IEDM), so this should be an interesting day to see what they’ve come up with and how we get there.

Roberto Bez of Micron has set up the other short course; now that we are getting into the 1x-nm flash (literally counting electrons) and 2x-nm DRAM eras, conventional scaling has probably reached its limits, and other storage mechanisms have to come into play. S.Y. Cha of Hynix kicks off the sessions with a review of DRAM technology, followed by Y.J. Choi (Adata) on NAND flash. The we get into the alternative mechanisms with Rainer Waser (RWTH-Aachen) on redox-based ReRAM, Janice Nickel (HP – Memristors), Andrea Lacaita (Politecnico Milano – Phase Change Memory), and Bill Gallagher from IBM finishing up on magnetic memories.

So some good solid stuff – although the courses make a long Sunday, from 9 a.m. to 5.30 p.m., but it’s worth sticking around to the end.

Monday morning we have the plenary session, with three pertinent talks on the challenges of contemporary electronics:

  • Approach Towards Achieving Sustainable Mobility by Takumi Matsumoto, Toyota Inc. – given the trend towards electric vehicles, and Toyota’s lead in that arena, this should be illuminating;
  • Perspective on The Past, Present and Future of Transistors by Mark Bohr, Intel – the big question here, of course, is will Mark give us any clues on the upcoming 22-nm trigate product? I’m inclined to doubt it – we’ll have to wait and see!
  • Various Technologies of MRAM and Logic-in-Memory Architecture Based on Hybrid CMOS/Magnetic Technology by Bernard Dieny, CEA – another perspective on where memory is heading. 

After lunch we have seven parallel sessions coming up! Session 2 gets straight into the way-ahead material with papers on graphene and nano-optical devices, although we seem to be moving away from R towards D in the R&D spectrum; for example, paper 2.2 from IBM builds graphene-based RFICs on 200 –mm wafers. Jim Montgomery at ElectroIQ has posted more details here.

Session 3 details phase-change and resistive memories, with papers on a 20-nm PRAM by Samsung (paper 3.1), and a 4F-sq cell 1-Gb PCRAM by Hynix (3.3). Session 4 provides the first of the inter-session clashes, with a paper (4.1) on 14-nm finFET circuit/device interactions from GLOBALFOUNDRIES.

In session 5, Asen Asenov’s device modelling group at the University of Glasgow has a paper on variability and reliability in finFETS (5.4), and IBM (5.5) discusses transistor matching and SOI thickness variation in extra-thin SOI (ETSOI).

There are a couple of interesting analytical papers in session 6; scanning spreading resistance measurement on a finFET by IMEC (6.1), and electron holography mapping of an under-30-nm MOS transistor. IBM starts session 7 with TSVs integrated with what looks like a 32-nm HKMG/e-DRAM process (7.1), and Renesas reports BEOL transistors using an InGaZnO channel integrated into the copper interconnect (7.4) – a different form of 3D!

Session 8 focuses on image sensors, and seeing that we do a lot of CMOS image sensor (CIS) reports, we won’t want to miss those – in particular papers from Sony (8.1), TSMC/Omnivision (8.2) and Panasonic (8.3). Sony discusses a flat (no STI in the array), 1.12-µm pixel CIS, possibly the one we’ve seen in the Apple iPhone 4S. Omnivision, who have had a lot of wins with Apple (but not the 4S!), talk about a 0.9-µm pixel back-illuminated CIS, and Panasonic’s paper is on a front-illuminated sensor fabbed in a 45-nm process using light pipes, with claimed performance better than back-illuminated sensors.

Tuesday morning we start with session 9 on flash memories: Hynix (9.1) discusses their “middle 1x-nm” (15 nm?) flash, now with air gaps similar to Micron’s paper last year; Macronix studies a thin (less than10 nm thick) floating gate at less than 20 nm (9.2), and Infineon reviews the use of embedded flash in uses such as automotive microcontrollers and smart cards (9.4).

Energy harvesting and ultra-low power is the topic of session 10, with a set of invited papers on thermoelectric, MEMS, and RF energy harvesting , and the types of device that could use such low energy supplies.

The other four morning sessions are predominantly academic; graphene and ultimate device modelling (S11), memory reliability (S12), InGaAs FETs (S13), and thin film technology (S14).

The speaker at the conference lunch will be Masaaki Tsuruta of Sony Entertainment, so we will likely see what’s coming up in the gaming experience – whole body sensors?

Session 15 in the afternoon is nominally about circuit/device interaction, but there are a couple of Samsung papers describing processes; paper 15.1 discusses their 20LP process, but the abstract does not say whether it’s gate-first or gate-last – it should be gate-last, but we’ll see! 15.6 talks about process improvements that enhance scalability of the 28LP gate-first HKMG process. There are two invited papers, by ARM (15.4) and STMicroelectronics (15.7), that get more into circuit/device interaction, ARM discussing scaling problems from the design perspective, and ST presenting process-design co-optimization at the 28-nm node, including TSV integration.

Sessions 16 – 19 are also at the academic end of the spectrum, with papers on Simulation of Memory Devices (S17), HKMG reliability (S18), and GaN devices (S19).

Session 20 gets into RF MEMS and resonators, starting with an invited paper from IDT (20.1) on MEMS oscillators (looks like they’re making MEMS as well, now). Nitronex, known for their GaN-on-Si RF transistors, are detailing a ~800 MHz MEMS resonator (20.3).

At the end of the afternoon Applied Materials is hosting a panel on “How will RAM Change for the Mobile Computing Era?” for a couple of hours. The panelists will be:

          Dr. Narbeh Derhacobian – president and CEO, Adesto Technologies, Corp.
          Dr. Gyoyoung Jin – senior vice president, Samsung Microelectronics, Ltd.
          Dr. Jae-Sung Roh – research fellow, Hynix Semiconductor, Inc.
          Dr. Gurtej Sandhu – senior fellow, Micron Technology, Inc.
          Dr. Klaus Schuegraf – chief technology officer, Applied Materials, Inc.
          Dr. Geoffrey Yeap – vice president of technology, Qualcomm, Inc.

Get registered here.

In the evening we have the conference panel sessions, “Is 3 Dimensional Integration at Best a Niche Play?”, and "Will SiC or GaN Replace Si as the Semiconductor for Power Devices?" – do panels always have to ask questions to get us interested?

In a way the three panels reflects the diversity of the business now – we tend to forget the huge range of applications these days, from the latest logic and memory nanotechnology in our smartphones, to the demands of bringing high-voltage DC power in from offshore wind-farms. I shall probably bounce back and forth between the two conference panels, they again have good speakers, and the 3D one has Jan Vardaman to keep them grounded – I don’t think she’s seen real 3D yet any more than we have at Chipworks.

Wednesday morning has sessions 23 – 29; S23 on carbon nano-tubes and Si-nanowire devices, which inevitably takes the academic track; S24 covers RAM and specialty memories, which is also a touch academic, but Samsung (24.1) discusses vertical spin-transfer torque MRAM, something we probably have to watch for in the not-too-distant future. IBM has two consecutive papers on their “racetrack memory” (24.2 and 24.3), and TSMC finishes up the session with a HKMG embedded DRAM in 28-nm technology using MIM capacitors (24.7).

Low voltage design and device variability is covered off in S25 – the “Albany consortium” (GLOBALFOUNDRIES, IBM, Infineon, Renesas, Samsung, STMicroelectrics, Toshiba, in alphabetical order) has a potentially interesting paper (25.6) on a layout dependency effect in HKMG which could read on the AMD Llano chip analysis we did a few weeks ago.

Now we get into scheduling clashes with S26 – TI has a stacked-die NexFET power module (26.1) which should be interesting, and Panasonic has two papers, the first (26.2) on a low-leakage GaN-based multi-junction diode, and the second (26.6) describes a SiC MOSFET which somehow uses the channel as a diode current path. Rohm also has an invited paper on SiC trench transistors (26.5).

Session 27 deals with MOSFET reliability, specifically bias-temperature instability, mobility and noise, and is a bit beyond me; however, S28 has some meat in it for advanced CMOS geeks.

In paper 28.1 the GLOBALFOUNDRIES/IBM, Infineon/Samsung/Toshiba group discusses their dual-channel (Si/SiGe) HKMG gate-first technology that we saw a version of in the AMD Llano. Later on IBM/GloFo describe an atomic layer oxidation technique for a gate-last process (28.5). Sony, Panasonic and Fujitsu in conjunction with IMEC also have a dual-channel HKMG paper (28.6), but this time in both gate-first and gate-last versions. There is also a review paper by UTokyo on germanium CMOS (28.4).

I shall be torn between paper 28.1 above, and Benedetto Vigna’s invited paper on MEMS sensors (29.1) at the same time. Benedetto has shepherded STMicroelectronics into the leading position in consumer MEMS in the last five years or so, so it’s likely that whatever phone or game system you have will have an ST motion sensor in it.

Lunchtime Wednesday, ASM will be holding a seminar across the road at the Churchill Hotel, with Ivo Raaijmakers hosting; and I have the privilege of speaking on “High-k/Metal Gate in Leading-Edge Silicon Devices”. To register, email Roseanne de Vries at [email protected].

The pace continues in the afternoon with session 30 on nano device technology, session 31 on resistive RAM, S32 on advanced SRAM, S33 on III – V FETs, S34 on simulation, S35 on high mobility, and S36 on biosensing and solar conversion.

Papers of interest for me in the RRAM session are 31.2 on HfO-based RRAM, bipolar ReRAM by Panasonic (31.4), a WOx RRAM by Macronix (31.5), and a vertical RRAM by Samsung (31.8).

Session 32 has one of the seven papers by Intel at this IEDM (32.1), on low-voltage SRAM operation (but no paper on 22-nm trigate transistors!). Suvolta and Fujitsu may come out of stealth mode and show details of their channel engineering and associated VDD reduction in paper 32.3.

Another Intel paper co-authored with substrate maker IQE (33.1) looks farther ahead at hi-k tri-gate InGaAs quantum-well FETs, and the same groups discuss a tunneling FET (33.6) in the last paper of the session.

In session 34, IMEC and Panasonic have a SiGe channel paper (34.3), and, as noted in my last blog, Intel sheds some light on their NMOS stress mechanism seen in their 32-nm process (34.4) – or at least, that’s my speculation!

Session 35 starts with another Intel/IQE paper, this time comparing MOVPE and MBE III-V quantum-well FETs on Si substrates (35.1). The Sony/Panasonic/Fujitsu/IMEC group have another paper (35.4), detailing a Ge-Sb-Te liner for putting compressive stress on PMOS finFETS. SEMATECH and CNSE discuss an ultra-shallow doping technique for finFETs (35.5), and IMEC/Panasonic/Ultimate Junction Tech. also talk finFET doping (35.6), this time specific to NMOS.

The last paper of the session (35.7) has NU Singapore and Varian describing what looks like a fairly complex way of tuning nickel silicide contact resistance by implanting aluminum, and locking into place with carbon. They claim an 18% drive current improvement for nFETs; so complex it may be, but it’s another way of pushing up performance, and processes are plenty complex already!

The conference finishes about 5 pm – by then a lot of attendees will be heading for home, and I’m usually thankful when the last paper’s done. As always, no peace for the curious!

Last year the SOI Industry Consortium held a workshop starting at 5 p.m. after the conference proper was finished, with some notable speakers from academe and industry. I haven’t heard anything of a similar event this year, but I will post an update to the blog with the details if I do.

On a completely different note, I have grudgingly joined the Twitterverse, so any Twitterati can follow me at @chipworksdick, I will be trying to post interesting industry tidbits. I can’t say I’ve ever been particularly good at one-liners, but we’ll see!

Intel clarifies 32nm NMOS stress mechanism at IEDM 2011

I was browsing through the advance program for the upcoming IEDM conference when, almost at the end, I came across paper number 34.4, "Modeling of NMOS Performance Gains from Edge Dislocation Stress," by Weber et al. of Intel. According to the abstract: "Simulations show stress from edge dislocations introduced by solid phase epitaxial regrowth increases as gate pitch is scaled, reaching over 1GPa. This makes edge dislocations attractive, as stress from epitaxial and deposited film stressors reduces as pitch is scaled. We show dislocation stress varies with layout and topography."

The abstract doesn’t have much detail, but it does re-enforce the teachings from a Samsung paper at last year’s IEDM conference, paper 10.1, "Novel Stress-Memorization-Technology (SMT) for High Electron Mobility Enhancement of Gate Last High-k/Metal Gate Devices" (Lim et al.).

The essence of this paper is that if you give the source/drains a deep amorphization implant, and then anneal to create solid-phase epitaxial re-growth with a tensile stress liner in place, then crystalline dislocations are formed adjacent to the gate edge, which apply tensile stress to the channel.

Source: IEDM/Samsung

Like the embedded SiGe stress for PMOS, this works better with a gate-last process, since the surface is not locked by a polysilicon gate. Samsung claimed ~1% lattice distortion, verified by nano-beam diffraction measurements. A vertical slice was taken below the center of the gate and the color coding shows strain of ~1%:

Source: IEDM/Samsung

When I saw this paper it made me wonder if this mechanism was what we had been seeing in the Intel 32nm parts; none of the earlier stress mechanisms seemed to being used. Intel were the first to apply stress to transistor channels at the 90nm node, using (for NMOS) the contact etch-stop layer (CESL) silicon nitride; and then at the 45nm node they evolved to using the contact plug itself and the gate-fill metal, since the CESL is almost gone.

But in the 32nm process the contact plugs have been polished away, and there is less gate metal (since it’s a smaller gate) — so what is supplying Intel’s fourth-generation strain?

In the light of these two papers we can now take a good guess when we see what Intel’s 32nm NMOS transistor looks like:

And as we can see, there are stacking faults on both sides of the gate, and they look similar to the ones in the image from the Samsung paper:

Source: IEDM/Samsung

Samsung claimed an increase in electron mobility of 40%-60% and drive current improvement of over 10%.

Stacking faults are not normally what we want to see in transistors, because they can be leaky if they go through a junction, but as long as they are contained within the source/drain diffusions, they should not be a problem. They are certainly in every NMOS transistor that we imaged (though given the billions of transistors in the millions of processors shipped, we cannot exactly claim a large sample).

At an intuitive level it makes sense that this mechanism should work — a stacking fault is a missing layer of atoms within the crystalline lattice, and we are now working with channel lengths of a hundred atomic spacings or less. So if a couple of atomic layers are missing at opposing ends of the channel, it seems logical that tensile stress would be induced in the channel.

Like the other stress techniques, this only works now that we are down in the nanometer range, but the good thing about this one is that the applied strain should increase as the channel length gets shorter.

So it seems that we have finally deduced at least some of what Intel are doing in their 32nm NMOS transistors. Now, of course, the question will be — can it be transferred to the trigate structures we’re looking forward to in the 22nm process?

Looking forward to IEDM, in addition to the conference program, ASM will be holding a lunchtime seminar on the Wednesday, Dec. 7th, at 12 noon, with Ivo Raaijmakers hosting; and I have the privilege of speaking on "High-k/Metal Gate in Leading-Edge Silicon Devices." To register, email Roseanne de Vries at [email protected]. We hope to see you there!