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Intel announces tweaks to 22FFL process for RF, MRAM at IEDM18

By Dick James

At IEDM last year, Intel gave a half-dozen papers on various topics, including two on their 22FFL SoC process aimed at low power IoT and mobile products. The first (14.1) was an invited presentation on “Intel 22nm FinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit Design Optimization for FinFET Technology”, and the second (18.1) introduced “MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology”. I had planned to cover the two papers in one article, but it expanded to the point where it made more sense to split it into two parts. So, here is the first part on the RF enhancements to the 22FFL process.

Part 1 – Initial 22FFL and RF Enhancements

Initial 22FFL Announcements

Mark Bohr announced the 22FFL process at the Technology and Manufacturing Day (TMD) at the end of March in 2017. At the time they said that it was “Fully RF design enabled”, but gave no more details, and MRAM as an option was not mentioned. More details were given at IEDM 2017 [1], but again no discussion of MRAM. The basic process details as stated at TMD were:

The raw dimensions, as you’d expect, are in between the 14-nm and 22-nm processes. The logic transistor images shown at IEDM17 indicate that 22FFL is based on the 14-nm technology, since we no longer have the tapered fins, and the punch-stop seal is present:

TEM images of logic transistor; parallel to gate (left) and parallel to fin (right)

The fins are still double-patterned, but the gate and metal are single-patterned, and the SRAM cell size puts it close to the 22-nm node. If we use the 45 nm fin pitch as a calibration, the fin heights come out at 36 – 38 nm, and fin width ~7 nm, giving a gate width of 80 – 85 nm. That is similar to the 22-nm fins and compares with ~42 nm fin height at 14-nm.

The base process combines high-performance, low power, and ultra-low power logic, analog, and high-voltage (HV) transistors [1]:

The high-performance transistors show 57%/87% higher NMOS/PMOS drive current compared to the 22-nm technology. The use of the punch-stop diffusion means that the fins are undoped, so Vt is set by adjusting gate length and work function for the various devices. As shown in the table, the HV transistors have thicker gate oxide and longer gate lengths.

TEM images of 1.8 V I/O transistor; parallel to gate (left) and parallel to fin (right)

When it comes to the RF capabilities, a device with optimized layout was developed and showed fT/fMAXof 230 GHz/284 GHz and 238 GHz/242 GHz for NMOS and PMOS respectively, with a 32 nm gate length.

Other SoC features in 22FFL are high resistance substrate, deep N-well isolation, precision resistors, MIM capacitors, and high-Q inductors. The relaxed metal pitch of the single-patterned back end results in reduced parasitics at the sacrifice of density – a good tradeoff for RF SoCs.

RF Modifications

In this year’s RF paper [2], five flavors of RF transistor are offered; nominal and low VTlow-leakage, nominal and low VThigh-density, and high-performance (HP). A drawback of FinFET technology is the increased lateral parasitic capacitance given by the extra gate material between the fins – as the poly pitch gets tighter, the capacitance increases, lowering fT, without increasing transconductance (𝑔𝑚). This effectively means that the 22-nm process is better suited to RF applications than smaller or larger nodes.

fT and fMAX vs process node: both peak around 20 ~ 25 nm

A known phenomenon of finFETs is self-heating, where the fin temperature increases while conducting current, made worse by the thermal isolation of the fin. This impacts temperature-dependent parameters such as mobility and threshold voltage, resulting in performance degradation, and endangering device and interconnect reliability. The effect can be reduced by operating at lower current densities or supply voltages, potentially trading off performance for reliability. Since finFETS have better channel control than planar devices, we can keep strong drive current at low supply voltages, enabling high performance low-voltage designs without reducing reliability.

Another feature of finFETs is the additional vertical component of the gate resistance; this non-linear resistance allows the designer to optimize devices for fTor fMAXby tuning the configuration of fins and gate legs.

Schematic of finFET gate capacitance and resistance structure: horizontal (Rh) and vertical (Rv) resistances surrounding fin structures

As a result, the HP NMOS fT has been pushed over 300 GHz, and the fMAXbeyond 450 GHz, and PMOS to just under 300 GHz.

RF performance of HP transistors optimized for peak fT (left) and peak fMAX (right)

The Intel paper does not give any data on the number of fins or gate legs for the devices described, but I found this simulation [3] based on Intel’s published figures for their initial 22-nm process, i.e. with trapezoidal fins [4]. Using the same effective gate width, it gives an indication of the influence of the fin and gate finger configuration on RF performance. One presumes, looking at these fTnumbers (fT >750 GHz for 20 fins), that there are significantly fewer fins in the 22FFL transistors quoted, with an fTof ~300 GHz.

fT vs. numbers of fingers and fins; the finger number for each different fin number is adjusted to give the same device width [3].

For low-noise amplifier (LNA) designs, noise matching and power matching can be tuned by regulating the input impedance, adjusting the number of fins for a particular device sizing.

Below we see three cases of fin configuration, maintaining total device size by changing the number of gate fingers. The maximum available gain 𝐺𝑚𝑎𝑥and the minimum noise figure 𝑁𝐹𝑚𝑖𝑛vary with the fin number, so the LNA figure of merit (FoM = 𝐺𝑚𝑎𝑥– 𝑁𝐹𝑚𝑖𝑛) also varies. In this case the FoM maximum is in 4- or 6-fin devices; 𝐺𝑚𝑎𝑥and𝑁𝐹𝑚𝑖𝑛were normalized to the 𝐺𝑚𝑎𝑥and 𝑁𝐹𝑚𝑖𝑛of a 2-fin device.

Device sizing for optimum LNA FoM; 4 or 6-fin devices reach highest equivalent FoM at ~0.3mA/um current density.

While the above figure shows relative 𝑁𝐹𝑚𝑖𝑛, other work [5] shows that the noise figure is below 2 dB up to 73 GHz, suitable for a mm-Wave receiver LNA. 

Plot of simulated 𝑁𝐹𝑚𝑖𝑛 vs. frequency [5]

When it comes to flicker (1/f) noise, FinFETs have inherently lower drain-induced barrier lowering (DIBL) compared with planar transistors, and we have the punch-through-stop diffusion in 22FFL, so there are no VT adjust implants, and likely no halo implant, both of which help generate flicker noise. By comparison, an equivalent planar transistor is at least 10x greater.

Flicker noise of 22FFL high performance logic transistors [1]

We will see what products come out in the RF-enhanced 22FFL, but with 5G looming up and Intel getting design wins in iPhones, there does seem to be potential, and Intel has clearly been working on the technology. 


  1. Sell, et al., “22FFL: A High Performance and Ultra Low Power FinFET Technology for Mobile and RF Applications”, IEDM Tech. Dig. 2017, pp. 685 – 688.
  2. -J. Lee, et al., “Intel 22nm FinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit Design Optimization for FinFET Technology”, IEDM Tech. Dig. 2018, pp. 316 – 319.
  3. An, et al., “Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance”, Journal of Semiconductor Technology and Science, vol.14, no.5, Oct. 2014.
  4. Auth, et al., “A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors,” Proc. VLSI Tech. 2012, pp. 131-132.
  5. Callender, et al., “FinFET for mmWave – Technology and Circuit Design Challenges”, Proc. BCICTS 2018, pp. 168 – 173.

The Packaging of Apple’s A12X is… Weird

By Dick James

Watching the video from the new iPad Pro launch back on October 30, there was a pseudo assembly sequence within it. Being the teardown nerd that I am, I kept running through it until I got a set of screen shots that showed the motherboard being populated, one of which was:

In the centre is what one presumes to be the A12X; but it looks like a half-package, together with what could be a couple of DRAM packages. Consequently, we zoom in, and get this:

It’s very pixelated, but we have what looks like half of a BGA package with a metal lid, and what again looks like two DRAM packages. No A12X marking, but iPad Pros usually have a lidded BGA for their A-X-series chips, and the packages alongside and their markings look real, and suspiciously like Micron DRAM – nothing is actually legible.

So, what looks like more package innovation from Apple, with no publicity as usual, and given that this is the launch video, and could be different from reality, I parked my speculation until TechInsights did their teardown.

They confirmed what Apple showed, we have some sort of unusual A12X packaging going on;

And if we look in close-up, we can see that there are two SK Hynix LPDDR4 DRAMs (H9HCNNNBRMMLSR-NEH, 4 GB total) adjacent to an abbreviated lidded BGA package of some sort, on a custom substrate, mounted onto the motherboard; 

The package dimensions are ~ 23.8 x 26.3mm.

They also took the assembly off the motherboard, so that we can look at the base.

Out of curiosity, I also looked at the iFixit teardown, and the boards look exactly the same, but their version has Micron DRAM (Micron MT53D256M64D4KA, 4 GB total) paired with the A12X, a reflection of Apple’s multiple sourcing for memory. Both options are using 2 x 16 Gb parts, which could be 2 x 8 Gb dies in each package, or possibly 4 x 4 Gb.

We can see that the two A12X parts have the same APL1083 part number, and even the same 1834 date code, but the more detailed device numbers are slightly different; the TechInsights sample is 339S00567, and the iFixit version is 339S00569.

TechInsights also did their customary x-ray, and the shadow of the thermal interface material (silicon is almost transparent to x-rays) gives us an estimated die size of ~10.4 x 13.0 mm (~135 mm2). There appear to be some ceramic passive components under the lid, and likely four silicon-based capacitors located on the base of the substrate. While the x-ray does confirm that we have three packages on a common substrate, it is odd that the BGA does not have any visible solder balls showing up in the image.

The DRAM packages clearly show their solder pattern meshing with that of the substrate; no such thing under the Apple chip. I can think of two reasons for that – the A12X package has exactly the same ball grid as the substrate (seems unlikely); or the assembly is truly a lidded BGA with the die flip-chipped conventionally onto the substrate under a truncated metal top, and the memory FBGAs mounted beside it. 

Looking at the perspective image above, it seems clear that the latter is the case. We can see the Micron DRAMs in the foreground, and the lid of the A12X package sits directly on the substrate, as it would do in a standard lidded BGA package.

In mobile phones we have had DRAM and application processor (AP) in package-on-package (PoP) configuration since the first iPhone, to save space and reduce delay time between the processor and memory, and power dissipation is relatively low so heat transfer is less of a concern, allowing the PoP stack. In tablets, they generate more heat, and space is less critical, so APs typically have a lidded package with the DRAM on the motherboard close by. This shot of the A10X shows what I mean.

However, the memory latency has to be inherently larger in this layout, and one of the innovations we have expected in this context is to see the memory flip-chipped on to the same substrate; though I, at least, expected to see that in a phone first, to reduce package height.

That would be a form of 2.5D packaging, but silicon interposers or Intel’s EMIB technology (using an embedded interconnect die) are likely too expensive for Apple’s taste. Organic interposers are cheaper, but still in their early days commercially.

Here we have a compromise – take a regular lidded BGA, cut off half the lid, and place the memory packages on the same BGA substrate. We have the advantages of good heat dissipation, and really close placing of the memory to the AP for minimal delay, and it is also likely the cheapest option. Flip-chip memory on the substrate for a 4 GB model would likely require two 16-Gb dies, which if they are available, would be more expensive.

To see what is really going on, we will have to wait until one of the analysis companies shows us a cross-section. We were right – more innovative packaging from Apple!

IEDM 2018 Coming Up!

This is Part 1 of a multi-part blog series of previews of the upcoming IEDM 2018 conference.

By Dick James

On December 1st– 5ththe good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2018 IEEE International Electron Devices Meeting.  To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.”

That’s a pretty broad range of topics, but from my perspective, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy.

In the last few weeks I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order. However, at this point I need to confess that I have run short of time to finish this review so as to get it posted before the conference, so I have to break with tradition and skip a few of the sessions and papers that I will not be getting to. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.


Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorialson a range of leading-edge topics:

  • Emerging Device Technologies for Neuromorphic Computing, Damien Querlioz, CNRS
  • Reliability Challenges in Advanced TechnologiesRyan Lu, TSMC
  • Quantum Computing PrimerMark B. Ritter, IBM
  • Design-technology Co-optimization at RF and mmWave, Bertand Parvais, Imec
  • STT-MRAM Design and Device Requirement, Shinichiro ShiratakeToshiba Memory
  • Power Transistors in Integrated BCD Technologies, Hal Edwards, Texas Instruments

The first three are from 2.45 – 4.15, and the remainder from 4.30 – 6.00.

On Sunday December 2nd, we start with the short courses, “Scaling Survival Guide in the More than Moore Era” and “It’s All About Memory, Not Logic!!!”.

Last year the process short course was “Boosting Performance, Ensuring Reliability, Managing Variation in sub-5nm CMOS” so I guess we are now getting away from numbers, and the topics indeed show that:

  • Extreme-UV lithography – Principles, Present Status and OutlookTony Yen, ASML
  • MOSFET Scaling Knobs (GAA, NCFET…) and Future AlternativesWitek Maszara, GLOBALFOUNDRIES
  • Overcoming Variation ChallengesSivakumar Mudanai, Intel
  • 3D Integration for Density and FunctionalityJulien Ryckaert, imec
  • Advanced Packaging: the Next Frontier for Moore’s “Law”Subramanian Iyer, UCLA
  • Embedded Memory: Present Status, and Emerging Architecture and Technology for Future Applications, Eric Wang, TSMC

This year’s effort is organized by Jin Cai (TSMC). The memories session has been set up by Nirmal Ramaswamy of Micron, with the following sessions:

  • DRAM : Its Challenging History and FutureDong Soo Woo, Samsung
  • 3D Flash Memories: Overview of Cell Structures, Operations and Scaling ChallengesMakoto Fujiwara, Toshiba
  • Emerging Memories including Cross-Point, Opportunities and ChallengesKiran Pangal, Intel
  • Memory Reliability, Qualification and their Relation to System Level Reliability StrategiesTodd Marquart, Micron
  • Future of the Packaging Technologies for HBM, Nick (Namseog) Kim, SK Hynix
  • Processing in Memory (PIM): Performance and Thermal Challenges and OpportunitiesMircea Stan, University of Virginia

I would call both courses a full day, seeing as we finish at ~5.30 p.m., but it’s worth sticking around to the end.

If you have the stamina, at 5.30 CEA-leti is holding a Devices Workshopacross the street at the Nikko Hotel, discussing “Disruptive and Highly Secure Technologies for Data Management” and at6.00 imec is hosting a networking event  “Imec’s Tech Excellence and Belgian Beer & Gastronomy” at the Parc 55 hotel.


Monday morning, we have the plenary session, with three pertinent talks on the challenges and potential of contemporary electronics:

  • 4th Industrial Revolution and Foundry: Challenges and Opportunities, Eun Seung Jung, President of Foundry Business, Samsung Electronics

If we accept that the 3rd Industrial Revolution is our current era of information technology (computers, internet, etc.), then it is arguable that the 4th Industrial Revolution will be the fusion of the physical and cyber worlds (artificial intelligence, smart cars, homes, factories, etc).

In that context, we are likely to see larger than ever volumes of semiconductors being used, and this talk looks at the semiconductor ecosystem and the role of foundries in the 4th Industrial Revolution, the technological challenges involved, and possible solutions.

  • Venturing Electronics into Unknown Grounds,Professor Gerhard P. Fettweiss, Center for Advancing Electronics Dresden (cfaed), TU Dresden

cfaed is a German Cluster of Excellence located in Dresden, focused on stretching the limits of electronics into new territory. This presentation describes their methodology, combining horizontal research approaches with vertical studies of materials, devices, circuits and systems; and reviews the research topics of the center.

  • Future Computing Hardware for AI Jeff Welser, Vice President and Lab Director, IBM Research – Almaden

As we’ve seen at earlier IEDMs, hardware is being developed for artificial intelligence at both the chip and system level – neuromorphic memories, high-bandwidth CPUs, specialized AI accelerators, and high-performance networking gear. Dr. Welser will detail the hardware needs of AI, considering possible specialized technologies for AI, such as heterogeneous digital von Neumann machines, reduced-precision accelerator techniques, analog cores, and quantum computing.

Three quality presentations in three hours, but beware of numb bum if you take in all of them – get up and have a stretch in between, and take a walk before lunch!

After lunch, in keeping with IEDM’s tradition of intellectual overload, we have nine parallel sessions, and continuing this year – exhibitors, and coffee breaks to give us time to talk to them.

Session 2:Memory Technology – Charge Based Memories

Session 2 starts a track on Memory Technology, the first of four sessions. It begins with an invited paper by Intel/Micron on Scaling Trends in NAND Flash(2.1), updating us on 3D NAND, going from 32 to 64 and 96 layers, and 3 bits/cell to 4 bits/cell; and the problems involved for further scaling.

In 2.2, Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory, Macronix investigates the operation of triple-level cell (TLC) and quad-level cell (QLC) charge-trap storage 3D NAND flash memories, concluding that random telegraph and program noise are the main influencers on the upper and lower Vt limits. A multi-times verify (MTV) scheme was tested and found to improve performance.

The authors in 2.3(Implementing Spike-Timing-Dependent Plasticity and Unsupervised Learning in a Mainstream NOR Flash Memory Array) report operating a mainstream NOR Flash array as an artificial synaptic array, demonstrating spike-timing-dependent plasticity (STDP) and unsupervised learning. Word-lines and bit-lines were pulsed to trigger hot-hole injection (HHI) or channel hot electron injection (CHEI) at the drain side of the cells in a conventional 40-nm double-polysilicon embedded technology.

Macronix is back again (2.4, A Novel Voltage-Accumulation Vector-Matrix Multiplication Architecture Using Resistor shunted Floating Gate Flash Memory Device for Low-power and High-density Neural Network Applications) describing the use of a buried-channel shunt resistor added below floating gate flash memory cells, creating a neural network (NN) string from a string of flash cells. The weighting factors are stored in each flash cell, and the sum-of-product is obtained by summing the voltage drop of the cells in each string. Using flash technology, a high density NN array can be created within a processing-in-memory architecture.

We move into ferroelectrics next, with imec describing (2.5,Vertical Ferroelectric HfO2FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory) a vertical HfO2field effect transistor based on a 3D NAND-type structure. Up to 2 V memory window was achieved, and flash-like endurance of 1E4 cycles.

Next, a 10 nm node HfZrO based FE-FinFET device is demonstrated in 2.6, Hybrid 1T e-DRAM and e-NVM Realized in One 10 nm node Ferro FinFET device with Charge Trapping and Domain Switching Effects, which showed both charge trapping and domain switching memory effects. In charge trapping mode, extreme high endurance (>1012), high operation speed (< 20 ns), good data retention (104@85C), and low operation voltage (<3 V) were identified, showing potential for e-DRAM. In domain switching mode, even better retention (>10 years) and read disturbance immunity were achieved, making eNVM a prospective use.

The last paper 2.7, High-performance (EOT<0.4nm, Jg~10-7A/cm2) ALD-deposited RuSrTiO3stack for next generations DRAM pillar capacitor, is an imec study of a very high-k dielectric stack (k~118) for the next generation of DRAM, using a Ru\SrTiO3(STO)\Ru trilayer to form metal-insulator-metal (MIM) capacitors. An ultrathin cubic SrRuO3phase is formed at the Ru\STO bottom interface, optimizing the STO epitaxial quality of the dielectric layer. In addition to the high k-value, low leakage (10-7A/cm2at ±1V) was also obtained, making this an excellent candidate for compact pillar DRAM structures in the 1x-nm node range.

Session 3: Circuit and Device Interaction — Device and Algorithm Co-design for Neuromorphic and In-memory Computing

Paper 3.1,Exploiting Hybrid Precision for Training and Inference: A 2T-1FeFET Based Analog Synaptic Weight Cell, describes a 2-transistor-1FeFET based analog synaptic weight cell that exploits hybrid precision for in-situ training and inference. The modulated “volatile” gate voltage of the FeFET was used to represent the least significant bits for symmetric/linear update during training only, and the “non-volatile” polarization states of the FeFET to hold the information of most significant bits (MSBs) for inference.

Schematic of the proposed 2T1F weight cell design (3.1)

Next up (3.2) is an invited talk from IBM Research on Analog Computing for Deep Learning: Algorithms, Materials & Architectures, giving an overview of how nonvolatile memory (NVM) is used, and discussing what the NVM requirements are to give weight encoding a classification accuracy comparable to digital methods.

In 3.3, Hardware Acceleration of Simulated Annealing of Spin Glass by RRAM Crossbar Array, a Ta2O5-based RRAM crossbar arrays and Cu-based CBRAMs were used to accelerate the solving of spin glass problems (N.B. not spin-on glass!). The RRAMs were utilized to calculate the Hamiltonian, and the CBRAMs for the decision of spin-flip events.

3.4, Demonstration of Generative Adversarial Network (GAN) by Intrinsic Random Noises of Analog RRAM Devicesuses the noise generated by the write/read cycles of analog RRAM devices. The noise is the input of a neural network to improve the diversity of the generated numbers; the effect on the GAN performance was studied with a 1 kb RRAM array, and optimized  to moderate the influence of excessive noise.

The final paper in this session, 3.5, Error-Resilient Analog Image Storage and Compression with Analog-Valued RRAM Arrays: An Adaptive Joint Source-Channel Coding Approachfrom Stanford/UCB, describes image storage and compression utilizing RRAM arrays; analog image data is directly stored onto an analog-valued RRAM array. A new joint source-channel coding algorithm was developed, together with a neural network, to encode and retrieve the images, and tolerant of variations in RRAM performance. A reconstruction performance is claimed of ~ 20 dB using only 0.1 devices/pixel for the analog image.

Session 4: Sensors, MEMS, and BioMEMS — Micro and Nano Electromechanical Systems

More folks from UCB start session 4 with a talk on digital ICs made from nano-electromechanical relays(4.1, Demonstration of 50-mV Digital Integrated Circuits with Microelectromechanical Relays), reporting 50-mV operation at room temperature, allowing ultra-low active and zero static power consumption. The group used an electrostatic body-biased design with as few contacts as possible to reduce stiction effects, and a PFOTES (Perfluorooctyltriethoxysilane – had to look that up!) self-assembled monolayer molecular coating to reduce adhesion even further.

Yoshihiko Fuji of Toshiba will give an invited paper (4.2)on the use of spintronic strain-gauge sensors in a MEMS microphone, Highly sensitive spintronic strain-gauge sensor based on magnetic tunnel junction and its application to MEMS microphone. The sensors are based on magnetic tunnel junctions with an amorphous magnetostrictive sensing layer, giving gauge factors >5000.

4.3 Intermixing of motional currents in suspended CNT-FET based resonators; ETH Zurich examines the current generation in a suspended carbon nanotube field effect transistor (CNT-FET) resonators. This can have two components, conduction modulation and piezoresistive, and the ratio is dependent depends on gate bias and the asymmetry of the CNT-FET, affecting the frequency harmonics in nanoresonators.

One of the characteristics of graphene is the high temperatures it can tolerate. Case Western Reserve U. has studied tri-layer graphene nanoelectromechanical resonators (Glowing Graphene Nanoelectromechanical Resonators at Ultrahigh Temperature up to 2650K,4.4), controlling the Joule heating, they demonstrated ultra-wide frequency tuning up to Δƒ/ƒ ≈ 1300%, with corresponding temperature variation from 300 K up to 2650 K. When the temperature goes above 1800K, the devices start glowing and emitting visible light with solid mechanical resonance.

Paper 4.5from Columbia U. (Monolithic Integration of Micron-scale Piezoelectric Materials with CMOS for Biomedical Applications) describes the integration of piezoelectric materials with CMOS, aimed at biomedical use; polyvinylidene difluoride (PVDF) is used in medical implants, and lead zirconate titanate (PZT) for ultrasound imaging. Neither of these can tolerate conventional CMOS process temperatures, but the researchers achieved compatibility and preserved the piezoelectric properties of PVDF/PZT in micromachined ultrasonic transducers.

5G wireless is a hot topic these days, and the next paper (4.6,A Nano-Mechanical Resonator with 10nm Hafnium-Zirconium Oxide Ferroelectric Transducer) by Florida U. describes a 10-nm hafnium-zirconium oxide (HZO) layer that has been engineered to have the piezoelectric properties to resonate at ~4 MHz, enabling CMOS-compatible resonance at 5G frequencies.

A CNRS-led characterisation of optomechanical ring sensors formed on opto-SOI substrates (Comprehensive optical losses investigation of VLSI Silicon optomechanical ring resonator sensors) is presented in 4.7; the optical properties of a statistically significant sample size were investigated, giving excellent modelling to experiment agreement.

Session 5: Focus Session – Characterization, Reliability, and Yield — Interconnects to Enable Continued Scaling

The focus sessions consist of a series of invited papers on a specific topic; first up here (5.1)is Georgia Tech. with a review of the effects of different front-end devices (finFET, tunnel-FET etc.) on interconnect design (Interconnect Design and Technology Optimization for Conventional and Emerging Nanoscale Devices: A Physical Design Perspective), and the need for co-optimization between front- and back-ends.

IBM continues (5.2, Mechanisms of Electromigration Damage in Cu Interconnects) with an examination of electromigration (EM) failure mechanisms in copper interconnects; they predict that the median lifetime of 7- or 10-nm node Cu with a TaN/Co liner and Co cap will be >10,000 years at 140oC with 1.5×107A/cm2current flow. Below 7-nm node there will be difficulties!

5.3, Interconnect metals beyond copper: reliability challenges and opportunities, is an invited talk from imec on the reliability challenges of potential metals to replace Cu in future interconnects. The better oxidation resistance and higher cohesive energy of some metals could enable barrierless integration, if adhesion properties are optimized. Similarly a high melting point and slower self-diffusion kinetics could improve electromigration, making possible higher current capabilities.

Process challenges are metal etch vulnerability, potential voids, adhesion, CMP compatibility, obtaining high aspect ratio trench fill, and avoiding small grain pinning. Higher joule heating and mechanical stresses could cause delamination, and greater electromigration in nearby metal lines.

In 5.4, Microstructure Evolution and Effect on Resistivity for Cu Nanointerconnects and Beyond, U. Texas investigates the evolution of microstructure with scaling in Cu, Co and Ru nano-interconnects and the effect on resistivity. Cu interconnects were studied down to 24 nm linewidths (14 nm node) with a high-resolution TEM precession microdiffraction technique. Monte Carlo simulation was also used to study grain growth in Cu, Ru and Co nano-interconnects, based on local energy minimization; and they examined the scaling effect on resistivity, also for Cu, Ru and Co, allowing for surface and grain boundary scatterings. The Cu and Co results agree with other published work.

Stanford U. looks at Integrating Graphene into Future Generations of Interconnect Wires(5.5), using single-layer graphene as the diffusion barrier and capping layer for Cu interconnects. With this structure, simulations of processor cores predict an 8% speed boost or 12% energy saving, and greater tolerance for process variations. The single-layer graphene is 3.35 Å thick, and provides 3.3× longer barrier lifetime than 2 nm TaN. Barrier reliability is expected to further improve with transfer-free and single-crystalline graphene. Cu electromigration lifetime is improved by 10× compared with Cu with 2 nm CoWP when in-situ low-temperature grown graphene (<0.7 nm thick) is used.

Multilayer graphene is also discussed as a potential Cu replacement, showing a better resistivity scaling trend with FeCl3doping, and better EM; and processor cores achieve 9% higher speed or 16% less energy consumption. EM lifetime of spin-on-glass encapsulated multi-layer graphene was twice that of than CoWP-capped Cu.

Applied Materials covers Interconnect Trend for Single Digit Nodes(5.6), now that we are in the 7-nm era and heading for the 5- and 3-nm nodes. New integration methods, materials, and fill technologies have to, and are, being studied.

Session 6: Focus Session – Nano Device Technology — Quantum Computing Devices

This topic is again covered by a set of research papers, but here we will only look at those dealing with qubits in Si technology. CEA-LETI reports on Si spin qubits in 6.2, Towards scalable silicon quantum computing, considering the use of FDSOI to in-situ tune the devices using back bias.

6.3is a study of Qubit Device Integration Using Advanced Semiconductor Manufacturing Process Technology; it appears that qubits using semiconductor spin are similar to scaled transistors, so Intel has developed a qubit test chip on 300-mm wafers, using a28Si epitaxial layer to improve spin coherence. The quantum dots were created using a dual-nested gate integration process.

Keio U.discusses Silicon Isotope Technology for Quantum Computingin paper 6.4. Isotopically engineered Si-28/SiGe heterostructures were prepared for silicon-based quantum computers using a standard silicon CMOS integration technology. The Si-28 quantum wells were well-strained and showed high electron mobility and large valley-splitting, potentially allowing integration of Si spin qubits with CMOS circuitry.

Another CMOS-based strategy is described in 6.5,Scalable quantum computing with ion-implanted dopant atoms in silicon. Quantum information is encoded in the combined electron-nuclear spin state of individual ion-implanted phosphorus dopant atoms in silicon, enabling a qubit pitch of ~200 nm. Fast and high-fidelity quantum logic operations are predicted, and a potential “flip-flop” qubit system.

Session 7: Process and Manufacturing Technology — 3D Integration and Memory Technologies

3D integration in our industry has at least two interpretations – the stacking of completed chips in order to integrate multiple functions (so a form of packaging), and the monolithic stacking of transistors to create a single IC. In this session we have both!

imec starts off (7.1, First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers) with the monolithic layering of finFETs, using junction-less devices in the top layer, and a 170nm wafer-bonding dielectric, fabricating and transferring them with processes ≤525ºC to avoid degradation. The local interconnect between the two layers was patterned with 193nm immersion lithography; the top layer was thin enough to allow this, enabling tight alignment precision of the top layer to the bottom layer (see below).

The top devices offer similar performance as the high temperature bulk finfet technology for low standby power applications. A TiN/TiAl/TiN/HfO2gate stack was adopted with La doping, giving good threshold voltage adjustment, reliability and low-temperature performance.

TEM cross-section of 3D stacked FinFETs along fins and across gates (7.1)

TEM cross-section of devices across fins with the gates covering the fins (7.1)

In 7.2, CEA-Leti continues to tell us about their CoolCube technology (Breakthroughs in 3D Sequential technology), which is the monolithic layering of planar transistors. One of the challenges of transistor stacking has been keeping the thermal budget for the top layer low enough to avoid degrading the bottom layer, and here we find out that a low resistance gate stack was formed using nanosecond laser processing, and a 500°C raised source & drain epitaxy was achieved. They also examined the intermediate Back End of Line properties (there is Cu/ULK under the top layer), and demonstrated the bonding of a Smart CutTMnm-thin wafer onto a CMOS wafer.

Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness(7.3) details a 3D-stacked CMOS image sensor from STMicroelectronics with a bonding pitch of 1.44 μm. The stacked hybrid bonding was progressed from 8 down to 1.44 μm without any specific failure mechanism due to pitch shrinkage.

We’ll have to pass on the memory papers, unfortunately, and sessions 8/9.

Session 8: Power Devices/ Compound Semiconductor and High-Speed Devices – Advances in Silicon Carbide and Gallium Oxide Silicon Power Devices

Session 9: Modeling and Simulation – Modeling and Simulation of Negative Capacitance Transistors

Session 10:Optoelectronics, Displays, and Imagers — Image Sensors

We have had stacked, hybrid-bonded image sensors in phones for a while, but the bonded connections have always been outside of the pixel array. In the first paper, 10.1, 1.5μm dual conversion gain, backside illuminated image sensor using stacked pixel level connections with 13ke- full-well capacitance and 0.8e- noise, Omnivision takes the bonding into the array, and each pixel has a bonded connection.

We have a 1.5μm pixel size, 8 Mpixel, dual conversion gain (DCG), back-illuminated CMOS image sensor (CIS) with a linear full-well capacity (FWC) of 13ke- and total noise of 0.8e- RMS at 8x gain. The stacked pixel-level connection (SPLC) has the same 1.5μm pitch as the pixels, with >8M connections, maximizing the fill-factor of the photodiode and size of the associated transistor to achieve a large FWC and low noise performance at the same time. The allocation some of the cell read-out transistors into two different layers enables the DCG function to be fulfilled within the 1.5μm pixel size.

Sony reports (10.2) A 0.68e-rms Random-Noise 121dB Dynamic-Range Sub-pixel architecture CMOS Image Sensor with LED Flicker Mitigation; the pixel has two sub-pixels of different sizes, allowing it to have ultra-low random noise of 0.68e-rms and a high dynamic range (HDR) of 121 dB in a single exposure, and mitigating LED flicker.

STMicroelectronics has developed a HDR Global Shutter (GS) pixel for automotive applications (10.4, A HDR 98dB 3.2μm Charge Domain Global Shutter CMOS Image Sensor)with dual high-density storage nodes using Capacitive Deep Trench Isolation (CDTI). Pixel size is 3.2μm, claimed to be the smallest reported GS pixel with linear dynamic range of 98dB and noise floor of 2.8e-. The pinned memory isolated by CDTI can store 2 x 8000e- with dark current lower than 5e-/s at 60°C. A shutter efficiency of 99.97% at 505nm and a Modulation Transfer Function (MTF) at 940nm better than 0.5 at Nyquist frequency is also reported.

TowerJazz announces a 2.5um GS CIS pixel using an advanced Light-Pipe (LP) structure in 10.5(High Performance 2.5um Global Shutter Pixel with New Designed Light-Pipe Structure), reportedly the smallest GS pixel. The pixel has excellent Quantum Efficiency (QE), Angular Responses (AR) and very low Parasitic Light Sensitivity (PLS). These characteristics enable ultra-high resolution sensors, industrial cameras with wide aperture lenses, and low form factor optical modules for GS mobile applications.

Sony returns with 10.6, Back-Illuminated 2.74 μm-Pixel-Pitch Global Shutter CMOS Image Sensor with Charge-Domain Memory Achieving 10k e- Saturation Signal. A 3208×2184 GS image sensor with back-illuminated architecture was fabbed in a 90 nm/65 nm imaging process. The sensor has 10000 electrons full-well capacity and -80 dB parasitic light sensitivity. Furthermore, 13.8 e-/s dark current at 60°C and 1.85 erms random noise are obtained. The pixel structure with memory, along with saturation enhancement technology is described.

That brings us to the end of the Monday afternoon sessions, and the receptionwill start at 6.30 pm in the Grand Ballroom.

Stay tuned for a preview of Tuesday’s sessions.

IEDM 2017: Intel’s 10nm Platform Process

By Dick James

IEDM this year was its usual mixture of academic exotica and industrial pragmatica (to use a very broad-brush description), but the committee chose to keep us all waiting until the Wednesday morning before we got to the CMOS platform papers. Of course, the talk we were all anticipating was Intel’s Chris Auth on “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects”.

Deliberate or not, Intel has been teasing us with release dates for their 10-nm products, and as yet there have not been any out in the market for the analysts to get their hands on and expose the secrets. TSMC and Samsung we have seen, but not Intel (and arguably, they are closer to 14-nm technology). Needless to say, the room was full, and Chris did the usual Intel preamble about being ahead of the 2x shrink trend, and achieving 100M transistors/mm2.

Intel 10-1


The claim is that density increases by a factor of 2.7 from the 14nm generation, using the metric announced by Mark Bohr at the Technology and Manufacturing Day (TMD) earlier this year:

Intel 10-2


The paper states that this was achieved by “use of SAQP w/193nm immersion lithography, improved transistor matching to enable fewer fins in the standard cell library and novel process features to enable tighter layout.”

The table below shows the design rules and shrink from the 14-nm process:

Intel 10-3

Any pitch 40 nm or below needs quad-patterning (or LELELE), so the fins, M0 and M1 use SAQP. Compared with SADP, Intel’s SAQP needs four additional steps, one deposition on the sidewall spacers from the original mandrel, and three etch steps. In addition to the feature shrinks, there are technology changes in the standard cell layout. The dummy gates at the cell boundaries have gone, replaced by a single gate spacing; and the gate contact is now over the active gate, ending the need for isolation space to fit in the contact.

The 14-nm process had a dummy gate at the edge of each cell, on the end of adjacent fins, similar to this image of a 22-nm device;

Intel 10-4

The 10-nm cell uses a dummy gate spacing between fin ends, which saves a gate pitch when packing two cells together, a claimed 20% cell area saving.


Intel 10-5


In actual fact there is no dummy gate in the finished product, just the fin etched where a single dummy gate would be. This was shown in the presentation, but it is not in the paper, but Samsung did something very similar in their 10-nm offering:

Intel 10-6_Samsung 10 SDG


In fact, a dummy polySi gate is used, allowing source/drain formation without risking the fin edge; but for these particular gates the polySi removal etch goes a bit further, and etches the fin to separate the cells.

The second layout change is to shift the gate contact into the active transistor area, over the functional part of the gate (see below).

Intel 10-7


Such tight alignment with the source/drain (diffusion) contacts requires the development of self-aligned contacts to the gate, and modification of the self-aligned diffusion contacts that were already in use at 14-nm and 22-nm.

Diffusion contacts (left) and gate contacts

Diffusion contacts (left) and gate contacts

To do this, two etch-stop materials and two selective etches are used. After gate formation it is etched back and the cavity is filled with silicon nitride, as in earlier generations; the contact is then put in and also etched back, and the cavity is filled with silicon carbide. Then there is a selective etch to open the gate contact, which does not touch the SiC in the contact cavity, and a second selective etch removes the SiC from the contact cavity, but does not affect the gate contact periphery. Clearly this sequence is reliant on excellent etch selectivity between the different materials.

There are other innovations in the contact stack – the contacts themselves are cobalt, giving >60% line resistance reduction, and there is a conformal titanium layer wrapped around the source drain epi, as well as a thin nickel silicide layer on the PMOS epi. This is claimed to give ~1.5x contact resistance reduction.

The fins are SAQP-defined with a 34-nm pitch, 7 nm width (at ½-height), and 46 nm height. Intel appeared to have backed off on the 53-nm fin height that they announced back in March. 46 nm is still an increase from the 42 nm of the 14-nm process, just not as ambitious; if memory is accurate, that is the same as the 14+ fin height. I guess the taller fin could be looking forward to the 10+ or 10++ generation. In the Q&A we were told that the fin height is tunable with a range of ~10 nm, and 46 nm is at “the low end of the mid-range”.

In fact, if you use the fin pitch as calibration, the fin height in Intel’s image is ~52 nm, and close examination reveals that it is the same image as that shown in Kaizad Mistry’s TMD talk last March.

Intel 10-12m

And if we compare this pic with the 14-nm device, it appears that the solid-source punch-stop diffusions introduced at 14-nm are present, since we can see the seal layer(s).

Intel 10-10


This allows the fin to be un-doped in the channel, with options for four or six Vts (low, standard and optional high Vts) with differing work-function metals. Source/drain epis are in-situ doped and provide strain enhancement, though we are not told if that is N- or P-MOS or both, nor is SiGe mentioned, though I would assume it is still used for PMOS stress. NMOS drive is also enhanced by interlayer dielectric stress, giving a ~10% improvement (from my notes – the paper says 5%).

With a smaller fin pitch the implant angle needed for doping is also shrinking; I measured it as less than 30o, compared with the 52o and 41o of the 22- and 14-nm processes, but I am told that if the implant has a twist (i.e. angled with respect to the fin orientation), then it is till feasible to get implants into the right location.

Additionally, the k-value of the sidewall spacers has been lowered, to reduce the parasitic contact-gate capacitance by 10%, and my notes also say that the gate fill has been changed to cobalt.

With a 46-nm fin height the gate width should be ~97 nm, compared with the ~85 nm of the previous generation (or the same as the 14+). If the 53-nm fin height is used, gate width is likely ~110 nm. Minimum gate length was stated to be 18 nm.

All of this transistor engineering leads to a NMOS Idsat of 1.78 mA/µm and Idlin of 0.475 mA/µm at 0.7 V and 10 nA/µm, increases of 71% and 100% compared to 14-nm FINFET transistors, for minimum Lg devices. Similarly, PMOS shows drive current gains of 35% Idsat and 55% Idlin. Steep subthreshold slopes (~70 mV/dec.) and very low DIBL (~70 mV/V) are also found.

TEM cross-section of NMOS(?) gates

TEM cross-section of NMOS(?) gates

The middle- and back-end stack has thirteen metal layers (including M0), with cobalt used in M0 and M1 to replace copper. This gives a 2x resistance reduction, and 5 – 10x electromigration improvement. Self-aligned double patterning (SADP) is used at Metal 2 – Metal 5, and a cobalt cap (no liner, as in TSMC) is also used on M2 – M5 to improve electromigration. Low-k dielectrics are used on eleven layers out of the thirteen, and in the Q&A it was noted that it is the same low-k as in the 14-nm process.

The SRAM cells are scaled by a factor of ~0.6, so that the low-voltage 1:2:1 (fins in Pull-Up:Pass-Gate:Pull-Down transistors) cell goes from ~0.059 µm2 to ~0.0367 µm2, and the high-density 1:1:1 cell shrinks from ~0.050 µm2 to ~0.0312 µm2. (The TSMC and GF/IBM/Samsung 7-nm cells announced at IEDM16, presumably 1:1:1 cells, were 0.027 µm2.) There is also a high performance 0.0441 µm2 cell. Ring oscillator performance at 0.7 V was 20% better than the 14-nm device.

The cell height is 272 nm, so with a 34 nm fin pitch, we have eight fin spacings per cell; but we tend to lose two fins in the centre to allow for well boundaries, and one each at top and bottom under the Vdd/Vss lines, implying 2x two-fin transistors in the minimum standard cell. That agrees well with the comments in the paper about “aggressive reduction in fin usage, improving transistor density.”

Back in March we were told that the 10-nm process shrinks beyond the usual 50% to 37% of the 14nm technology:

Intel 10-13
And that this actually brings them back on to a two-year cadence from the 45-nm node, assuming high-volume production as of the second half of this year.

It’s a bit close to the end of the year for that to happen, but if we see product in the New Year they won’t be too far off – we look forward to it!

I had hoped to fit in some commentary about the GLOBALFOUNDRIES 7nm paper given in the same session, but in the interest of brevity I will have to make a separate blog, maybe in the New Year.

Intel 10-14

IEDM 2017 Next Week Part 2

Part 1 of Dick James’ preview can be read here

By Dick James


Most of the sessions Wednesday morning are limited to five papers, since we have a second plenary session (30) at 11.10 am.

Session 28: Memory Technology – In-memory Computing

28.1 looks at the modeling-based design of brain-inspired spiking neural networks with RRAM learning synapses. A comprehensive model for spiking neural networks based on spike-timing dependent plasticity in RRAM synapses is presented.

A dual-mode computing (DMc) ReRAM macro structure with a dual-function voltage-mode self-write termination (DV-SWT) scheme is proposed in 28.2, to achieve both memory and fundamental computing-in-memory (CIM) functions (AND, OR and XOR operations). A 16Mb DMc-ReRAM full-function macro was fabricated using 1T1R HfO ReRAM devices and 0.15um CMOS process. The measured delay of the CIM operations is less than 14ns, which is 86+x faster than previous ReRAM-based CIM works.


In 28.3 a new method for fast and robust compressed sensing recovery of sparse signals using computational memory (CM) is proposed. (CM performs certain computational tasks within resistive memory units.) Large-scale experimental demonstrations using more than 256k phase-change memory devices are presented along with an in-depth device analysis and array-level considerations.

Next up is an invited paper that presents data-aware NAND flash memories (28.4). By recognizing the data value, sophisticated data management such as storing important data in reliable memory cells, or adaptively optimizing read voltage are realized. Consequently, intelligent computing such as image recognition with deep neural networks, data compression and disaggregated hybrid storage can be achieved.

Given the processes mentioned, this (28.5) looks like a GLOBALFOUNDRIES-sponsored paper, on a reconfigurable NAND/NOR logic gate based on a single ferroelectric FET (FeFET) in 28 nm HKMG and 22 nm FD-SOI FeFET technology. The gate uses hafnium oxide as the ferroelectric material with a pull-up device connected in series.

Session 29: Circuit and Device Interaction – Advanced Platform Technologies

Intel 10nm

This is the session that a lot of us will be waiting for – Chris Auth of Intel is first up (29.1) with “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects”. 

Fig 1


The transistors feature rectangular fins with 7 nm fin width and 46 nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon. Self-aligned quadruple patterning (SAQP) is used for critical layers such as fins and minimum metal (34 nm and 36 nm pitches, respectively). Four or six work-function metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices. NMOS and PMOS current is 71% and 35% greater, respectively, compared to 14-nm FinFET transistors. For high density, a self-aligned  contact over active gate process and elimination of the dummy gate at cell boundaries are introduced, as described in the Technology and Manufacturing Day last March.

Intel appeared to have backed off on the 53-nm fin height that they announced back in March (above), so the final fin profile could be different, especially if they are actually rectangular. 46 nm is still an increase from the 42 nm of the 14-nm process, just not as ambitious; I guess the taller fin could be looking forward to the 10+ or 10++ generation, definitely one for the Q & A!

There are 12 metal layers of interconnect, with cobalt in the lowest two layers that yield a 5-10x improvement in electromigration and a 2x reduction in via resistance, and ultra-low-k dielectrics throughout the interconnect stack. Three different types of SRAM cells are detailed, a high-density 0.0312 µm2 cell, a low voltage 0.0367 µm2 cell, and a high-performance 0.0441 µm2 cell.

29.2 is an invited talk from S. Barraud of CEA-Leti; “Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs”, reviewing recent progress on GAA-NW and NanoSheet (NS) MOSFETs. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power- performance optimization.

IBM/Samsung/GF are also looking at nanosheets in 29.3, in which a quantitative performance evaluation of horizontal nanosheet structures across a wide range of sub-7nm design spaces is presented.

fig 2


Intel 22FFL

Intel also announced their 22FFL process in March, now we get a paper on it (29.4); clearly aimed at the foundry business and IoT products, it appears to an upgrade from the 22-SoC process [1]. Or maybe it’s a relaxed 14-nm process, we’ll have to see the transistor profile to make that call. The raw dimensions, as you’d expect, are in between.
We still have double-patterned fins, but the gate and metal are single-patterned, and the SRAM cell size puts it close to the 22-nm node. The process combines high-performance, ultra-low power logic and RF transistors; the high-performance transistors show 57%/87% higher NMOS/PMOS drive current compared to the 22-nm technology. New ultra-low power logic devices reduce bitcell leakage by 28x compared to a regular SRAM cell, and an RF device with optimized layout has been developed and shows excellent fT/fMAX of 230 GHz/284 GHz and 238 GHz/242 GHz for NMOS and PMOS respectively.

Other SoC features are high resistance substrate, deep N-well isolation, precision resistors, MIM capacitors, and high-Q inductors.

The final talk (29.5) is a late-news submission from GLOBALFOUNDRIES on their upcoming 7-nm platform (don’t forget, GF are skipping 10 nm). It features 3rd-generation SAQP finFET architecture, and SADP BEOL metallization, with an improvement of 2.8X in routed logic density and >40% performance over the 14nm reference technology. Multiple Vts are derived from “a unique multi-work-function process”, giving low-voltage SRAM response and highly scaled memory areas. The HD 6-T bitcell size is 0.0269 um2. The technology uses immersion lithography, but is also designed to adopt EUV for specific levels, for cycle time benefit and manufacturing efficiency, when EUV is ready.


Session 30: Plenary Session II

This year we have a second plenary session squeezed in with the other sessions, so that the awards associated with the traditional Tuesday conference lunch can be presented. After that we have a plenary paper (30.1), “Development of Sustainable Smart Society based on Transformative Electronics”, from M. Ogura of Nagoya University. The title belies the rest of the abstract, since it focuses on gallium nitride defects and GaN nanorod devices:

“Defects which cause leakage under a high-voltage reverse-biased condition were identified in GaN pin diodes grown on freestanding GaN substrates. The performances of GaN-based horizontal-heterostructure superjunction high-electron mobility transistor and a GaN-nanorod-based vertical pn-superjunction diode were simulated. A vertical pn-superjunction was fabricated using GaN nanorod growth technology.”


Session 31: Modeling and Simulation – Simulations of Nano-devices

31.1 is an invited study of time-resolved energy currents in a molecular optoelectronic junction made of two donors and an acceptor, sandwiched between two electrodes and excited by a Gaussian femtosecond laser pulse. Features of the direct energy currents are thus correlated to the intra-molecular structure.

Gate-induced-drain-leakage (GIDL) in 2D FETs is evaluated by UCal Santa Barbera/Micron using a novel quantum transport methodology (31.2). GIDL is a key issue in access transistors, and the results establish the advantages of certain 2D semiconductors in greatly reducing GIDL, and thereby support use of such materials in future memory technologies.

UCal Santa Barbera presents again (31.3), on “How to Derive the Highest Mobility from 2D FETs – A First-Principle Study” – a comprehensive mobility modeling framework for 2D-semiconductor FETs is developed, and applied to study the impact of synthesis technology, defect concentration, electric field, and channel/dielectric materials on the mobility.

In 31.4 a unified surface potential based physical compact model for both unipolar and ambipolar 2D-FETs is developed and verified by device measurements, including the influence of extensive disorder effects on transport. This is implemented in Verilog-A for evaluating the possibility of digital and RF applications with 2D-FETs.

GLOBALFOUNDRIES presents the next paper (31.5), describing a quantitative model for switching asymmetry in p-MTJs, by combining a 4×4 tunnelling conductance matrix derived using NEGF formalism, and a 4×4 ferromagnetic conductance matrix derived from the Valet-Fert equation. It provides qualitative and quantitative agreement with switching voltages in spin torque experiments observed in IBM, Everspin and GLOBALFOUNDRIES hardware data.

Session 32: Process and Manufacturing Technology – 3D Integration

32.1 is an imec-led review of the different variants of sequential 3D integration, and the potential challenges to achieve a realizable solution. The benefits observed due to sequential scaling at a die level are analyzed and quantified.

More CEA-Leti work in 32.2; they have been doing a lot of work with laser annealing and Solid Phase Epitaxy Regrowth (SPER), and now double SPER with two amorphization/recrystallization steps, which has the advantage of doping the bulk of the S/D junctions. This enables a low-temperature FinFET process to be demonstrated, with gate-last integration and self-aligned contacts; devices exhibit performances close to those of the high temperature process of reference.

We have an invited presentation from Tohoku U. next (32.3), on new materials and processes for advanced Si devices. Co contact plugs and amorphous Co-Ti barriers showed a good adhesion for MOL, with limited growth of Co silicide, and a low contact resistivity of the order of 10-9 Ωcm2 on both n+ and p+ Si. For BEOL, a CVD-MnOx layer could be formed conformally in high-aspect ratio contact holes, and an ALD-MnOx layer of 1.2 nm thick showed a good diffusion barrier property at 400 oC. For 3D integration, TSV of 10 μm diameter and 80 μm depth could be filled with low resistivity sintered Cu paste without voids.

32.4 is an imec study of wafer-to-wafer hybrid bonding, using SiCN in combination with Cu pads of unequal size and surface topography, formed by CMP processing, to give electrically yielding 300 mm-bonded wafers with pad pitches of 1.44 μm down to 0.72 μm.

Liquid jet impingement cooling of high power devices is considered in 32.5, again by imec, using a 3D-shaped polymer cooler.


Session 33: Power Devices – Development of GaN Power Devices Technologies

TSMC has a smart GaN power platform (33.1), with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, and the 2nd level integration has high-low side on-chip integration on a 100 V technology platform.

33.2 is a study of reverse-bias stability and reliability of hole-barrier-free E-mode LPCVD-SiNx/GaN MIS-FETs. With limited hole-generation, the devices deliver small NBTI values, even without a hole-barrier. In reverse-bias stress, the SiNx gate dielectric, while exhibiting a negative valance-band-offset with GaN, acts as a plug to holes, and hole-induced degradation can be greatly contained by limiting gate-bias to a few volts below VTH.

Toshiba details improved GaN MOSFETs (33.3) with drastically suppressed positive bias temperature instability (PBTI), by reducing impurity densities in the SiO2 gate dielectric; they were controlled by heat treatment after dielectric deposition.

Defect bands are found in carbon-doped GaN (33.4); these layers, crucial for GaN HEMT buffers, show non-Arrhenius thermal behavior of capacitance transients related to the trapping/detrapping dynamics of leakage current in a wide temperature range. The model developed indicates that conduction via defect band controls both processes, redefining the way III-N:C containing layers should be investigated.

Proton irradiation is used to achieve zero dynamic-Ron in GaN-based power HEMTs (33.5). The results are explained by considering that proton irradiation increases the leakage through the uid-GaN channel layer. This increases the detrapping rate, and leads to the suppression of dynamic-Ron at high VDS.

Session 34: Focus Session – Optoelectronics, Displays and Imagers – Silicon Photonics

This is the last focus session of the conference, with another five invited papers from purveyors and researchers into Si photonics. Luxtera announced partnership with TSMC in March this year, so maybe in 34.1 we’ll hear how that is going, since the topic is “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain”.

34.2 is imec’s take on the technology; “Reliable 50Gb/s Silicon Photonics Platform for Next-Generation Data Center Optical Interconnects”. Their platform claims to support single-channel data rates of 50Gb/s and above – advanced process options include 50 GHz GeSi electro-absorption modulators, and high efficiency thermo-optic phase shifters.

South of the border from imec, we have the Grenoble cluster describing their “Developments in 300mm silicon photonics using traditional CMOS fabrication methods and materials” (34.3). Japan’s Photonics Electronics Technology Research Association (PETRA) looks at “Advanced devices and packaging of Si-photonics based optical transceiver for optical interconnection” (34.4) as a way keeping system costs down – highly accurate assembly processes in optical coupling are needed, but they are not always cheap.

Lastly, NTT reviews their recent achievements in various energy-efficient nanophotonic devices based on photonic crystals (34.5). The strong light confinement of these devices enables large enhancement of light-matter interactions, and ultra-small capacitance for OE/EO conversion devices; they demonstrate that the energy consumption can be reduced down to fJ/bit or less.


Session 35: Modeling and Simulation – Progress in Modeling Methodology and Approaches

35.1 presents the theory, implementation and application of a new quantum transport, NEGF based modelling approach employing a full-band Empirical Pseudopotential (EP) Hamiltonian, enabling complete, self-consistent simulations for both FETs and Tunnel FETs in Si or in Ge, and with geometrical features in line with upcoming CMOS technologies.

35.2 is an invited talk discussing first-principles-based quantum transport simulations of nanoscale field effect transistors made of Ge, Si, strained-Si, and few-layer black phosphorus channels.

In a joint paper by GLOBALFOUNDRIES and Synopsys (35.3), density functional theory (DFT) is used to calculate TCAD parameters to describe dopant diffusion in Si, SiGe and Ge. The dopant profile simulated in TCAD with calculated parameters is in good agreement with experiment.

We get into the TCAD simulation of SiC CVD in 35.4, simulating trench filling for SiC super-junction devices. 35.5 studies the conductance of doped carbon nanotubes (CNTs) as a possible candidate for BEOL interconnects; circuit-level simulations predict up to 88% signal delay improvement with metal-doped vs. pristine CNT. This was validated by electrical measurements of Pt-salt doped CNTs with up to 50% of resistance reduction.


Session 36: Nano Device Technology — Device Technologies for Disruptive Computing

In 36.1 we look at van der Waals (vdW) heterojunctions of MoS2 and VO2; the sharp vdW interface enables a tunable diode-like characteristic, and this can be extended to tunable rectifiers, photodiodes and field effect transistors. The next paper (36.2) proposes and demonstrates a stochastic computing unit with a single MTJ; it can perform addition and multiplication operations and requires no additional logic gates.

In 36.3, it is shown that compact spin-torque nano-oscillators can form sub-micron neurons; and that they can naturally implement reservoir computing with high performance, and detail the recipes for this capability.

A STDP synapse with outstanding stability based on a novel insulator-to-metal transition FET is detailed in 36.4, based on a gate-controlled insulator-to-metal- transition FET. Since a metallic channel is used, stochastic phenomena have little effect, giving high stability with a large dynamic range and very low power consumption.

The last paper (36.5) demonstrates a CMOS-compatible double quantum dot spin qubit that is all-electrically controlled without the need for external components such as micromagnets, that could complicate integration. Universal control of the qubit is achieved through spin-orbit-like and exchange interactions. Using single shot readout, we show both DC- and AC-control techniques.


Session 37: Process and Manufacturing Technology — Advanced Transistor Technologies

37.1 is a study of 5-nm-thick ferroelectric Y-doped HfO2 on p+ Ge; the investigation indicates that stable ferroelectric characteristics are maintained down to 5 nm by controlling doping and capping effects. The cycling performance showed no wake-up behavior, and no obvious degradation after 108 cycles.

In 37.2 IBM/GLOBALFOUNDRIES studied the relative impacts of germanium content vs. strain on the performance of SiGe channels in strained SiGe p-FinFETs and planar devices on a strain-relaxed buffer (SRB) substrate. Last year GF/IBM/Samsung gave a paper on a SRB-based 7-nm process [2], and we looked at it in a follow-up blog.

This looks like further work to set some more parameters; the devices had different strain configurations, Ge channel compositions and surface properties. The inclusion of planar devices likely provides a baseline, but also may have useful data for the FDSOI processes at GF (no mention of FDSOI in the abstract). The fin shape is more rectangular than in last year’s paper – is the process evolving that way?

By comparing the transistor electrical properties of SiGe pFETs on SRB with those on Si substrate, the influence of strain and Ge content in the channel on device performance is decoupled from factors such as gate stack quality, reliability, and carrier transport.

The authors found that, independent of strain, increasing Ge content led to unstable gate stacks with greater interface trap charges and relatively low hole mobility, although it improves NBTI reliability. Carrier transport is predominantly controlled by the channel strain, and a (100) substrate crystal orientation helps optimize the effects of strain for both n- and p-FinFETs.

Process flows for SiGe planar pFETs and pFinFETs fabricated on SRB virtual and on Si substrates  (source: IEDM/IBM/GF)

Process flows for SiGe planar pFETs and pFinFETs fabricated on SRB virtual and on Si substrates (source: IEDM/IBM/GF)

TEM images of a Si fin after M1 metallization; STEM (left) HAADF (center) and (right) EDX. No Ge diffusion from the SRB to the Si active fin is observed  (source: IEDM/IBM/GF)

TEM images of a Si fin after M1 metallization; STEM (left) HAADF (center) and (right) EDX. No Ge diffusion from the SRB to the Si active fin is observed (source: IEDM/IBM/GF)

37.3 is an invited IBM talk on gate-stack engineering for gate-first and RMG transistors, so again keeping consideration of FDSOI applications. Key process details are disclosed to achieve optimized devices with near-ideal SS, excellent NBTI, mobility and transconductance at scaled-EOTs. Aggressively-scaled fins with WFIN=6.4nm and excellent short-channel characteristics are also demonstrated.

imec/Applied Materials claim the first circuit built with Si nanowire transistors in 37.4 . They built functional ring oscillator test circuits using stacked Si NWFETs, with devices that featured in-situ doped source/drain structures and dual-work-function metal gates. A SiN STI liner was used to suppress fin deformation and improve shape control; a high-selectivity etch was used for nanowire/nanosheet release and inner spacer cavity formation, with no silicon reflow; and a new metallization process for n-type devices led to greater tunability of threshold voltage.

(a)NWFET structure after inner spacer fill and etchback; (b) after source/drain (S/D) epitaxy; (c) TEM view after S/D epitaxy (source: IEDM/imec/Appled Materials)

(a) NWFET structure after inner spacer fill and etchback; (b) after source/drain (S/D) epitaxy; (c) TEM view after S/D epitaxy (source: IEDM/imec/Appled Materials)

National Taiwan University also claims a first in 37.5, this time the first stacked GeSn pGAA-FETs. Good crystalline quality is achieved from CVD-grown stacked GeSn layers. Using Ge barriers as sacrificial layers and an ultrasonic-assisted hydrogen peroxide etching technique, the GeSn 60 nm channel has record high Ion of 1850 uA/um, with SS=88 mV/dec.


Session 38: Memory Technology — STT-MRAM

Avalanche Technology seems to have been in stealth mode, but in 38.1 they present a bi-directional threshold switching selector and integrated one selector/one perpendicular MTJ (1S1R) device. The selector shows an On/Off ratio above 1E+7, 1 pA leakage current, 0.3 V threshold voltage, and fast speed (10 ns).

Next up is an invited review by Seung Kang of Qualcomm; “MRAM: Enabling a Sustainable Device for Pervasive System Architectures and Applications” (38.2)

With its unique attributes and tunability, MRAM is poised to become a unified memory subsystem that can revamp the architectures of emerging ultra-low-energy systems, and has potential to transform computing-centric architectures at advanced nodes.

IBM and Samsung give a joint paper (38.3) on the impact of four key parameters on the switching efficiency of STT-MRAM devices with perpendicular magnetic anisotropy (p-MTJ): device size, device resistance-area product, blanket film Gilbert damping constant (α), and process temperature. Optimization of the p-MTJ materials eliminated the performance degradation observed in 400ºC-processed devices. Additionally, 400ºC-compatible double MTJs showed 1.5x improvement in switching efficiency compared to single MTJs with identical free layers.

In 38.4 TDK- Headway Technologies takes their expertise in magnetic analysis (they make magnetic recording heads) to probe the magnetic properties of STT-MRAM devices down to sub-20 nm using spin-torque ferro-magnetic resonance (ST-FMR).

Measurements of the anisotropy field (Hk) of devices down to 20 nm using ST-FMR are reported, and it is shown that Hk increases for decreasing sizes. Using micromagnetic simulations, they developed a simple model to fit Hk size dependence, allowing the quantification of magnetic edge damage for various process conditions.

Etching magnetic tunnel junction (MTJ) cells at small dimensions and very dense pitch is still challenging for high density STT-MRAM. This paper (38.5) avoids MTJ etching, and demonstrates MTJ nano-patterning at very narrow pitch (pitch=1.5F, F=MTJ dot diameter) by growing the MTJ material on pre-patterned conducting non-magnetic pillars without post-deposition etching.

38.6 also describes 400°C-compatible p-MTJ stacks; top-pinned stacks with a new synthetic ferromagnetic stack pinning layer design is used to demonstrate free layer off-set control and low current switching in 30nm CD devices.


Session 39: Characterization, Reliability and Yield — Advanced Reliability Characterization and Circuits

In paper 39.1, a set of two- and three-dimensional analysis techniques are combined to clarify the switching and failure modes of resistive switching in state-of-the-art TiO2-based vacancy modulated conductive oxide memory. 39.2 examines ultra-fast (<1 ns) electrical characterization of the self-heating effect and its impact on hot-carrier injection in 14nm finFETs, capturing the heat generation and dissipation process in the transistor channel.

Now that 14nm is a mature process, U. Minnesota/Intel are characterizing soft error rates (SER) in combinational logic gates (39.3), using a NAND/NOR readout chain. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data, capturing the impact of various circuit parameters on SER.

In 39.4 the statistical behaviors of read current noise and retention in a 1Kb filamentary analog RRAM array are investigated. The conductance distribution of different levels is found to change with time, and the physical mechanism of this retention degradation is explained. From the experimental data, a compact model is developed in order to predict the statistical conductance evolution, which can effectively evaluate the impact of read noise and retention degradation in neuromorphic computing systems.

The last paper (39.5) is an invited presentation from Carnegie Mellon U., on “Combatting IC Counterfeiting Using Secure Chip Odometers”. The odometers employ chained one-shot binary aging elements that use intentional accelerated device aging to measure the use and age of the chip. A prototype secure odometer was taped out on a 1.2mm x 1.7mm test chip in a 65nm bulk CMOS process as a proof-of-concept.


Session 40: Sensors, MEMS, BioMEMS — MEMS for Internet-of-Things (IoT)

High-Q silicon fin bulk acoustic resonators (finBARs) are described in 40.1; high-aspect-ratio fins are etched in the silicon substrate and covered by aluminum nitride films to enable efficient electromechanical transduction of bulk acoustic resonance modes with large coupling coefficient (kt2), resulting in unprecedentedly high quality-factors (Q) in ultra- and super-high- frequency (SHF) regimes.

A monolithically 3D-printed pressure sensor with excellent sensing performance was demonstrated (40.2). The porous-structured dielectric was formed by casting an elastomer prepolymer into 3D-printed water-soluble templates. The flexible electrodes were monolithically 3D-printed using a conductive thermoplastic as well. Finally, the sensors were applied to the e-skin and wearable healthcare monitoring system.

A triboelectric nanogenerator (TENG) composed of porous conductive-polymer and PTFE wrapping wires, is detailed in 40.3. The TENG generated a short-circuit current for a long duration and great output performance. A model based on parallel connection of the finite capacitors was developed, and validated by comparison between experiment and calculated results.

In 40.4 a self-powered broadband (20 Hz ~ 2000 Hz) electromagnetic-induced vibration sensor, a remote temperature sensor, and a first stage read-out circuit MEMS, are integrated heterogeneously in compact packaging.

40.5 describes a refractive index sensor formed from aluminum nanohole arrays on vertical Ge PIN photodiodes; the interaction of plasmonic resonances and thin-film reflection within the PIN layer stack enables sensitivities comparable to Au sensing systems showing FOM* up to 14.
Chronologically the last paper is due at 3.40 pm – by then a lot of attendees will have headed for home, especially West-coasters who want to get home today.

I will definitely be suffering from information overload and becoming brain-numb, but with 228 papers and an average of seven parallel sessions at any one time, plus the offsite events, that’s not really surprising. On the other hand, where else do we go to get all this amazing stuff?

Time to unwind, maybe do a little holiday shopping, and go for an indulgent meal.



  • -H. Jan et al., “A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra Low Power, High Performance and High Density SoC Applications”, IEDM 2012, pp. 44 – 47.
  • Xie et al., “A 7nm FinFET Technology Featuring EUV Patterning and Dual Strained High Mobility Channels”, IEDM2016, pp. 47 – 50

IEDM 2017 Next Week Part 1

By Dick James

On December 2nd – 6th the good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2017 IEEE International Electron Devices Meeting. To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.”

That’s a pretty broad range of topics, but from my perspective, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy.

In the last few weeks I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.


Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorials on a range of leading-edge topics:

  • The Evolution of Logic Transistors toward Low Power and High Performance IoT Applications, Dae Won Ha, Samsung Electronics.
    This tutorial will cover the evolution of logic transistors; then, state-of-the-art FinFETs, including layout, key design rules, short channel effects, multi-Vth engineering, local layout effects (LLE), variability, etc. Finally, potential future GAA (Gate-All-Around) device architectures such as MBCFET (Multi-Bridge Channel FET) and VFET (Vertical FET) will be discussed.
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden.
    This talk reviews recent progress towards brain-inspired computing architectures, ranging from systems that combine CMOS devices in different and unconventional ways, to those built around emerging NVM (Non-Volatile Memory) devices; and from systems designed to accelerate conventional ML (Machine Learning) through hardware innovation, to systems that seek to transcend the limitations of current ML algorithms, e.g. the requirement for batch-based learning using vast datasets of static and labeled data.
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, Imec
    First, Joris discusses short-reach optical interconnect scaling trends and the industry roadmap, then the variety of silicon photonics devices; how these building blocks can be combined with low-power CMOS driving circuits to implement Tb/s scale electro-optical transceivers, and finally, the future prospects for integrating GaAs and InP based laser sources on silicon by direct epitaxial growth.
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley.
    Sayeef will review the physical origin of negative capacitance, and how it can be used to amplify the electrostatic field. If combined a transistor gate, this stabilized negative capacitance could lead to supply voltage reduction and/or increase of the ON current. Current understanding of this phenomenon will be reviewed, together with possible pathways to optimize transistor performance for scaled nodes.
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University.
    Dr. Pop will explain the operation and limitations of non-volatile phase-change memory (PCM) and resistive random-access memory (ReRAM), presenting the two memory types in context, and emphasizing their thermal and energy limitations. He will also discuss modern devices, challenges, test structures, and simple models required to understand their operation.
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Venkatesh Sundaram, Associate Director, Georgia Tech 3D Systems Packaging Research Center.
    This talk will introduce interposer and fanout packaging technologies, their market drivers, application examples and infrastructure evolution, and the latest state of the art innovations. Emerging fanout technologies such as TSMC’s InFO used in Apple iPhones, Intel’s embedded bridge (EMIB) technology, and silicon, organic and glass 2.5D interposers will be reviewed.

The first three are from 3.15 – 4.45, and the remainder from 5.00 – 6.30, half an hour later than last year; but a little easier for those of us that fly in on Saturday. This year I hope to make it to the Samsung/IoT session, and possibly the packaging talk at 5.00.

On Sunday December 3rd, we start with the short courses, “Boosting Performance, Ensuring Reliability, Managing Variation in sub-5nm CMOS” and “Memories for the Future: Devices, Technologies, and Architecture”.

Last year the process short course was “Technology Options at the 5-Nanometer Node” so I guess we will see how things have evolved beyond 5 nm.

This year’s effort is organized by Sandy Liao (Intel), and will feature the following sessions:

  • Transistor Performance Elements for 5nm Node and Beyond, Gen Tsutsui, IBM.
    Gen will focus on Si- and SiGe-based FinFET technologies, and discuss transistor optimization in terms of mobility and reliability, and also discuss issues specific to the gate-dielectric interface on SiGe channels. The IBM consortium used SiGe channels in their gate-first PMOS high-k, metal gate (HKMG) devices, so there is solid experience to draw on for this part of the talk.
  • Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture, Steve CH Hung, Applied Materials.
    Steve will focus on gate-stack engineering for advanced FinFETs, in particular from a Vt-modulation perspective using work-function engineered metal-gate electrodes. We are now seeing multiple-Vt options in the leading-edge processes, so this should help us understand how that is done.
  • Sub-5nm Interconnect Trends and Opportunities, Zsolt Tokei, Imec.
    Zsolt is imec’s Distinguished Member of Technical Staff, Interconnect, and gave a talk on “Challenges of 10nm and 7nm Advanced Interconnect” as part of the IEDM 2013 short course, as well as covering “How to Solve the BEOL RC Dilemma?” at the imec Technology Forum at Semicon West this year. He will deal with EUV-related fabrication challenges, track height scaling in standard cells, novel conductor materials, as well as performance issues such as trade-offs in power rails and signal wires and circuit sensitivity to RC delay. Quite a lot to cover in an hour or so! Now we know that Intel is using cobalt interconnect in their 10-nm process, the materials segment will definitely be apposite.
  • Transistor Reliability: Physics, Current Status, and Future Considerations, Stephen M. Ramey, Intel.
    In this session we will hear about transistor reliability issues such as gate oxide integrity, self-heating and transistor aging issues like BTI and hot carrier effects; none of them new, but at 5 nm and below there may be extra complications.
  • Back End Reliability Scaling Challenges, Variation Management, and Performance Boosters for sub-5nm CMOS, Cathryn Christiansen, GLOBALFOUNDRIES.
    Cathryn will start with an overview of reliability basics and improvements established for TDDB and EM through the 7nm node, and then follow-up with a discussion of potential boosters for 5nm nodes and beyond, including asymmetric spacing, thinner barriers/liners, alternative metals, lower-k dielectrics, airgap, and self-aligned vias.
  • Design-Technology Co-Optimization for Beyond 5nm Node, Andy Wei, TechInsights.
    Andy will wrap up the short course with a presentation about design-technology co-optimization (DTCO) for beyond the 5nm node. Andy joined Chipworks (now TechInsights) a couple of years ago, and has ramped up their process and design architecture offerings by an order of magnitude. Those who attended the 2013 short course may remember his session on “Process Integration Challenges in 10nm CMOS Technology”, so he’s a seasoned speaker; and now he’s had the benefit of examining all the 16, 14, and 10-nm offerings since then, so we are likely to get some original commentary.

His topics will be:

  • I thought Moore’s Law was dead: What’s driving accelerated scaling?
  • DTCO Overview: PPA + C + TTM
  • Challenges: beyond the 40-nm pitch barrier and Gate All Around
  • Beyond 5-nm device option evaluation
  • System level innovation and future product requirements

Kevin Zhang from TSMC (formerly Intel) set up the memories short course, apposite now that we are in an era of increasing memory demand, from mobile to server to automotive, not to mention IoT, each with their own challenges.

Intel posted this graphic looking at data storage as equivalent to beer storage, which is a fun way to look at it:

disruptive tech


Of course, that was a plug for their Optane 3D-Xpoint technology, but I guess we can see the automotive use there, and IoT memory in everything from the bottle to the mega-mart…

So we have:

  • Embedded Non Volatile Memory for Automotive Applications”, Alfonso Maurelli, STMicroelectronics.
    Alfonso will review the scaling of embedded nonvolatile memories for automotive applications. He will present the key technology scaling challenges and discuss their solutions to drive eNVM technology to meet the future requirements for automotive electronics.
  • 3D ReRAM: Crosspoint Memory Technologies”, Nirmal Ramaswamy, Micron.
    Nirmal will follow with a technology overview of ReRAM technology for 3D Crosspoint Memories. This new class of memory boasts an unparalleled storage density while rivaling DRAM in terms of access latency. Micron is the other half of the 3D XpointTM partnership – will we get more details of what’s in there?
  • Ferroelectric Memory in CMOS Processes”, Thomas Mikolajick, Namlab. Thomas will discuss the key breakthroughs in ferroelectric devices that have the potential to bring this memory into CMOS-based technologies for embedded applications.
  • Embedded Memories Technology Scaling & STT-MRAM for IoT & Automotive”, Danny P. Shum, GLOBALFOUNDRIES.
    Danny will present state-of-the-art STT-MRAM memories and their applications. Spin-Transfer-Torque (STT) MRAM has drawn lots of interest in recent years due to its unique memory characteristics and scalability.
  • Embedded Memories for Energy Efficient Computing”, Jonathan Chang, TSMC. Jonathan will go through the embedded memory landscape, what is needed for energy efficient computing, SRAM scaling, eFlash for automotive, and MRAM for IoT and mobile applications, and RRAM for IoT.
  • Memory Centric Abundant Data Computing”, Subhasish Mitra, Stanford U.
    Here we will hear about the memory wall in processors and accelerators; in-memory compute, monolithic 3D Integration vs TSV 3D, interwoven memory, logic and sensor arrays using heterogeneous technologies, and abundant data applications such as graph analytics and deep learning,

I would call both courses a full day, seeing as we finish at ~5.30 p.m., but it’s worth sticking around to the end.

If you have the stamina, at 5.30 CEA-leti is holding a Devices Workshop across the street at the Nikko Hotel, and at 6.30 imec is hosting a Technology Forum at the Grand Hyatt San Francisco, on Stockton Street.



Monday morning, we have the plenary session, with three pertinent talks on the challenges and potential of contemporary electronics:


  • Multi-Chip Technologies to Unleash Computing Performance Gains over the Next Decade, Lisa Su, AMD.
    Hot on the heels of their latest batch of successful CPU launches, Lisa will explain how techniques such as system, architectural and software innovation have extended high-performance processor performance. Some of these will continue, but new innovations are needed, especially at the system level, to continue improving performance over the next decade. Multi-chip technologies and system-level innovations will be key.
  • Energy Efficient Computing and Sensing in the Zettabyte Era: from Silicon to the Cloud”, A. M. Ionescu, Nanolab, Ecole Polytechnique Fédérale de Lausanne
    This paper is a look at some of the great research challenges and opportunities for 21st Century energy efficient computing and sensing devices and systems, in the context of the IoT revolution. In future, major innovations in Information and Communication Technologies (ICT) will need holistic approaches including silicon and cloud technologies, centered on big/deep data and context. The monstrous amounts of stored, computed, communicated and sensed information will test the world’s capability of efficiently managing zettabytes of data.
  • System Scaling for Intelligent Ubiquitous Computing”, J. Y-C. (Jack) Sun, Taiwan Semiconductor Manufacturing Company.
    In this talk it looks like Jack is extrapolating what can be done when we really get 3D going:
    “Wafer based 3Dx3D system scaling revolutionizes machine learning (ML) and artificial intelligence (AI) as well as mobile computing. It may trigger a big bang in intelligent ubiquitous computing. 3D CMOS scaling continues with many challenges and opportunities for relentless innovation in materials, processes, devices, circuits, design, EDA, computing architectures, algorithms, and software. 3D stacking and heterogeneous system integration, e.g., CoWoS® and InFO, not only augments but also amplifies the benefits of 3D CMOS logic, 3D memory, integrated specialty technologies and 3D sensors for intelligent ubiquitous computing. The virtuous cycles of 3Dx3D system scaling innovation may expand like a galaxy or universe. The aggregate transistor count in a 3Dx3D sub-system may reach the equivalent of human brain in the 2020s to provide brain-like augmented intelligence.” Whew!


Three quality presentations in three hours, but beware of numb bum if you take in all of them – get up and have a stretch in between, and take a walk before lunch!

After lunch, in keeping with IEDM’s tradition of intellectual overload, we have nine parallel sessions, but this year – now we have exhibitors, we have coffee breaks!

Session 2: Memory Technology – ReRAM and Selectors

Session 2 starts a track on Memory Technology, the first of five. It begins with a paper by SK Hynix (2.1) on selector technology for a cross-point ReRAM; metal atoms were injected into oxide films, and off-current and threshold voltage (Vth) were controlled by using arsenic doping. A one selector-one resistor (1S1R) memory was successfully demonstrated.

SiO2-based ReRAM selector (source; SK Hynix/IEDM)

SiO2-based ReRAM selector (source; SK Hynix/IEDM)

Selectors are again the topic of a collaborative presentation (2.2) from Macronix and IBM TJ Watson Research, this time an Ovonic Threshold Switch (OTS) structure using TeAsGeSi, incorporating Se and an extra dopant (not stated). Excellent endurance is claimed, and robust characteristics after 350 C/30 mins annealing; and the thin film could withstand 500 C annealing. TechInsights has revealed that the selector switch in Intel’s Optane 3D XpointTM products is Se0.44As0.29Ge0.1Si0.17, somewhat similar since Te and Se are in the same group in the elemental periodic table.

Paper 2.3, from an array of French research institutes, studies the programming and reading operations in HfO2-based RRAM cells using OTS selectors, and proposing a new reading strategy. In 2.4, SMIC and collaborators describe a 28-nm, BEOL-based RRAM using one extra mask, though in the abstract they don’t give any details of its structure.

Macronix presents again (2.5) on transition metal oxide (TMO) ReRAMs, studying the retention of the high resistance state, and finding that it is composed of three stages — extending tail-bits, distribution shift, and distribution broadening. Winbond shows a SPI interface, 90-nm 512-Kbit HfO2 RRAM in 2.6; and the last paper in this session is from the Chinese Academy of Sciences (CAS), discussing an 8-layer, 3D Vertical RRAM using a self-selective cell (SSC) with non-filamentary switching. An extreme-scaled structure with 5 nm size and 4 nm vertical pitch was also demonstrated (2.7).

Session 3: Focus Session – Process and Manufacturing Technology – 3D Integration and Packaging

This session consists of invited papers, starting with a paper (3.1) that looks like a review of CEA- leti’s CoolCube monolithic 3D stacking technology. One of the challenges is keeping the thermal budget down so that the first transistor layer is not destroyed by annealing of the higher transistor layers; the authors claim that stacked FETs and ULK/metal lines between stacked tiers can be achieved with a 500°C thermal budget.

Next up, (3.2) Sony displays their 3- layer pixel/DRAM/logic stacked CMOS image sensor first detailed at ISSCC this year. Having the DRAM in the stack allows a camera system capable of 960 fps, launched in the Experia XZ Premium and XZs phones.

In 3.3 we hear about miniaturized and integrated Power Supply on Chip (PwrSoC) and Power Supply in Package (PwrSiP) platforms, from Tyndall National Institute in Eire, enabled by the application of thin-film, integrated magnetics on silicon; a process flow for, and the design of, a thin-film coupled-inductor, switching at 60 MHz, is described.

In paper 3.4, Rao Tummala of Georgia Tech takes a different look at 3D, considering the system package architecture as a way of improving latency and bandwidth between logic and memory, rather than the 3D stacking of ICs with TSVs. In contrast, GLOBALFOUNDRIES (GF) contributes 3.5, how TSVs will enable continued scaling.

TSMC’s InFO (Integrated Fan-Out) technology is the subject of 3.6, seen in the last three iPhone iterations, but not to my knowledge in any other product as yet. In their 2Q17 analyst call, C.C. Wei stated that they had put $1B capex into InFO, and revenue at that point was $500M; and volume production for other customers would not start until 2018.
The session finishes with an IBM-led team describing several novel heat removal and power delivery technologies aimed at making so-called computing cubes a reality (3.7). They tried dual-side cooling of a stack of chips, interlayer cooling, integrated voltage regulators, and electrochemical power delivery.

Schematic of stacked dies with dual-side cooling topology (source: IBM/IEDM)

Schematic of stacked dies with dual-side cooling topology (source: IBM/IEDM)

Session 4: Modeling and Simulation – Modeling and Simulation of Advanced Non-volatile Memory

Paper 4.1 is an atomistic (i.e., atom-by-atom) simulation of Ge-rich GexSe1-x materials for selector switches, coupled with experiment, so as to understand the electrical and thermal dynamics and correlate them to carrier-transport. They found that the population and localization of mobility-gap states changes solely under the effect of electric field. Nitrogen doping introduces strong covalent bonds into the material, increasing its thermal conductivity and crystallization temperature beyond 600C. Carbon dopants are found to add mobility-gap states, and nitrogen removes them.

Paper 4.2 also looks at atomistic simulations, this time of conductive bridging random access memory (CB-RAM) cells. Realistic device structures containing an atomic-scale filament have been constructed and their transport properties have been studied.
4.3 is another CB-RAM investigation, defining an active-electrode selection criterion for non-volatile and volatile switching; then simulating switching behaviour in Ag/HfO2/Pt and Co/HfO2/Pt, including the intrinsic switching time; and using this data to predict the switching behaviour of other CBRAM active-electrodes, and corroborate with experiments.

The disorder effect of oxygen vacancy distribution in filamentary analog RRAM is modeled in 4.4, and verified by experiments performed on a 1-Kb RRAM array, coming to the conclusion that disordered VO distribution is desired for analog switching.

In 4.5 we move on to 3D NAND flash memories, studying the charge diffusion in charge-trap (CT) cells, examining various hydrogen (H) and oxygen (O) incorporated defects in the SiN CT layer. The next paper (4.6) looks at wordline (WL) interference in a 32Gb 16-layer single-gate vertical-channel (SGVC) 3D NAND flash test chip, finding that the far-neighbour WL cell also contributes to the WL interference; this can be suppressed by applying a lower bitline sensing voltage.

The last talk (4.6) discusses the current transport through the thin polysilicon channel of (likely) Micron 3-D NAND flash strings, showing that variability in the polysilicon grain configuration in the channel broadens the array VT distribution when temperature is changed.


Session 5: Nano Device Technology — 2D and Carbon Nanotube Devices

This session (not surprisingly) is a set of research papers, starting with a trio of molybdenum disulphide (MoS2) transistor studies; 5.1 details gate-tunable memristors based on monolayer MoS2 grown by CVD, fabricated in a field-effect geometry with a polycrystalline MoS2 channel. In 5.2 high performance transistors with CVD graphene and MoS2 on commercially available paper substrates are demonstrated; and 5.3 exhibits a quantum dot superlattice structure fabricated on monolayer MoS2, where the quantum dots work as charge traps that induce memristive resistance, which can then be modulated by a gate-induced electric field and exhibits light stimulation.

In paper 5.4 electronic synapses were made using multilayer hexagonal boron nitride as a switching layer, showing the coexistence of volatile and non-volatile resistive switching.

Next is an invited talk on scaling carbon nanotube CMOS FETs towards the quantum limit (5.5) When combined with graphene, a high-performance top-gated CNT FET with gate length scaled down to 5 nm was demonstrated; this begins to touch the quantum limit of a FET, and involves approximately only one electron when switching between on-state and off-state.

Carbon nanotube FETs were fabricated based on solution-processed carbon nanotube film in 5.6. FETs with a gate length of 120 nm exhibited maximum drive current density of 1.7 mA/um and peak transconductance of 0.8 mS/um, which is claimed to create a new record for CNT FETs.

In the last paper, monolithic 3D-integrated dichalcogenide (MX2) FETs are benchmarked with Si FinFETs (5.7) using energy-delay as a figure-of-merit and a physical compact model. Single-gate (SG) and double-gate (DG) MX2 FETs are compared from ON current, device capacitance and energy-delay perspectives.


Session 6: Circuit and Device Interaction — Devices and Circuits for Neuromorphic and Stochastic Comparison

This topic is again covered by a set of research papers:

The first, 6.1, discusses NeuroSim+, an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of system-level learning accuracy and hardware performance metrics; in particular, the impact of the “analog” eNVM non-ideal device properties, and benchmark the trade-offs of SRAM, digital and analog eNVM-based array architectures for online learning and offline classification.

A ferroelectric FET (FeFET) analog synapse for the acceleration of deep neural network training is demonstrated in 6.2. The symmetric 5-bit potentiation and depression characteristics of the FeFET synapse resulted in 90% accuracy for image recognition after training on the MNIST database, and improved training time on 1M images by 1000× compared to demonstrated RRAM devices is claimed, while maintaining a 10× area advantage over SRAM.

Paper 6.3 proposes Random Sparse Adaptation (RSA) to efficiently recover the accuracy due to RRAM variations. RSA integrates a small, accurate on-chip memory with the main, inaccurate RRAM array. It completely eliminates the Write of RRAM, achieving 10-100X speedup in MNIST and CIFAR-10, and >10% accuracy enhancement.

The time-dependent variability (TDV) in RRAMs, and its interaction with the RRAM-based analog neuromorphic circuits for pattern recognition is investigated in 6.4. It is found that the TDV effect can introduce non-negligible recognition accuracy drop during the operating condition. 6.5 details a mixed-signal neuromorphic network with 100K+ floating-gate memory cells, based on a commercial 180-nm NOR flash memory.

In paper 6.6, the feasibility of stochastic computing (SC) circuits based on FinFET technology is investigated, with on-chip image processing as an example. Practical technical issues are carefully examined, including static and transient device variations in 16/14nm FinFET.


Session 7: Characterization, Reliability and Yield — Reliability of Advanced Devices

Gate-all-around (GAA) nanowire (NW) devices are still a research topic to me, but the first paper in this session looks at the degradation of stacked Si gate GAA-NW nFETs (7.1), resulting in a fully intrinsic GAA-NW nFET lifetime map in the entire bias space.

In 7.2 we hear about hot carrier degradation (HCD) in FinFETs, studied from a trap-based approach rather than the carrier-based approach. A new HCD time dependence was observed, not predictable by traditional models, and from this a trap-based HCD compact model is proposed and verified in both n- and p-type FinFETs.

NBTI in replacement metal gate (RMG) HKMG SiGe p-FinFETs is modelled in 7.3; time kinetics for DC and AC stress and recovery, temperature dependence of voltage acceleration factor, and the impact of Ge% and N% are quantified, and benchmarked against Si p-FinFETs, and explained by TCAD and band structure calculations.

Paper 7.4 from imec discusses the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options on ESD diode performance in next generation bulk FF and GAA technologies, using 3D TCAD and ESD characterization.

Imec is back in 7.5, examining oxide traps in InGaAs MOS gate stacks in high-mobility n- channel MOSFETs. Various trap characterization techniques such as bias-temperature instability, defect capture-emission-time maps (applied here to InGaAs devices), random telegraph noise, hysteresis traces, and multi-frequency C-V dispersion, were used, on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). They propose guidelines for developing sufficiently reliable III-V gate stacks.

A study of thermal effects in 3D sequential integration (CEA-leti’s CoolCube) is presented in 7.6, on 3D ICs made from 7nm-thick SOI wafers, with a base oxide thickness of 145nm. As we noted in 3.1, heat dissipation is an issue with monolithic stacking, because heat can negatively affect transistor electrical characteristics, performance and reliability. A particular area of concern is the need to understand the thermal effect of the second layer on the performance of devices in the first layer. The authors found that the self-heating of individual transistors is more significant than thermal coupling between the layers.

TEM image of two stacked transistors fabricated in 3D sequential integration technology (source: CEA-leti/IEDM)

TEM image of two stacked transistors fabricated in 3D sequential integration technology (source: CEA-leti/IEDM)

Session 8: Optoelectronics, Displays, and Imagers — Thin Film Transistors and Detectors

The first paper in the session presents an investigation (8.1) of flexible ultra-thin chalcogenide glass Ge2Sb2Te5 (GST) p-type thin-film transistors (TFTs). Together with n-type InGaZnO4, flexible CMOS inverters and NANDs are realized, and the devices sustain tensile bending to a radius of 6 mm.

The next paper (8.2) reports extremely stable and high performance etch-stopper a-IGZO TFTs on a plastic substrate by using split semiconductor and source/drain electrodes: the authors state that this technology can be used for the manufacturing of high resolution flexible AMOLED displays.

A printable device structure design is introduced in 8.3 to fabricate a low voltage organic field effect transistor, for low power and high sensitivity ion and fluorescence sensing, using thick gate dielectric layers and high throughput printing/coating processes.

A black phosphorus carbide infrared phototransistor with wide spectrum sensing is up next (8.4), which shows promise for IoT applications. It is followed by a paper discussing flexible paper deep UV photosensors (8.5) based on 2D BN nanosheets which have ultrahigh thermal conductivity, fast recovery-time, and excellent flexibility and bending durability.

A high-performance graphene/ultra-thin silicon metal-semiconductor-metal UV photodetector is reported in 8.6, which uses the mechanical flexibility and high-percentage visible light rejection of ultra-thin silicon. The proposed photodetector exhibits high photo-responsivity, fast time response, high specific detectivity, and UV/Vis rejection ratio of about 100, comparable to the state-of-the-art Schottky photodetectors.

A Schottky-PN cascade heterojunction short-wavelength infrared photodetector built with hyper-boron-doped silicon quantum dots on graphene is reviewed in the last paper (8.7).


Session 9: Power Devices — SiC and GaN Vertical Power Devices

This session alternates silicon carbide (SiC) and gallium nitride (GaN) papers – first up, Fuji Electric will present on a novel SBD-integrated SiC-MOSFET (9.1) with a small cell pitch; the fabricated 1.2 kV SWITCH-MOS successfully inactivated the body-PiN-diode without degradation of on- and off-state characteristics when compared with conventional UMOS.

In 9.3 Mitsubishi studied the intrinsic phonon-limited mobility and carrier transport properties of 4H-SiC MOSFETs, coming to the conclusion that surface roughness scattering does not limit inversion layer mobility in high effective normal field, suggesting that conventional mobility models need to be updated.

Schematic showing electron scattering in the inversion layer (source: Mitsubishi/IEDM)

Schematic showing electron scattering in the inversion layer (source: Mitsubishi/IEDM)

The SiC papers wrap up with an invited paper by Tsunenobu Kimoto of Kyoto U. (9.5) on “Progress and Future Challenges of SiC Power Devices and Process Technology” We can expect a review of recent progress in SiC device physics and power devices, more accurate device simulation of SiC, and details of 13 kV SiC PiN diodes ,11 kV SiC epitaxial MPS diodes, and 3 kV reverse-blocking MOSFETs.

9.2 demonstrates a 1200 V GaN vertical finFET with claimed record performance in a normally-off GaN vertical transistor with submicron fin-shaped channels; the figure of merit is up to 7.2 GW/cm2. A >1.4 kV OG-FET with a novel double field-plated geometry is detailed in 9.4, with a breakdown voltage of 900 V and an on-state resistance of 4.1 ohm.

The final GaN paper, 9.6, looks at high voltage vertical p-n diodes with ion-implanted edge termination and sputtered SiNx passivation. These are GaN-on-GaN diodes with a Baliga figure of merit of 13.5 GW/cm2, and do not require field plates or complex edge terminations to achieve material-limited performance.


Session 10: Focus Session – Sensors, MEMS, and BioMEMS — Nanosensors for Disease Diagnostics

Being a focus session, again we have a series of invited papers, starting with a review of nanofluidics for cell and drug delivery (10.1). Houston Methodist has developed implantable micronanofluidic-based platforms that leverage molecular nanoconfinement for the controlled administration of drugs and transplantation of cells using silicon nanofabricated membranes and 3D-printed polymeric architectures.

Photo and schematic of the internal structure of the Houston Methodist remote-controllable drug-delivery platform (source: Houston Methodist/IEDM)

Photo and schematic of the internal structure of the Houston Methodist remote-controllable drug-delivery platform (source: Houston Methodist/IEDM)

I tend to think of bulk acoustic wave (BAW) resonators as filters in mobile phones, but Tianjin U. has been developing them as biosensors and bioactuators (10.2). This review
covers two aspects, as biosensors to provide label-free measurement of biomarkers, and as bioactuators to manipulate biomolecules and enhance biosensing performance.

10.3 details a microfluidic device from Nagoya U., based on ionic current detection for single bacteria and mammalian cell sizing. A highly precise sizing system based on blocking ionic current at a narrow microchannel provided information on antibiotic-resistant strains of bacteria; and deformability changes associated with the passage of adipose tissue-derived stem cells (ASCs) were also successfully detected without any chemical or biological modification.

The next paper (10.4) from Seoul National U. describes a rapid antibiotic susceptibility test (RAST) system composed of biochips and an automated expert system, which can determine the antibiotic susceptibility of bacteria and mycobacteria derived from various parts of the body. With RAST, antibiotic susceptibility was available in six hours, versus conventionally taking more than two days.

In 10.5 Reza Mohamadi from U. Toronto next describes the microscale profiling of circulating tumor cells (CTCs), which are potential cancer markers; they are heterogeneous and can change as they enter the bloodstream, so profiling them at single cell level is critical to unraveling their complex and dynamic properties. This paper discusses new nanoparticle-enabled microscale technologies for CTC classification, which characterizes them based on their surface expression profile.

Cancer is also the subject of 10.6, from multiple institutes of the Grenoble research complex, which discusses encapsulated organoids and an organ-on-a-chip platform for cancer modeling. An example is given of “prostate-on-a chip” developments to illustrate the potential of engineered organ-on-chip devices for creating novel human organ and disease models.

A team from U. British Columbia (10.7) have developed a microfluidic flow-focusing method to create multicellular, 3-D spheroids that can better model several aspects of a tumour in vivo, including diffusion gradients of O2 and drugs. This drives the need to image deep within the tissues to assess parameters such as cell viability at the tissue cores, or drug penetration into the tissue as a function of time. They developed an on-chip method to rapidly clear arrays of 3-D cell cultures and micro-tissues, compatible with two-photon microscopy to track drug and nanomedicine penetration into the tissues.

That brings us to the end of the Monday afternoon sessions, and the reception will start at 6.30 pm in the Grand Ballroom.



Session 11: Focus Session – Memory Technology — Modelling Challenges for Neuromorphic Computing

Again, all invited papers – the session starts (11.1) with a discussion from UC Irvine on “Stochastic Synapses as Resource for Efficient Deep Learning Machines”; it is shown that always-on stochasticity at networks connections is a sufficient resource for deep learning machines, when combined with simple threshold non-linearities. The findings can improve performance of deep learning machines with fixed point representations, and argue in favor of stochastic nanodevices as primitives for efficient deep learning machines.

Paper 11.2 presents a summary of recent results toward implementing RRAM-based attractor networks. Using realistic models of HfO2 RRAM devices, recurrent networks were designed and simulated, showing the capability to train, recall and sustain attractors; this supports the feasibility of RRAM-based bio-realistic attractor networks.

The next talk (11.3) comes from a different angle – studies of the human brain show that synapses in the brain do not maximise information transfer, but instead transfer information in an energetically efficient manner. This implies a high failure rate in the transmission of individual information-carrying signals, which may be an important design principle when considering trade-offs between energy use and information transfer in man-made devices.

11.4 reviews the understanding of the trade-offs of device, circuit and application in ReRAM-based neuromorphic computing systems, through the discussion of three major problems — weight mapping, reliability, and system integration.

We again consider RRAM in 11.5; the device structure and materials stack detailed in the paper were optimized to achieve reliable bidirectional analog switching behavior. A human face recognition task was demonstrated on a 1k-bit 1T1R RRAM array using an online training perceptron network, and several RRAM characteristics were carefully evaluated for a handwritten digit recognition task.

Paper 11.6 also highlights the feasible routes of using RRAM for accelerating online training of deep neural networks (DNNs). Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.

We go to the atomic level in last talk in the session (11.7), which discusses a modeling platform connecting atomic material properties to electrical device performance, in relation to neuromorphic computing devices. The main ingredients of the platform are reviewed considering the different technologies (e.g. RRAM, PCM, FTJ) proposed for 3D-integrated neuromorphic computing.


Session 12: Circuit and Device Interaction — Circuit-Device Challenges in More Moore and More than Moore

Paper 12.1 details twin-mode non-volatile logic gates that allow multiple logic functions to be obtained by controlling its non-volatile states, that are fabricated in a standard 16-nm FinFET process. The floating metal-gate based cells consist of an inverter controlled by slot contact.

Physical unclonable functions (PUFs) are considered in 12.2. Here we have a new PUF design based on a double-layer RRAM array architecture and digital RRAM programming, achieved by splitting resistance distribution after a continuous distribution was formed. It was implemented on a 16 Mb RRAM test chip, and its randomness was verified with a NIST test suite, and demonstrated strong reliability and significantly enhanced resistance against machine-learning attack.

12.3 is an invited paper from MIT – “Large-Scale Terahertz Active Arrays in Silicon Using Highly-Versatile Electromagnetic Structures”. The small wavelength of terahertz (THz) signals and the high integration capability of silicon processes make it possible to build a high-density, very-large-scale active THz array on a single chip. There are problems though; most conventional circuit designs are area-inefficient, leading to unnecessarily large chips.

MIT has designed a set of compact while versatile circuits, using structures with tight device-electromagnetic integration that exhibit multi-mode behaviors. Put on silicon, that can achieve homogeneous arrays for high-power, collimated radiation, or alternatively, heterogeneous arrays for fast broadband spectral scanning. They demonstrate an example with 0.1-mW power generation (20-mW effective isotropically-radiated power) at 1 THz, simultaneous transmit/receive capability, and high-parallelism molecular spectroscopy.

Peking U. gives another invited talk in 12.4 about variability- and reliability-aware design for 16/14nm (and beyond) technologies. Accurate compact models and a new design methodology for random variability in FinFETs are proposed for the variation- and correlation-aware design.

For the reliability awareness, the impacts of BTI-induced temporal shift and the layout dependent aging effects should be taken into account for the optimization of end-of-life (EOL) performance/power/area (PPA). A new-generation aging model and circuit reliability simulator for FinFETs are also proposed and developed in industry-standard EDA tools.

TSMC discusses (12.5) a bit-level characterization method for benchmarking finFET SRAM performance under the influence of leakage current; whether it be due to intrinsic or extrinsic device failure, it can severely impact the 6-T SRAM performance. This study introduces a ‘Pseudo-Leakage’ current source in the SRAM circuit and analyzes the impact on the overall SRAM performance matrices.

Computing-in-memory (CIM) is becoming a hot topic now that memory interfaces have become the data bottleneck in systems; paper 12.6 describes a monolithic 3D vertical cross-tier computing-in-memory SRAM cell, fabricated using a low cost TSV-free FinFET 3D+-IC technology. The 9T 3D CIM SRAM cell is able to compute NAND/AND, OR/NOR and XOR/XNOR operations within a single memory cycle.

The stackable, multi-fin, single-grained Si FinFET was fabricated using low thermal-budget CO2 far-infrared laser annealing (FIR-LA) for activation, and self-aligned silicide. This monolithic 3D device reduces area overhead by 51%, compared to the 2D version, thanks to the stacking of three additional transistors above the 6T SRAM cell.


Session 13: Modeling and Simulation — Modeling and Simulation of Advanced CMOS Transistors

In 13.1 hot-carrier degradation (HCD) in FinFETs is analyzed. A physics-based HCD model was used to study the distribution of the trap density across the fin/stack interface, after experimental validation. The effect of fin length, width, and height on HCD was analyzed, showing that HCD is worse in shorter and wide-finned devices, with little impact from fin height.

13.2 is a comparison of FinFETs, stacked nanowires (NWs), circular and square gate-all-around 𝑛-FETs, using a deterministic BTE solver that accounts for quantum confinement, a wide set of scattering mechanisms and self-heating. Surface roughness is shown to reduce the improvement in I𝑜𝑛 expected in stacked NWs compared to FinFETs, and whether or not In0.53Ga0.47As can provide better I𝑜𝑛 than strained silicon.

Monte Carlo benchmarking of FinFETs with LG 20, W 9 nm shows that InGaAs has similar performance as Si for Vdd of 0.5 V (13.3). However, ideal InGaAs-FinFETs lose all advantage upon reducing W to 5 nm because of a charge reduction due to n-type channel doping.

13.4 is an invited review paper, looking at modelling nanoscale n-MOSFETs with III-V compound semiconductor channels, from advanced models for band structures, electrostatics and transport to TCAD. 13.5 discusses a ferroelectric transistor model for FEFETs/NCFETs without an inter-layer metal between ferroelectric and dielectric in the gate stack.

The final paper (13.6) considers self-heating effects (SHE) in FinFETs, NWFETs, and nanosheet-FETs. The IC-specific SHE reflects increasing thermal resistances (Rth) associated with the transistor, circuit, and system of the hierarchy. Physics-based compact models are developed for each tier, then stacked to estimate junction temperature-dictated performance/reliability of sub-10nm technologies. The authors concluded that nanosheet-FETs are good candidates at sub-10nm nodes, with a lower subthreshold swing than FinFET, and better reliability than NWFET.


Session 14: Process and Manufacturing Technology — Interconnect Patterning and Memory Integration

The first paper is a trip down memory lane by Dan Edelstein of IBM (14.1), marking the 20th anniversary of the introduction of copper interconnect into the metal/dielectric stack of ICs. Twenty years ago, Dan presented at IEDM ’97:

fig 7


With the accompanying colorized cross-section:

cross section
Copper interconnect is now in its 10th generation of manufacturing, and 12th in research, but as we will see in Intel’s paper (29.1), cobalt is being used in their 10-nm process, so copper may have run its course in leading-edge technologies.

The second talk is by one the Albany consortia (14.2), detailing a fully aligned via BEOL integration scheme at 36 nm pitch, with claimed extendibility to beyond the 7-nm node. We get exotic in 14.3, with an all-carbon interconnect scheme that integrates horizontal multilayer graphene wires and vertical carbon-nanotube vias. It is reported that it surpasses copper in terms of performance, energy efficiency, and reliability down to the 5-nm node.

After the coffee break Bob Turkot of Intel gives an invited talk on “Continuing Moore’s Law with EUV Lithography” (14.4), reviewing the current status and challenges of EUV lithography for high volume manufacturing. Source power is now up to 250W, and throughput is >125 wafers/hr, so “insertion” is anticipated in the next year, and Samsung claims it will using EUV for its 7-nm generation.

Now that we have cobalt interconnect going into production, it needs to be inspected, and Applied Materials is up next (14.5), describing a non-destructive electron beam cobalt void detection method. This uses an improved SEM imaging technique that is shown to correlate the electron signal to the volume and depth of voids in the metal.

The last presentation (14.6) switches to memory, discussing the improvement of HfO2-based RRAM performance by local Si implantation; this is claimed to enable switching area localization, and to significantly decrease forming, set and reset voltages, and improving data retention, while not being detrimental for endurance.


Session 15: Nano Device Technology — Negative Capacitance and Other Steep-Slope Devices 1

First up in this session (15.1), GLOBALFOUNDRIES discusses a “14nm Ferroelectric FinFET Technology with Steep Subthreshold Slope for Ultra Low Power Applications”. Here they have integrated doped hafnia ferroelectric layers into their 14nm FinFET technology, without any further process modification, and demonstrated ring oscillators operating at frequencies similar to regular dielectrics, while improved subthreshold slope reduces their active power.

Ferroelectric negative capacitance finFETs are investigated using transient TCAD simulation in 15.2; the proposed FinFETs are expected to operate at 0.25 V and thus are promising for low-power applications. The first hysteresis-free Ge CMOS FinFETs are reported in 15.3, exhibiting sub-60mV/dec subthreshold slope (SS) in both forward/reverse sweeps at room temperature with ferroelectric Hf0.5Zr0.5O2 (HZO) and Al2O3/GeOx.

15.4 discusses Ge NWFETs with a HfZrOx ferroelectric gate stack, exhibiting SS <60 mV/dec and examining biasing effects on ferroelectric reliability; and 15.5 is an investigation of the frequency dependence of performance in Ge negative capacitance (NC) pFETs.

Next is a proposal and demonstration of an oxide-semiconductor/(Si, SiGe, Ge) bilayer tunneling field effect transistor (15.6), and in the last paper (15.7) we hear about crystal-oriented black phosphorus TFETs with transport directions aligned to the armchair and zigzag crystal orientations. Strong band-to-band- tunneling anisotropy is observed between the two orientations, with a subthreshold slope nearing the thermionic limit of 22 mV/dec at 110 K.


Session 16: Optoelectronics, Displays and Imagers — Image Sensors and Single-Photon Detectors

Sony is a dominant force in image sensors, and they start this session with a description of a CMOS image sensor (CIS) photon-detector targeted on replacing photo multiplier tubes (16.1). 15-µm pitch active sensor pixels with complete charge transfer and readout noise of 0.5 e- RMS are arrayed, and their digital outputs are summed to detect micro light pulses. Successful proof of radiation counting is demonstrated.

16.2 also details a radiation imaging device, this time using SOI pixel technology. Issues of the back-gate effect, coupling between sensors and circuits, and the TID effect have been solved by introducing a middle Si layer. A small pixel size is achieved by using the PMOS and NMOS active merge technique.

Next we have a report (16.3) on a backside-illuminated germanium-tin (GeSn) large-area, tensile-strained and single-crystal photodiode array, formed on a quartz substrate by using laser-induced liquid-phase crystallization. Since quartz is transparent to NIR frequencies, and is compatible with silicon, GeSn near-infrared (NIR) imagers could be integrated with silicon CMOS circuitry.

Sony continues the NIR theme in 16.4, demonstrating NIR sensitivity enhancement of back-illuminated CIS by forming pyramid surface structures on crystalline silicon and using deep trench isolation (DTI). The diffraction on the pyramids results in a quantum efficiency of more than 30% at 850 nm. Using a special treatment process and the DTI, without increasing the dark current, the amount of crosstalk to adjacent pixels was decreased, providing resolution equal to that of a flat structure.

STMicroelectronics has succeeded in getting their SPAD (single-photon avalanche diode) technology into the iPhone 7 and 8 series, and the iPhone X, and in 16.5 they report pushing into the 40-nm node; a high fill factor >70% is claimed, a low dark count rate (DCR) median of 50 cps at room temperature and a high photon detection probability (PDP) of 5% at 840 nm, as well as the potential to 3D-stack the device.

A back-illuminated 3D-stacked SPAD using 45-nm CMOS is shown next (16.6). This has a DCR of 55.4cps/µm2, and a maximum PDP of 31.8% at 600nm, over 5% in the 420-920nm wavelength range.


Session 17: Compound Semiconductor and High Speed — 1D and 2D III-V Nanoscale MOSFETs
This session is where we get to hear more about vertical nanowires (VNWs) and other exotica. That’s what we have in 17.1, where high performance, dry etched In0.53Ga0.47As vertical nanowire and nanosheet devices are reported, fabricated using a VLSI compatible flow.

Left: TEM cross-section of the width of a 37x480nm single nanosheet FET device Right:TEM of vertical nanowire resistor after transmission line measurement (TLM) fabrication (source:  IEDM/KU Leuven/imec)

Left: TEM cross-section of the width of a 37x480nm single nanosheet FET device Right:TEM of vertical nanowire resistor after transmission line measurement (TLM) fabrication (source: IEDM/KU Leuven/imec)

More InGaAs VNWs are detailed next (17.2), fabricated by a top-down approach using reactive ion etching, alcohol-based digital etch and Ni alloyed contacts. Record ON current and peak transconductance are obtained in a 7-nm diameter device. Excellent scaling behavior is observed with performance increasing as the diameter is shrunk down to 7 nm.

17.3 considers sub-100-nm gate-length scaling of InAs/InGaAs VNWs on silicon with gate-lengths ranging from 25 to 140 nm. The heterogeneous integration of InGaAs MOS-HEMTs and Si-CMOS on 200 mm wafers is discussed in 17.4; the HEMT epitaxial layers, with threading dislocation density of lower than 2 × 107 cm-2 are demonstrated using MOCVD and an effective mobility of 4900 cm2/V·s at sheet carrier density of 3 × 1012 cm-2 is achieved.

A scaled replacement-metal-gate InGaAs-on-Insulator n-FinFET on Si is detailed next (17.5), and 17.6 has self-aligned InGaAs FinFETs with 5-nm fin-width and 5-nm gate-contact separation fabricated through a CMOS compatible front-end process. Precision dry etching of the recess cap results in metal contacts that are about 5 nm away from the intrinsic portion of the fin. The last paper demonstrates an InGaSb p-channel FinFET (17.7) with a narrowest fin width of 10 nm, a gate length of 20 nm, and a fin width/channel thickness aspect ratio > 2. To fabricate the devices, a new antimonide-compatible digital etch was developed.


Session 18: Sensors, MEMS, and BioMEMS — Bio and Chemical Sensors

The first paper describes a Lab-on-Skin that is a fully integrated, low-power, multi-sensing smart system that can passively collect sweat and measure its biomarker content in real-time, from a team led by EPFL (18.1). It is built using wafer-level techniques, and features the 3D-stacking of ion-sensitive, fully depleted SOI (FD SOI) FETs and micro/nanofluidic sensing channels created with the commonly used SU-8 negative photo resist.

Schematic of Lab-on-Skin; the two top layers depict the design of the sensing and microfluidic layers, while the bottom layer is a wafer-level view after the ion-sensitive FETs and the first layer of SU-8 passivation have been fabricated.  (source: IEDM/EPFL)

Schematic of Lab-on-Skin; the two top layers depict the design of the sensing and microfluidic layers, while the bottom layer is a wafer-level view after the ion-sensitive FETs and the first layer of SU-8 passivation have been fabricated. (source: IEDM/EPFL)

18.2 presents a strategy to design and fabricate a skin-like nanostructured biosensor system for non-invasive blood glucose monitoring. 18.3 details a mechanical-field-coupled thin-film transistor (TFT) intended for mechanical sensor applications. A tactile sensor was demonstrated with high sensitivity that can detect a gentle dynamic touch down to mN, and a wearable piezoelectric self-driven heart rate monitoring device with only µW-range power consumption.

The study in 18.4 presents a wearable and flexible temperature sensing circuitry for a diagnosis of skin temperature. The system is based on a carbon nanotube (CNT)-based temperature sensor array, built on cotton yarn using a mixture of multi-walled (MW)-CNTs and PDMS (polydimethylsiloxane). To divide and select the unit thermistors, a normally-off memristor was used.

18.5 describes a monolithically integrated Si-CMOS-monolayer-graphene gas sensor, joining the two-dimensional material with low latency, low power, low-cost silicon CMOS. Fujitsu has developed a two-dimensional SnS2-based gas sensor in 18.6. It can detect HCHO, a gas causing “Sick Building Syndrome,” with concentrations down to 1ppb.

These seven sessions take us to lunchtime when, instead of the usual Conference Luncheon, we have the IEDM Entrepreneurs Luncheon in Continental 4 ballroom, featuring Courtney Gras, Executive Director for Launch League, a local nonprofit focused on developing a strong startup ecosystem in NE Ohio.


Session 19: Memory Technology – Charge Based Memories and Advanced Memories
A 128Gb (MLC)/192Gb (TLC) Single-Gate Vertical Channel (SGVC) architecture 3D NAND is described by Macronix (19.1) using only 16 layers. It makes use of arrays of vertically arranged single-gate, flat-cell thin film transistors with an ultra-thin body, which aren’t as sensitive to CD variation as the industry-standard GAA devices. SGVC has the important advantage of much smaller cell size and pitch scaling capability which allows very high-density memory at much lower stacking layer number.

Schematic diagram illustrating the advantages of the SGVC flat-channel device  (source: IEDM/Macronix)

Schematic diagram illustrating the advantages of the SGVC flat-channel device (source: IEDM/Macronix)

TEM cross-sectional views in the (left) channel length and (right) width directions  (source: IEDM/Macronix)

TEM cross-sectional views in the (left) channel length and (right) width directions (source: IEDM/Macronix)

In 19.3 Renesas has managed to adapt the split-gate flash structure to the finFET structure, presumably sourcing from TSMC and Samsung since they mention 14- and 16-nm processes. A finFET SG-MONOS eFlash array is successfully operated and tight Vth distribution is confirmed, even after retention. This paper raises some questions in my mind – have they converted it to replacement metal gate? Do we have the fin etch-back and epi growth? This should be interesting…

GLOBALFOUNDRIES has been publicizing their MRAM recently, and 19.7 is a presentation on that very topic from their Dresden fab. They show a ferroelectric field effect transistor (FeFET) based eNVM solution for a 22nm FDSOI CMOS technology (22FDX). FeFET cells are aggressively scaled to 0.025 μm² with memory windows of 1.5V, and endurance up to 10E5 cycles.

Schematic of eMRAM cell  (source: GLOBALFOUNDRIES)

Schematic of eMRAM cell (source: GLOBALFOUNDRIES)

Session 20: Circuit and Device Interaction – Path-Forward for Advanced CMOS Scaling

This session starts with an Intel paper on interconnect scaling (20.1) which as we know is a key performance limiter instead of the transistors. They show a 35% performance improvement obtained by device-circuit-architecture solutions, using reconfiguration of buffered interconnects and execution architecture.

20.2 is from GLOBALFOUNDRIES, discussing the benefits, trade-offs and limitations of aggressive fin width scaling down to 1.6 nm on logic and SRAM device characteristics, and also considering an AC performance boost opportunity from gate length scaling along with fin width scaling.

In 20.3, it looks as though CEA-Leti is studying the possible double-gate operation of the top transistor in a monolithic 3D stack, and they have done extensive layout and spice simulations of standard cells and SRAMs.

Imec continues reporting on their nanosheet technology (20.4), showing 5.5-track standard cells with gate pitch of 42 nm and metal pitch 21 nm. They demonstrate that three stacked nanosheets are competitive with FinFETs made with two fins, while relaxing the constraints on design rules.

20.5 is another imec nanosheet paper; “Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm”. It discusses SRAM scaling beyond the 5nm technology node, and highlights the fundamental scaling limits due to FinFET and GAA technology. A vertically stacked lateral nanosheet architecture using a forked gate structure is proposed, showing superior performance and area scaling with limited additional processing complexity.

Georgia Tech updates Rent’s power-law (20.6), addressing the inability of the current approach to accurately capture standard cell level, and design characteristics that are inherent to the way we design microprocessors today. The proposed models are validated against state-of-the-art commercial microprocessors at 14/16nm, 10nm and 7nm process nodes, and the results illustrate the importance of design-specific technology prediction.


Session 21: Characterization, Reliability and Yield – Memory Reliability

TSMC presents (21.1) on the effect of external magnetic fields on embedded perpendicular STT-MRAM technology qualified for solder reflow. They show that the most critical polarization direction is writing from a parallel to an anti-parallel state, with an external field opposed to both the final free layer direction and the bottom pinned layer direction. Various other key factors including temperature, write condition and MTJ film stack were also studied.

In 21.2, an epi-Si process is used to investigate the impact of traps and grain boundaries in vertical 3D NAND. The defects are shown to have a reduced impact on device performances compared to the usual poly-Si channel devices. These results are also confirmed and extrapolated to other geometry using 3D TCAD simulations.

Now that 3D NAND is in volume production, we are starting to see more detailed reliability studies. In 21.3, Micron examines the impact of temperature on RTN fluctuations in 3D NAND flash cells. The average amplitude of RTN fluctuations increases when temperature is reduced. This is explained by TCAD simulations, in terms of stronger nonuniformities in the polysilicon channel inversion at lower temperatures, increasing the dVT of traps at or close to the polysilicon grain boundaries.

In 21.4 a physical mechanism for random-telegraph-noise (RTN) in oxide based resistive switching memory (Ox-RRAM) is proposed, with the new insight that current fluctuation can be attributed to the activation and deactivation of oxygen vacancies (VO) in the filament gap region. A RTN-based VO probing method is proposed to analyze the properties of each VO and detect the VO count in the filament gap region, and can establish a connection between the microcosmic VO properties and the Ox-RRAM reliability. The tail bits of high resistance state are shown to originate from the redundant VO generation in the filament gap region in the ineffective RESET phase, and an optimized operation scheme is presented to suppress the tail bits.

IBM Research gives an invited review of the fundamental limitations of existing models and future solutions for dielectric reliability and RRAM applications (21.5) The Weibull/ Poisson model and constant field-acceleration E-model are useful for more-or-less ideal situations, but new applications and experimental findings have challenged and exposed the fundamental limitations of these decades-old models. Recent advances in atomistic simulation and microscopic modeling provide fresh insights for the correct choice of field/voltage acceleration models.

SK Hynix details reliability improvement in DRAMs (21.6) by using a silicon migration technique by hydrogen annealing after a dry etch to form the saddle-fin structure in a 2y-nm 4Gb DRAM. The anneal reduces the interface trap density, enhancing the variable-retention-time and row-hammering immunity. Now that we are into the 10-nm class, this is likely to be even more important; at last year’s IEDM, a SK Hynix spokesman said that he hoped to get four nodes out of the 10-nm, and most road-maps I’ve seen have at least three.


Session 22: Process and Manufacturing Technology – Advanced Metal Gate and Contact Technology

The IBM/Samsung/GLOBALFOUNDRIES trifecta kicks off the session with a look at VT tuning in stacked nanosheet gate-all-around (GAA) transistors (22.1). VT can be modulated through work-function metal (WFM) thickness as well as the inter-nanosheet spacing (Tsus); combining the two can increase the number of undoped VT offerings.

If you believe Applied Materials (22.2), RMG gate fill will be using cobalt, in a reflow process, combined with a thin barrier layer for future node FinFET and gate-all-around technology.

IBM/GLOBALFOUNDRIES details a manufacturable CMOS dual solid phase epitaxy (SPE) process in 22.3, on both NFET and PFET in a 7-nm technology. Contact resistivity is reduced by both the conventional approach of high in-situ doped epi and the novel SPE processes.

22.4 is a comprehensive study of Ga activation in Si, SiGe and Ge. A low Ti/p-Ge contact resistivity of 1.2×10-9 ohmic·cm2 is approached using Ga doping and low temperature activation, while a record-low contact resistivity for p-Ge down to 5×10-10 ohmic·cm2 with a high activation level of 5×1020cm-3 is achieved using nanosecond laser activation.

22.5 Cluster-Preforming-Deposited Amorphous WSin (n = 12) Insertion Film of Low SBH and High Diffusion Barrier for Direct Cu Contact

In 22.5, the insertion of WSi12 films reduces the Schottky barrier height to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions. It also extends TDDB lifetime to >10 years at 100ºC under 5 MV/cm stress for Cu MOS capacitors, potentially enabling direct Cu contacts at S/D in advanced CMOS.

Session 23: Nano Device Technology – Negative Capacitance and Other Steep-Slope Devices 2

The scaling potential of negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) are studied for technology nodes down to 2nm (23.1). TCAD simulation evidence is presented that negative capacitance enables FinFET and FDSOI scaling to the 2 nm node, showing Ioff < 100nA/um and 10%~29% higher Ion compared with 2nm FinFETs and FDSOI. Also, NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI.

In 23.2, HfAlOx NCFETs with gate strain exhibit 66% Ion enhancement and 27% Vt reduction. Additional defect passivation can mitigate the interface depolarization field and help to reinforce surface potential amplification effect.

Ferroelectric Al:HfO2 NCFETs are demonstrated (23.3) with SS of 40 mV/dec and 39 mV/dec for forward and reverse sweep, respectively.

23.4 is an investigation of the physics and technology of the electronic insulator-to-metal transition (E-IMT) effect to create predictive model showing that, for reliable operation, the maximum ON/OFF ratio of an E-IMT device should follow a square-root relation with the strength of the thermally driven insulator-to-metal transition (T-IMT).

It was verified by systematic experiments using prototypical VO2 E-IMT devices, achieving a record value of reliable E-IMT with an ON/OFF ratio of 3.5×103 at 1.2 V, more than 10x improvement over the previous state-of-the-art. A record low voltage of IMT switching at 0.3 V (ON/OFF ratio =20) was also demonstrated.

Steep-slope MoS2 NC-FETs with ferroelectric HZO and IMG are demonstrated in 23.5. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSFor=37.6 mV/dec and SSRev=42.2 mV/dec. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and simulation.

A high-performance and low-power MoS2 NCFET is demonstrated in 23.6, with ultra-low subthreshold swing (SS) of 23 mV/dec, sub-60 mV/dec over 6 orders of ID, nearly hysteresis-free, small |Vth|

A NbO2 based threshold switch device is detailed in 23.7; the NbO2 threshold switching (TS) device is connected in series with the gate side of a MOSFET. Thanks to the TS device showing an abrupt transition between the OFF and ON states at threshold voltage (Vth), the implemented transistor exhibits extremely low leakage current (10-7μA/ μm), high ION/IOFF ratio (>106), sub-2 mV/dec subthreshold swing, drift-free characteristic and high temperature operation (>85°C). The Vth is also tunable by controlling the thickness of the NbO2 TS device, so the NbO2-MOSFET can fulfill various demands of operating bias conditions.


Session 24: Optoelectronics, Displays and Imagers – Silicon Technology Based Optoelectronics

As we noted earlier (16.5), STMicroelectronics has penetrated the iPhone bill of materials with their time-of-flight sensors, which have a VCSEL mounted on the die; the next step is to integrate the laser into the CMOS platform, now detailed in 24.1 in a joint paper from U. Grenoble Alpes and STMicroelectronics. They show the integration of a hybrid III-V/Si laser into a fully CMOS-compatible 200mm technology; the fabrication flow is fully planar and compatible with the large-scale integration of silicon photonics circuits.

24.2 is an invited talk discussing direct bandgap group IV materials, GeSn/SiGeSn heterostructures and resulting quantum confinement effects for laser implementation. The 32-nm SOI process from (I guess) GLOBALFOUNDRIES is used by UCal and MIT (24.3) to demonstrate a monolithic silicon photonic platform in an unmodified 32nm SOI CMOS process. This platform provides the fastest transistors ever monolithically integrated with photonics.

A Ge based, steep switching (114 mV/dec), directly tunnel-modulated LED/laser light source (Germanium Zener-Emitter) and sub-thermal voltage-switching (31 mV/dec) photodetector (Germanium Esaki-Collector) is reported in 24.4, for the potential monolithic integration of an optical transceiver on silicon (100).

A 25 Gbps electro-optic Pockels modulator is integrated on to silicon (24.5); the devices, based on barium titanate thin films on 200 mm wafers, show excellent VpiL (0.3 Vcm) and VpiLa (1.7 VdB), high-speed operation (25 Gbps), and low static power tuning (100 nW).


Session 25: Power and High-Speed Devices – Novel Device Concepts

In the first paper, led by Panasonic (25.1), high current and high voltage AlGaN/GaN MIS-HFETs on Si are demonstrated, with a drain current of 20 A and breakdown voltage of 730 V, serving normally-off operations; the devices use an AlON gate insulator.

Next, in 25.2, a normally-off power switching device with interdigitated MIS-HEMT and lateral-SBD sharing common ohmic contacts and access regions is described, exhibiting a Vth of 1.7 V, RON of 12.1 Ω•mm, BV of 698 V, and reverse turn-on voltage of 0.6 V.

Paper 25.3 demonstrates improvement of the linearity of GaN-based high electron mobility transistors (HEMTs) through VT- engineering and self-alignment through channel-fin-formation. Lateral diamond MOSFETs operating in the deep depletion regime have been experimentally demonstrated in 25.4, exhibiting already impressive features: 200 V breakdown with 0.6 nA/mm gate and drain leakage, 4 MV/cm peak electric field at breakdown even without the use of field plates, and carrier mobility between 1000 and 1700 cm²/V.s.

In 25.5 NXP shows off a new 5V-EDMOS device (BV ~ 10V) comprising a stepped gate oxide and a dummy gate, which boosts the RF performance to a record fMAX (~ 450 GHz), very high fT (~ 90GHz) and small device degradation, fabricated in a baseline 40-nm CMOS technology.

We don’t often see filter technology at IEDM , but every mobile phone has them; here (25.6) Akoustis Technologies reports on a high-rejection 5.2-GHz wideband bulk acoustic wave filter using undoped single crystal AlN-on-SiC resonators. The filters had an absolute 4dB bandwidth of 151 MHz, a minimum insertion loss of 2.82 dB and rejection >40 dB. Resonators show k2eff of 6.32%, Q of 1523, and FOM of 96.


Session 26: Sensors, MEMS, BioMEMS – Technologies for Neural Activity Monitoring and DNA Analysis

In 26.1, low impedance transparent graphene microelectrode arrays are fabricated for artifact-free electrophysiological recordings. Transparent graphene electrodes eliminate light-induced artifacts during optical imaging and optogenetic stimulation.

A passive Si photodiode array, aiming to establish a miniaturized optical recording device for in-vivo use is described in 26.2. The array features high yield (>90%), high sensitivity (down to 32 μW/cm2), high speed (1000 frame per second by scanning over up to 100 pixels), and sub-10uW power.

26.3 reports that arrays of vertical gallium phosphide nanowires are promising materials for biosensing in membranes and cells. Additionally, nanowires were used to investigate the interactions of high aspect ratio nanoparticles with living cells and tissue.

The integration of FinFETs and 3D nanoprobes devices on a common bio- platform is discussed in 26.4, for monitoring the electrical activity of single neurons.

The direct characterization of cell-free DNA (cfDNA) in blood plasma using µLAS technology (26.5) allows the quantification of the size distribution of purified cfDNA in a few minutes, even when its concentration is as low as 1 pg/µL. It is also shown that DNA profiles can be directly measured in blood plasma, to speed up the cfDNA analytical chain.

26.6 details nanopore devices integrated with ITO gate electrodes, that are used for electrical gating of DNA at different folding states; pore diameters are <10nm and lengths ~30nm. The gate bias modulates the DNA translocation, and as VG goes from
-0.5V to 0.5V, the count of folded-once events increases by ~5.5X relative to that of unfolded ones, indicating electrical modulation of the effective pore cross-section.


After the sessions finish Applied Materials will be having their usual IEDM off-site gathering, at the Parc 55 hotel at 5 pm, and Coventor is also hosting a panel discussion in the Hilton, also at 5 pm.


Session 27: IEDM Evening Panel

Instead of the usual two competing panels, we have one panel this year, moderated by Philip Wong of Stanford; tentative panelists are Kaizad Mistry (Intel), Kevin Zhang (TSMC), Jong Shik Yoon, (Samsung), Chidi Chidambaram (Qualcomm), Kazu Ishimaru, (Toshiba Memory), TY Chiu (SMIC), and Hughes Metras (CEA-LETI). The topic will be “Where will the next Intel be headquartered?”. Despite the focused title, this is intended to be a wide-ranging discussion on the future of the semiconductor industry and how it could evolve in the next ten years.

Stay tuned for more preview of IEDM 2017…

Intel Unveils More 10nm Details

By Dick James

On March 28, Intel held a Technology and Manufacturing Day in San Francisco, not surprisingly focusing on the work of the Technology and Manufacturing Group (TMG) within the company. This event was an exposition of the 10nm process, a new 22FFL ultra-low-power process, a quick mention of EMIB packaging, a plug for the enhanced 14nm technologies, some more marketing of Intel foundry, and all within the context of “Moore’s Law is alive and well at Intel!”



Getting straight to the 10-nm presentation, which was the fourth of the day, Kaizad Mistry unveiled some of the mysteries:

He put the numbers up remarkably quickly:


We had speculated in the last blog that self-aligned quadruple patterning (SAQP) would be used for the fins, and it would be “really ambitious” for metal definition; and Intel have surprised us by being really ambitious! Going below 40nm takes us into the realm of SAQP, or alternatively LELELE (litho-etch, litho-etch, litho-etch), adding to the complexity and cost of the process; Intel obviously considers the extra bump in density worth the cost. It also likely sets them up for the next node; take the pain now, and hopefully reduce the time to 7nm!

The gate pitch was announced at IDF as 54nm, and we now know the fin pitch is 34nm, the metal pitch is 36nm, and the cell height is 272nm. Taller fins were also mentioned, and indeed we have that, with an increase from 42 to 53nm:


Putting a ruler on the fins, we come up with a fin width of 5 – 15nm, and ~7nm at half height. Gate width is ~110nm, compared with the ~85nm of the previous generation. Gate length is still an unknown, but we can speculate that it will be in the 18 – 20nm range, assuming dielectric thickness of ~8nm between the gate and contacts.

Kaizad claimed a 25% performance improvement, with another 15% to come from the 10++ version in a couple of years, and corresponding power reduction to 0.55x, and 0.7x for the 10++ sub-generation.

Two other elements of the hyper scaling were also detailed; contact over active gate (COAG), and single dummy gate (SDG), which in total are claimed to add another 30% transistor density improvement.

COAG means moving the contact from a position away from the fins to directly over the active part of the gate:


We can perhaps see the concept a bit more clearly in this (somewhat fuzzy) image of 14nm transistors:


We can see here that if we can somehow squeeze the gate contacts in between the source/drain contacts, then we don’t need the vertical space for them, and we can shrink the cell height; the vertical distance between the gates is reduced to the gate tip/tip spacing. However, this strikes me as quite a challenge, likely requiring at least self-aligned gate contacts, and it’s no wonder that Kaizad commented that “there are a number of technology attributes and innovations that we needed to introduce to allow the contact to be placed directly above the active transistor.” This extra complexity may mean that the cell architecture could have also changed, and the routing metal may not be at the minimum pitch; the minimum metal may start at the M3 level.

For the single dummy gate, he also said that Intel “introduced unique innovations to overcome the difficulties of single dummy gate,” to ensure that the performance of centre transistors and the edge transistors are closely matched.


The dummy gates are shown in the plan-view image above, but what can’t be seen is that he dummy gates usually overlap the end of the fin, unlike the left-hand schematic above. Here’s a shot of 22nm PMOS gates on a fin:


This clearly adds to the width of the cell, but it has the advantage of matching the performance of all the transistors on the fin. If we have a single dummy gate on the STI between the fins, as in the Samsung 14nm and earlier 20nm devices, then the source/drain cavity etch and the contacts are on or near the ends of the fin. They are then subject to overlay errors, increasing variation in both the contact resistance and the source/drain epi growth.

The simplest structure to get rid of this problem would be to do without the STI between fins, making the dummy gate some sort of isolation structure, but presumably that would mean having contacts to those gates to keep them tied to the correct potential – adding more complexity to the structure and design rules. We’ll see what those “unique innovations” are when the part comes out!

In total these changes make for a shrink beyond the usual 50% to 37% of the 14nm technology:


Intel claims that this hyper-shrink actually brings them back on to a two-year cadence from the 45nm node, assuming high-volume production as of the second half of this year.


The SRAM cells are scaled by a factor of ~0.6, so that the low-voltage 1:2:1 (fins in Pull-Up:Pass-Gate:Pull-Down transistors) cell goes from ~0.059 µm2 to ~0.037 µm2, and the high-density 1:1:1 cell shrinks from ~0.050 µm2 to ~0.031 µm2. (The TSMC and GF/IBM/Samsung 7-nm cells announced at IEDM, presumably 1:1:1 cells, were 0.027 µm2.)

If we look at the transistor image, there are features in common with the 14-nm device. Comparing at the two cross-sections, it appears that the solid-source punch-stop diffusions introduced at 14-nm are present, since we can see the seal layer(s).



Looking at the gate stacks, we do not seem to have any significant change, so we now have the fifth generation of Intel’s HKMG technology, and of course it’s their third-generation finFET.

Things are not getting any easier, not the least getting the gate and contact materials into ever smaller spaces. With a smaller fin pitch the implant angle needed for doping is also shrinking; I measured it as less than 30o, compared with the 52o and 41o of the 22- and 14nm processes, but I am told that if the implant has a twist (i.e. angled with respect to the fin orientation), then it is till feasible to get implants into the right location.

Taller fins with higher aspect ratios will have their own mechanical challenges, implying tighter stress control to avoid fin bending and distortion, which was quite noticeable in some samples of the 14nm product.

We could go on detailing more problems, but suffice it to say that I don’t have much sympathy with some of the media criticism that I see of the slow-down in process generations. It wasn’t easy in the days of Grove, Kilby, and Moore, given the technologies of the time, and now that we are counting atoms it certainly isn’t any easier – don’t forget that a 7nm fin is actually less than 25 atoms wide!

Intel’s 10nm Enigma

By Dick James

I’ve been looking back at the talk given by Mark Bohr and Zane Ball (Building Winning Products with Intel® Advanced Technologies and Custom Foundry Platforms) at the Intel Developer Forum (IDF) in August last year, and I’m a bit puzzled.

Mark Bohr presenting at the 2016 IDF in San Francisco (Source: Intel)

Mark Bohr presenting at the 2016 IDF in San Francisco (Source: Intel)

Mark announced the gate pitch as 54 nm, which I make as 0.77 x 70 nm (the 14-nm gate pitch):

Gate pitch

And he also said that their measure of scaling is gate pitch x cell height:

Cell size

and then he said that new design rules give even better scaling:

Cell size 2

“Our trend in reducing logic cell area has been about 0.46x per generation, a little bit faster than the typical Moore’s Law of 0.5x.

On our last two generations, 14 nm and now on 10 nm, we’re actually scaling our logic cell area a little bit faster than what that simple metric suggests; there are some other tricks that we’re doing on 10 nm that is providing even faster than normal logic cell area scaling, so although 0.46x was the long-term trend over the past four generations, it’s actually a bit faster on our 14 and now again on our 10-nm technology.”

If you look at the numbers in the revised graph, then we appear to have a scaling factor of ~0.37 per generation, which is indeed quite impressive!

The cell height can also be measured by the number of metal tracks that are needed for routing for the cell; in recent nodes we have gone from 12-track (12T), to 9T, to ~7.5T in the latest 14- and 16-nm processes. So we can also describe cell height as the number of metal pitches (MPP) in a cell.

That leads me to the enigma – if you take the 10-nm number from the above graph, ~11,000 nm2, and divide the 54-nm gate pitch into it to get the cell height, and then divide that by the minimum SADP (self-aligned double patterning) metal pitch of ~40 nm to get the number of tracks, then you get a five-track cell, which seems really ambitious for a one-generation shrink.

If you go the other way and plug in 54 nm and a six-track cell, then the MPP comes out at 34 nm, which presumably means SAQP (self-aligned quadruple patterning), which again sounds really ambitious.

The 5T cell is more in keeping with “design rule enhancements” but if that is the case, that also requires a reduction in the number of fins per transistor, which implies taller fins or other tweaks to maintain transistor performance; or SAQP for fin definition, to allow increased fin density. Given that the 14-nm fin pitch was ~42 nm, already close to the SADP limit, the latter may be a real possibility (a 76% linear shrink would be ~32 nm).

If they’ve done any of these, I guess it could account for the increased time between generations!

Mark also broke with the current convention of showing performance plots with the dreaded “arbitrary units”, later in the talk he showed the four transistor options available in their 10-nm process:

Transistor options

According to Mark, the four options will use the same 54nm gate pitch. NMOS drive currents are still higher than PMOS, which to me suggests two things – there is a seventh-generation strain mechanism at work for NMOS, and it seems unlikely that we have a different channel material such as SiGe in the PMOS devices.

In keeping with their foundry ambitions, there will be three evolutions of the 10-nm process, with the initial launch of 10, then 10+ and 10++, as well as a SoC version of the process with high-voltage and analog elements, and three interconnect stacks. In any case, these numbers do support the Intel claim that their process is a true shrink from 14 nm, not just an improved 14-nm process.

The increased shrink allows Intel to stay ahead of the cost curve, so that we still have improved PPAC (performance/power/area/cost) numbers.

Transistor cost

We will see if any more information comes from the quarterly call this week, or at the Investor Meeting next month, but in the meantime, we have our mystery – do we have a five-track cell, or am I missing something?

IEDM 2016 – Setting the Stage for 7/5 nm

By Dick James

At IEDM last month, there was much ado about the adjacent 7-nm late-news papers from TSMC and the GLOBALFOUNDRIES/IBM/Samsung group consortium from the Albany Nanotechnology Center, and with less ado, Samsung gave a 5-nm presentation later in the conference. Here we discuss all three talks, and try and make some comparisons.

TSMC 7 nm

In paper 2.6 [1], TSMC announced the “world’s first 7nm CMOS platform technology for mobile system-on-a-chip (SoC) applications, featuring FinFET transistors”. They claimed the world’s smallest-ever SRAM cell at 0.27 µm2, and 3x the gate density of the 16-nm (16 FF+) process, together with a 35 – 40% speed gain or over 65% power reduction. In addition, the process uses 193 nm immersion lithography, dual raised source/drain epi, a novel contact technique, and a 12-layer copper/low-k interconnect stack.

The fourth-generation fin profile and width are “carefully optimized” for the fifth-generation HKMG gate-last, dual gate oxide process, with an effective gate length (leff) centered around 16.5 nm. Sub-threshold swing has been pushed down to ~65mV/decade, and DIBL is ~40 mV/V.


Four Vt options are available in the TSMC 7-nm technology [1]

There are four device Vt options with a range of ~200 mV.

The contacted poly pitch (CPP) is not stated (Scotten Jones speculates that it is 54 nm, the same as Intel’s 10-nm process), enabled by a novel contact process, and we also have “novel strain engineering and new process knobs” which boost mobility and reduce parasitic resistance to give increased drive current (at least in arbitrary units).

The 1x metal pitch is 40 nm for M0 to M4, and M5 – M9 are 1.9x (76 nm). The paper states that “single patterning is adopted for metal layers with 2X minimum metal pitch and above” – which make me wonder if they’ve managed to push single patterning to the 76-nm pitch, or whether they are going with double patterning for the first nine levels.

An earlier SRAM paper was given in June at the VLSI meeting [2], as a sub-0.03 µm2 bitcell, aimed at a “beyond 10-nm node”, so likely the same SRAM. It also has an leff centered on ~16.5 nm, and claims similar performance figures. Some details of the inter-well spacing are also included [1]:


Which allows us to speculate about device sizings, at least in the SRAM cell itself. Typically, a 6-transistor (6T) SRAM unit cell is 2 x CPP high, so if we take the guesstimate of 54 nm for CPP, the 0.27 µm2 cell should have a height of 108 nm. Dividing that into 27,000 nm2, we get a cell width of 250 nm. The 16FF cell was 0.70 µm2 [3], 2.6 x the area of the 7-nm cell, confirming the claim of a 2.6 x array density increase in the paper.

I don’t have a plan-view image of the TSMC 16-nm cell, which I assume is a 1:1:1 PU:PG:PD cell (i.e. one fin for each of the pull-up/pass gate/pull-down transistors), but Intel kindly provided one of their 14-nm cell in a JSSC paper [4]:

TEM image of Intel 14-nm SRAM cell [4]

TEM image of Intel 14-nm SRAM cell [4]

The Intel 14-nm cell size is 140 x 360 nm, to give a cell size of ~0.050 µm2, considerably smaller than the 16FF cell; we can see that each transistor uses one fin, and there are four fins in the cell. In this case the fin pitch is ~80 nm, instead of the nominal 42 nm, but we have to allow space between the fins and the edge of the N-well that the PMOS pull-up transistors sit in. Theoretically the two pull-up transistor fins could use the minimum pitch, but Intel have chosen not to do that here.

Applying these considerations to TSMC’s cell, if we use the maximum fin-well edge spacing of 23 nm shown above, plus (say) 8 nm for the fin width, then we get a PU – PD/PG spacing of 2 x 23 = 46, + 8 = 54 nm; if we assume a SADP (self-aligned dual patterning) minimum fin pitch of 40 nm between the PU transistors, then we get a total of 148 nm for the center of fin 1 – fin 4, which leaves us 52 nm at each end for the PD/PG – PG contact spacing. If the PU/PU pitch is also 54 nm, that only leaves 45 nm at the end of the cell, which is pushing the limits for double-patterned contact spacing. Which gives us something like this – just guessing!

Speculative layout of TSMC 7-nm SRAM bitcell

Speculative layout of TSMC 7-nm SRAM bitcell


The other 7-nm paper [5] from Albany was clearly a research paper, but illuminating in that it shows other possible directions, not the least being the use of EUV lithography, SiGe channels for PMOS, and stress applied to the channels using a strain-relaxed buffer (SRB) substrate.

The application of a SRB substrate to generate channel stress takes me back 15 – 20 years, to the late 90’s and the turn of the millennium, when a lot of work was published on the topic by Stanford, MIT, and IBM. If a silicon epitaxial layer is grown on a SiGe substrate, then the lattice mismatch creates biaxial tensile stress in the layer, and the greater the Ge content, the greater the stress. The earliest reports I can find date back to 1992/4/5 [6, 7, 8,], but the effect is nicely summarized in this plot from IEDM 2003 [9]:

Mobility enhancement vs. strain and Ge % in strained Si/relaxed SiGe MOSFETs [9].

Mobility enhancement vs. strain and Ge % in strained Si/relaxed SiGe MOSFETs [9].

As we can see, low Ge concentration gives a large increase in electron mobility, but a high Ge content is required to enhance hole mobility.

In this paper, we have the following structure:

Schematic (center) of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with dark-field TEM images of (a) the tensile-strained silicon fin and (b) the compressively-strained SiGe fin on a common SRB [5]

Schematic (center) of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with dark-field TEM images of (a) the tensile-strained silicon fin and (b) the compressively-strained SiGe fin on a common SRB [5]

This gets around the weak PMOS improvement in silicon from the SRB by using 25% Ge in the SRB and growing a 50% Ge fin; if silicon is tensile-stressed, then a layer with more Ge than the SRB will be compressively stressed; and as we know, compressive stress is a big lever for PMOS performance. The authors claim that this combination gives ~1.6 GPa enhancement stress in both NMOS and PMOS devices. SiGe also has a higher hole mobility, compounding the performance gain.

As I remember it, SRB stress never made it into production, likely for two reasons – it was difficult to get rid of the dislocations formed in the SRB, and they propagated through into the sSi; and more production-friendly sources of uniaxial stress could be supplied by tensile nitride and embedded SiGe source/drains.

Now that we are in the finFET era, and twenty years on, we have the advantage of better process control, (so likely lower defect density), and any defects that are formed cannot propagate up the fin because of its narrow aspect ratio. In addition, fins formed in the correct orientation on a SRB use only one axis of the biaxial stress, giving the uniaxial stress that we are used to; so maybe this technique can become the stress mechanism for the 7/5 nm nodes.

Biaxial stressed layer becomes uniaxially-stressed finFET [10]

Biaxial stressed layer becomes uniaxially-stressed finFET [10]

If I read the paper correctly, the SSRW is grown epitaxially as part of the SRB (“An epi based SSRW technique is utilized to improve sub-fin isolation” [5]), before the strained silicon (sSi) epi is grown; the sSi is then etched back and the 50% SiGe layer is formed and (presumably) polished back to separate the sSi and SiGe regions before fin etch [11].

Self-aligned quadruple patterning (SAQP) was used for the fins (my notes say the fin pitch was 27 nm), and SADP for the gates with a CPP of 44/48 nm. EUV was reserved for the middle-of-line (MOL) and lower metal levels, with a minimum metal pitch of 36 nm.

(a)Schematic flow for SAQP fin patterning (b) top-down SEM of fins before cut/block mask [5] Top-down SEMs of (a) BEOL M1 lines with 36nm pitch, and typical MOL trenches with (c) 45°, (d) 90° cross-couples, (24nm trench width), all patterned by EUV lithography [5]

(a) Schematic flow for SAQP fin patterning (b) top-down SEM of fins before cut/block mask [5]
Top-down SEMs of (a) BEOL M1 lines with 36nm pitch, and typical MOL trenches with (c) 45°, (d) 90° cross-couples, (24nm trench width), all patterned by EUV lithography [5]

The EUV process was presented at last year’s IITC/AMC conference [12]; a metal hard mask was used to pattern lines and self-aligned vias into an ultra-low-k dielectric (k~2.45), and a TaN/Ru liner stack was filled conventionally with a CVD Cu seed and plating. A Co cap and SiCN/SiNO layer sealed the interconnect, giving acceptable TDDB (time-dependent dielectric breakdown) and electro-migration results.

M1 – M3 stack in test die used in [12]

M1 – M3 stack in test die used in [12]

Cross section and elemental mapping of M1 Cu lines with TaN/Ru barrier and selective Co cap [12]

Cross section and elemental mapping of M1 Cu lines with TaN/Ru barrier and selective Co cap [12]

Contacts are self-aligned, with the use of a M0 level, CA/CB contacts, and a sub-contact (TS) for source/drains. The CA/CB/M0 metallization is dual-damascene cobalt, lowering line resistance, while the TS sub-contacts appear to be tungsten. Before the TS contacts are filled, Si:P and SiGe:B epi is grown in the contact trenches, and then implanted and annealed, to give improved contact resistance.

Middle-of-line architecture (left), and dark-field TEM of M0/CA/TS stack [5]

Middle-of-line architecture (left), and dark-field TEM of M0/CA/TS stack [5]

The gate profile was modified by etching back the high-k layer before depositing the work-function metal (WFM), which helps isolate the high-k from the self-aligned contact process reactants, and improves control of the WFM recess before metal fill and dielectric deposition.

Cross-section TEM of <17 nm gate showing etch-backs of high-k and WFM [5]

As you can see from the above, there was quite a bit of detail in this presentation, which can be summarized in the process sequence shown [5]:

IBM flow

Strangely, despite the tighter pitches when compared with the TSMC SRAM bitcell, the size is the same, ~0.27 µm2, though we don’t know if this is a 1:1:1 cell or not – if (say) a 1:2:1 configuration is used, that would add at least ~0.052 µm2 to the cell size, assuming the 48 nm CPP. (The paper does not state bitcell size, but in the Q & A’s, we were told that it was 50% of the 10-nm bitcell, which was quoted at ~0.53 µm2.) The Q & A’s also mentioned that there were three flavours of Vt, and high-Vt I/O transistors were not studied, reinforcing the research nature of the paper.

Samsung 5 nm

Later in the conference (paper 28.1), Samsung presented a “co-integration scheme for 5nm logic” [13] which clearly drew on the 7-nm work from Albany detailed above, and illuminating some more development problems that that must have been seen in Albany.

A SRB substrate is used with a SiGe fin for PMOS, and a common interlayer, high-k, and work-function materials. The SiGe fin, combined with e-SiGe source/drains, gives an estimated 1 GPa compressive stress, and the SRB applies similar tensile stress to the NMOS channel. As with the Albany process, the Ge concentration increases as we go from SRB to fin to e-SiGe source/drains.

Schematic of Samsung 5-nm CMOS design concept [13]

Schematic of Samsung 5-nm CMOS design concept [13]

Defect density from the SRB was definitely a concern, and was reduced to 5e4/cm2, and then demonstrated by SRAM that leakage levels are comparable with those of a reference SRAM structure on bulk Si. My notes say that a thicker SRB was used, but no actual thicknesses were mentioned.

SiGe SRB TDD evolution with lowest TDD of 5e4/cm2 (left), 128M finFET SRAM with TDD 2.3e5 /cm2 (right) shows comparable yield and leakage with reference SRAM [13]

SiGe SRB TDD evolution with lowest TDD of 5e4/cm2 (left), 128M finFET SRAM with TDD 2.3e5 /cm2 (right) shows comparable yield and leakage with reference SRAM [13]

Another problem was migration of the Ge to the surface of the SiGe fin (shifting Vt and degrading interface state density), because of later thermal processing, as shown in this LEAP (laser enhanced atom probe) image:

Ge (blue) in SiGe fin, showing higher Ge content at the surface [13]

Ge (blue) in SiGe fin, showing higher Ge content at the surface [13]

Careful optimization of the thermal sequencing reduced this to about a 4% variation. Since the STI penetrates into the buffer layer, and we have a SiGe fin, a new STI formation process had to be developed, to reduce any side-effects from oxidation.

More details were given of the stress development; the presenter showed that the strain was uniaxially transferred to the fin, and also that the source/drain recess etch relaxed the channel stress – in the PMOS device the e-SiGe epi restored the stress, but for NMOS a non-recessed S/D was used.

Geographic phase analysis (GPA) shows uniaxial (along fin) tensile strain induced by SRB, and strain fully relaxed perpendicular to fin (a). Strain profile along fin depth shows uniaxial strain along fin but almost fully relaxed strain across fin (b) [13]

Geographic phase analysis (GPA) shows uniaxial (along fin) tensile strain induced by SRB, and strain fully relaxed perpendicular to fin (a). Strain profile along fin depth shows uniaxial strain along fin but almost fully relaxed strain across fin (b) [13]

When it comes to the electrical results, long- and short-channel plots were shown, but with no numbers for either device size or measurements, so we have to trust that they actually fit 5-nm node dimensions, or at least are for smaller pitches than the 7-nm papers detailed. However, as an integration scheme it is interesting, as gives us some clues as to what we might see from Samsung and GLOBALFOUNDRIES as we go from 10 – 7 – 5 nm.

Given the lack of detail in TSMC’s presentation, we don’t know what their novel contact and strain engineering and process knobs are – could they be contact epi and SRB strain? I guess we’ll see in a couple of years or so.

N/PFET channel average stress evolution during processing – the relative strain clearly shows relaxation from the S/D recess process. After recess optimization, relaxation was minimized for the NFET (but non-recessed process chosen), and recovered with eSiGe process [13]

N/PFET channel average stress evolution during processing – the relative strain clearly shows relaxation from the S/D recess process. After recess optimization, relaxation was minimized for the NFET (but non-recessed process chosen), and recovered with eSiGe process [13]


  • S-Y Wu, et al., “A 7 nm CMOS Platform Technology Featuring 4th Generation FinFET Transistors with a 0.027 um2 High Density 6-T SRAM cell for Mobile SoC Applications”, IEDM 2016, pp. 43 – 46
  • S-Y Wu, et al., “Demonstration of a sub-0.03 um2 High Density 6-T SRAM with Scaled Bulk FinFETs for Mobile SOC Applications Beyond 10nm Node”, VLSI 2016, pp 92 – 93
  • S-Y Wu, et al., “An Enhanced 16nm CMOS Technology Featuring 2nd Generation FinFET Transistors and Advanced Cu/low-k Interconnect for Low Power and High Performance Applications”, IEDM 2014, pp. 48 – 51
  • Karl, et al., “A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry”, IEEE JSSC, VOL. 51, NO. 1, (Jan 2016), pp. 222 – 228
  • Xie et al., “A 7nm FinFET Technology Featuring EUV Patterning and Dual Strained High Mobility Channels”, IEDM2016, pp. 47 – 50
  • Welser et al., “NMOS and PMOS Transistors Fabricated in Strained Silicon-Relaxed Silicon-Germanium Structures”, IEDM 1992, pp. 1000 – 1002
  • Welser et al., “Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs”, IEDM 1994, pp. 373 – 376
  • Rim, et al., “Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs” IEDM 1995, pp. 517 – 520
  • Rim, et al., “Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs”, IEDM 2003
  • IEDM 2016 Short Course, “Technology Options at the 5 Nanometer Node”, session 3, N. Collaert, “Novel channel materials for high-performance and low-power CMOS”, sl. 17
  • Guo et al., “FINFET Technology Featuring High Mobility SiGe Channel for 10nm and Beyond”, VLSI 2016, pp. 14 – 15
  • Standaert, et. al., “BEOL Process Integration for the 7 nm Technology Node”, IITC/AMC, 2016, pp. 2 – 4
  • D, Bae et al., “A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond”, IEDM 2016, pp. 683 – 686

IEDM 2016 Next Week! (Part 2)

By Dick James, Senior Technology Analyst, Chipworks

Read Part 1 here.

Now for the second part of the preview, starting with the Tuesday afternoon sessions:

Session 17: Process and Manufacturing Technology — Silicon Based Advanced CMOS

Here we look ahead a little, considering how silicon will evolve rather than using other higher-mobility materials. First up is a joint IBM/GF report of air spacers in 10nm finFET structures (17.1), between the gate and the contacts, to reduce the parasitic capacitance.

Schematic of partial air spacers (left), and TEM cross-section of finFET gates, showing spacers between gates and contacts (17.1)

Schematic of partial air spacers (left), and TEM cross-section of finFET gates, showing spacers between gates and contacts (17.1)

IBM/GF also study (17.2) the use of laser-induced liquid- or solid-phase epitaxy in contact trenches, to form semi-metallic, semiconductor-dopant (Si:P and Ge: group III metals) metastable alloys to reduce contact resistance.

17.3 also considers contact resistance, this time looking at Ni(Pt) silicide on fin-on-insulator (FOI) finFETs. IBM/GF are up again in 17.4, discussing low Ge-content SiGe finFETs; imec and Applied Materials are collaborating in the usage of high-temperature ion implantation in bulk finFET technology (17.5); next we look at vertically-stacked horizontal nanowires with replacement metal gates (RMG), inner spacers, and SiGe source/drain stress for p-FETs (17.6); and finally we have an FD-SOI paper, discussing a dual-isolation process (STI and local oxidation) to maximize both SiGe-channel stress and back-biasing performance(17.7). 

Session 18: Sensors, MEMS, and BioMEMS Enhanced Sensing, Heterogeneous Integration and Wearables

We start this session with a report (18.1) on using pre-bias to improve the sensitivity of a silicon FET gas detector which has ZnO as a sensing layer. Then Fujitsu describes a graphene-based gas sensor capable of detecting 7 ppb of nitric oxide (18.2), and in 18.3 laser-patterned graphene is used for strain sensing.

Graphene shows up again as a transparent epidermal sensor in 18.4, measuring skin temperature, hydration and electrophysiological signals (ECG, EEG, EMG). Prof. Shuji Tanaka of Tohoku University gives an invited talk on “Heterogeneously-Integrated Microdevices” in 18.5, then flexible (i.e. thin) bulk silicon is used for the system-level monolithic integration of multiple sensor types using CMOS processing, including a wearable version (18.6).

The session finishes (18.7) with an invited review by Raji Baskaran of Intel, on “Sensors and Haptics Technologies for User Interface Design in Wearables”. 

Session 19: Nano Device Technology — Tunnel and Nanowire FETs

The first paper combines both themes of the session – we have a vertical nanowire InAs/GaAsSb/GaSb tunnel FET (19.1) with a record high on-current of 10.6μA/μm.

Schematic of InAs/GaAsSb/GaSb TFET (left), and a colorized SEM image of a nanowire with W gate metal applied (19.1)

Schematic of InAs/GaAsSb/GaSb TFET (left), and a colorized SEM image of a nanowire with W gate metal applied (19.1)

19.2 is an invited review of a “Two-dimensional Heterojunction Interlayer Tunnel FET (Thin-TFET): From Theory to Applications” by Mingda Li from Cornell. The ThinFET was formed from WSe2/SnSe2 stacked heterostructures, which intrinsically has a smaller gate-drain capacitance due to its vertical stack.

Next we have the first hybrid Phase-Change-Tunnel FET (PC-TFET) device (19.3). Experimental digital and analog benchmarking of the new device was performed, and it was compared with Tunnel FETs and CMOS; it was also included into a neuromorphic computing cell, taking advantage of the phase-change mechanism.

Isoelectronic trap technology (IET) is used to improve the performance of silicon-based TFETs in 19.4, and Shinichi Takagi of U. Tokyo gives an invited review (19.5) of “Tunneling MOSFET Technologies using III-V/Ge Materials”.

The next paper details InGaAs/GaAs and Ge/GeSn p-TFETs on GaAsSb and GeSn substrates (19.6), and the last paper harks back to nanowires, this time vertical silicon GAA-NW transistors with a dual work-function, high-k last RMG process (19.7).

Session 20: Power Devices — Focus Session: System-level Impact of Power Devices

This session focuses on the use of GaN and SiC power devices and how they have expanded the spectrum of applications to very high voltages, temperatures and power levels, compared to existing silicon-based devices.

It comprises a sequence of invited talks:

  • Wide Bandgap (WBG) Power Devices and Their Impacts On Power Delivery Systems,” by Alex Huang, North Carolina State University
  • Si, SiC and GaN Power Devices: An Unbiased View on Key Performance Indicators,” by G. Deboy et al, Infineon/ETH-Zurich
  • System-Level Impact of GaN Power Devices in Server Architectures,” by A. Lidow et al, Efficient Power Conversion Corp.
  • GaN-based Semiconductor Devices for Future Power Switching Systems,” by H. Ishida et at, Panasonic
  • Application Reliability Validation of GaN Power Devices,” by S. Bahl et al, Texas Instruments
  • Horizon Beyond Ideal Power Devices,” by H. Ohashi, NPERC-J (Japan’s New-Generation Power Electronics & System Research Consortium)

 Session 21: Characterization, Reliability and Yield — Reliability and Characterization of Memory Devices, Contacts and Interfaces

This session starts with a reliability study of a 128 Mb GaSbGe PCM device (21.1), followed by an examination of the effect of filament shape on Cu/Al2O3 CBRAMs (21.2).

21.3 investigates the microsecond transient thermal behavior of HfOx-based RRAMs, and 21.4 identifies the switching/failure mechanisms in non-filamentary RRAM.

Back in September GLOBALFOUNDRIES and Everspin announced production of Everspin’s 256 Mb DDR3 perpendicular magnetic tunnel junction (pMTJ) product, and availability of the embedded version of the technology on GF’s 22FDX platform. Jon Slaughter of Everspin is giving an invited talk (21.5) “Technology for Reliable Spin-Torque MRAM Products”, which will include a review of the performance of the 256 Mb, DDR3 ST-MRAM chip.

In 21.6 we have an endurance study of perpendicular spin-transfer torque (p-STT) memory, and 21.7 describes Schottky contacts between silicon and graphene, to finish the session. 

Session 22: Optoelectronics, Displays, and Imagers — Optoelectronic Integration

We start with GeSn thin-film transistors (TFTs) formed on a quartz substrate, which have high carrier mobility and luminescence (22.1). The second paper utilizes the optical properties of SOI wafers to couple an InGaAsP laser to a pair of distributed Bragg reflectors (DBRs) and a grating coupler diffracting the light to an optical fiber (22.2).

Schematic of a heterogeneous hybrid III-V/Si DBR laser cavity with the gain zone, two DBRs and a grating coupler at one side diffracting the light to an optical fiber (22.2)

Schematic of a heterogeneous hybrid III-V/Si DBR laser cavity with the gain zone, two DBRs and a grating coupler at one side diffracting the light to an optical fiber (22.2)

22.3 is an invited presentation by Dan Buca of Forschungszentrum Julich, “GeSn Lasers for CMOS Integration”, followed by a description of a high-gain optical amplifier, monolithically integrated with an InGaN-based laser diode (22.4).

A germanium-on-silicon Zener emitter is detailed in 22.5, and NXP and A*STAR come up with a surprising method of optically sensing the states of flash memory in the last paper (22.6); they demonstrate it with the on-chip integration of an optical micro-ring resonator and a memory array, and claim 1200× sensing speed improvement.

That is numerically the last paper of the afternoon, if not chronologically – the sessions with seven papers finish at ~5.15 pm.

In the evening at 8 pm we have the panel sessions in the Continental Ballrooms:

  • How Will the Semiconductor Industry Change to Enable 50 Billion Connected Devices? Moderator: Prof. Aaron Thean, University of Singapore
  • Challenges and Opportunities for Neuromorphic and Machine Learning, Moderator: Marc Duranton, Sr. Member of the Embedded Computing Lab, CEA

But, if you have the stamina after a day-full of technology, Applied Materials, Coventor and Synopsys are holding seminar/receptions between 5 and 8 pm. The Applied Materials event is at the Parc 55 hotel just around the corner from the Hilton, on “Rethinking Scaling: New Paradigms, New Approaches”, and Coventor is looking at the back-end “BEOL Barricades: Navigating Future Semiconductor Yield, Reliability and Cost Challenges”, in the Union Square rooms on the 4th floor of the Hilton. The Synopsys reception is around the corner at the Serrano Hotel from 6 – 8 pm.


Session 25: Process and Manufacturing Technology — Beyond Conventional CMOS

25.1 looks at the contribution to source/drain resistance made by interfaces such as the p-SiGe/p-Si interface, and also studies the n-Si/n-Ge, n-InAs/n-Si and n-InAs/n-Ge interfaces.

The second paper examines the effects of doping HfO2 with different ions, both cations and anions, in order to influence and predict ferroelectric properties; and demonstrates an N-doped dielectric layer in a ferroelectric FET (25.2).

Next up is a description of an AgTe/TiO2-based threshold switching (TS) device that can be integrated with a conventional BEOL (25.3). When switched on, a conductive silver filament forms, and when switched off, the filament dissolves and conduction stops. A TiN liner is put between the AgTe and the TiO2 to prevent silver diffusing into the TiO2 during BEOL processing; a steep subthreshold slope of less than 5 mV/decade is claimed.

Schematic and TEM image of the integrated TS transistor (25.3)

Schematic and TEM image of the integrated TS transistor (25.3)

We live up to the theme of “Beyond Conventional CMOS” in 25.4; here we have InGaAs-on-insulator MOSFETs, fabricated by direct wafer bonding (DWB)and epitaxial lift-off techniques, aimed at monolithic 3D integration; and in addition, the InP donor wafer can be re-used.

We stay with wafer bonding in 25.5, but in the photonics realm; an InGaAsP/Si hybrid MOS-based phase shifter formed on a Si photonics platform by using DWB is described.

The last talk of the session is an invited one, by Janos Veres of Xerox PARC; “Additive Manufacturing for Electronics “Beyond Moore””. The ability of additive manufacturing and 3D to change the paradigm of electronics production will be discussed. 

Session 26: Sensors, MEMS, and BioMEMS — N/MEMS for Physical, Chemical, and Bio-sensing

A solid-state pH and chloride sensor is formed from iridium oxide (IrOx) and silver chloride (AgCl) electrodes fabricated on a Si substrate in 26.1, with a microfluidic reference electrode incorporated. 26.2 describes the use of a spin-transfer torque operated magnetic tunnel junction (STT-MTJ) to make a thermal sensor more than 0 times faster than a traditional CMOS thermal sensor.

Next Chae Ahn from Stanford gives an invited talk (26.3) on the challenges of encapsulating MEMS timing reference devices, with particular reference to those produced by SiTime Inc; and the influence of the thickness of a tribo-dielectric layer on the performance of a tribo-electric energy harvester is described in 26.4.

In 26.5 we look at a brain probe which uses neuron-sized LEDs to stimulate the neuronal proteins with light instead of electrically. Micro-LEDs and electrodes are integrated on thin silicon probes formed by micro-machining to give a four-probe opto-electrode which can be inserted into the target area of the brain.

The four shanks of an optoelectrode with its tips are shown (26.5), with the LEDs illuminating. The inset (left) shows a SEM view of a tip.

The four shanks of an optoelectrode with its tips are shown (26.5), with the LEDs illuminating. The inset (left) shows a SEM view of a tip.

The effect of Lamb waves (sound waves confined to a thin layer) on the two-dimensional electron gas (2DEG) in an AlGaN/GaN heterostructure are studied in 26.6, generating an acousto-electrical effect that results in DC current flow between contacts on the acoustic layer.

In 26.7 a micro-oven is used to control a CMOS-MEMS oscillator, with a built-in temperature detector for self-test and resonator temperature monitoring; and in the last talk (26.8), self-assembled perfluorodecyl-triethoxysilane (PFDTES) is used as an anti-stiction coating on the contacting parts of a nano-electro-mechanical relay. 

Session 27: Memory Technology — MRAM

Hynix and Toshiba kick off the session with a joint paper (27.1) on a 4-Gb perpendicular SST-MRAM (spin-transfer-torque magnetic random access memory) with a 9F2 cell area. The vertical stack and a plan-view SEM image of the MTJ array are shown below, clearly using some of the techniques used in DRAMs, such as buried wordlines.


Just eyeballing the scale bar on the SEM image, it looks like the MTJ cell diameter is ~50 nm, which compares with ~60 nm in a 20-nm DRAM.

This is followed by a Samsung exposition (27.2) of an 8-Mb STT-MRAM embedded into the BEOL of their 28-nm logic process, again using a perpendicular MTJ (pMTJ). Third up (27.3) is a study of data extraction methods for perpendicular SST-MRAM, to evaluate retention as cell size decreases from 250 nm to 50 nm in diameter.

Qualcomm and Applied Materials shrink the pMTJ cell size even further in 27.4, down to 25 nm, studying the properties in 1-Gb arrays. 27.5 is an examination of a voltage-torque MTJ MRAM; and in the last paper (27.6) Toshiba describes another voltage-controlled MTJ, with volts used to select bits, and spin-torque to write.

Session 28: Circuit and Device Interaction — Technology Elements for 5nm Logic Platform and Advanced Automotive/IoT Applications

Samsung manages to integrate strained Si-channel NMOS and SiGe-channel PMOS finFETs in 28.1, using a buried strain-relaxed SiGe buffer layer to create tensile-strained NMOS and compressively-strained PMOS devices. The gate stack uses a common interfacial layer, high-k, and metal gate, without dual-work-function metals, and a simplified multi-Vt module.

Imec (28.2) discusses a 5-track standard cell (Intel’s 14-nm uses 7.5-T cells) optimized for finFETs and horizontal nanowires, using single-fin design and air-gap spacers. Stanford and ARM analyse a 32-bit processor core designed with 5-nm design rules (28.3), looking at transistor and interconnect technologies.

In the next paper (28.4), a new method of near-threshold-voltage (NTV) design optimization for FinFETs is developed, and demonstrated based on silicon data using Vdds of 199 and 145 mV.

In 28.5 Xilinx looks at high-speed analog circuits, and presents an optimized MOS varactor design and finFET model; both were validated in a 16-nm finFET process in a high-speed transceiver design.

The final talk is an invited review of “Embedded Flash Technology for Automotive Applications”, by T (Tadashi?) Yamauchi from Renesas, including the integration of their split-gate MONOS eFlash into a 28-nm HKMG process.

Session 29: Compound Semiconductor and High Speed Devices — Ultra-High Speed Electronics

This session is a special focus session, again consisting of invited papers on TeraHertz technology and applications:

  • 29.1InP HEMT Integrated Circuits Operating Above 1,000 GHz,” by W.R. Deal et al, Northrop Grumman
  • 29.2A 130 nm InP HBT Integrated Circuit Technology for THz Electronics,” by M. Urteaga et al, Teledyne Scientific Co./SungKyunKwan University
  • 29.3Resonant-Tunneling-Diode Terahertz Oscillators and Applications,” by M. Asada and S. Suzuki, Tokyo Institute of Technology
  • 29.4Physics of Ultrahigh Speed Electronic Devices,” by M. Shur, Rensselaer Polytechnic Institute
  • 29.5InP/GaAsSb DHBTs for THz Applications and Improved Extraction of their Cutoff Frequencies,” by C.R. Bolognesi et al, ETH-Zurich
  • 29.6On-Chip Terahertz Electronics: From Device-Electromagnetic Integration to Energy-Efficient, Large-Scale Microsystems,” by R. Han et al, MIT/Office of Naval Research/Cornell University/University of Michigan/STMicroelectronics/University of Texas at Dallas/Naval Research Lab
  • 29.7Active Terahertz Metasurface Devices,” by H.T. Chen, Los Alamos National Laboratory
  • 29.8Devices and Circuits in CMOS for THz Applications,” by Z. Ahmad et al, University of Texas at Dallas/NXP Semiconductors/MIT/SeoulTech/Texas Instruments/MediaTek/IDT/Wright State University /UT Southwestern Medical Center/Ohio State University/ UConn Health

Session 30: Modeling and Simulation — Steep Slope Devices and Nanowires

The first paper is a TSMC study of III-V ‘broken gap’ nanowire TFETs (30.1), claiming a 58x gain increase over a Si MOSFET; followed by simulations of TFETs at Vdds of 0.08 – 0.18V (30.2).

Then we have more TFET analyses, this time of the band-tails in 2D devices (30.3), and resonant tunnelling characteristics of inter-layer TFETs with multiple tunnel barrier layers (30.4).

30.5 demonstrates models of ferroelectric negative capacitance finFETS; 30.6 examines the performance of ultra-thin body III-V finFETS and nanowires with 15 and 10.4 nm gate lengths, confirming that GAA-NWs is the only viable architecture below 10.4 nm; and the final paper is a look at vertically-stacked NW-FETs for sub-10 nm nodes (30.7).

Session 31: Characterization, Reliability and Yield — Reliability Modeling and Characterization of Dielectrics and Interfaces

In 31.1 IBM Research studies the electronic defect states at the interface between a compress SiGe channel and the interlayer dielectric of p-FETs. Samsung also looks at SiGe p-FETs (31.2), assessing the effects of acceptor traps on negative-bias temperature instability (NBTI), and coming to the conclusion that they can lower the oxide electric field and improve the NBTI performance.

Next up is a characterization of Ge p- and n-MOSFETs with an Al2O3/GeOx/Ge gate stack (31.3), followed by the presentation of a new model for looking at NBTI and PBTI (31.4). SMIC and Peking U. review the gate dielectric reliability of TFETs in 31.5, and IBM Research is back (31.6) with a model for gate oxide progressive breakdown in n- and p-FETs

We switch topics to the back-end in an investigation by TSMC (31.7) of AC TDDB (time-dependent dielectric breakdown) in BEOL extreme low-k (ELK) dielectric in (presumably) their 10nm technology.

The final talk is a presentation on the use of self-healing in gate electrodes in silicon GAA-NW FETs (31.8), aiming at electronics for deep space missions.

Session 32: Optoelectronics, Displays, and Imagers — Thin Film Transistors for Imaging and Displays

We start the session with a demonstration of an active artificial iris (32.1) built on a contact lens, and formed solely of thin-film components. It comprises an organic thin-film photovoltaic mini-module as a power supply/integrated illumination sensor; a flexible thin-film a-IGZO circuit as a driver chip; and a liquid crystal display which acts as the iris. Such a device can help with iris deficiencies that can bring great discomfort and extreme photosensitivity for sufferers.

A “smart” contact lens system, comprising an integrated display, energy harvesting components, communication antenna, sensors and more (32.1).

A “smart” contact lens system, comprising an integrated display, energy harvesting components, communication antenna, sensors and more (32.1).

In 32.2 an elevated-metal metal-oxide (EMMO) thin-film transistor (TFT) is proposed that can also act as an etch-stop layer in a high-resolution display stack. 32.3 is a proof-of-concept study, forming polysilicon TFTs on paper, sintering a liquid silicon solution at 100 oC or below.

Next up in 32.4 is Adrien Pierre of UCal. Berkeley, giving an invited talk on “High-detectivity Printed Organic Photodiodes for Large Area Flexible Imagers”, followed by a report on dual-gate a-Si:H fin-TFTs (32.5), which have photosensitivity when operated sub-threshold.

While not conventional TFTs, FD-SOI n- and p-FETs can be light-sensitized by putting a diode in the substrate below the transistors (32.6). The photo-generated carriers in the diode can create a back-bias, shifting the threshold voltage of the transistors. This capability was used to demonstrate a light-controlled SRAM.

Then – lunch! IEDM and IEEE Women in Engineering have organised their annual Entrepreneurs Luncheon, which will feature Vamsee Pamula, co-founder of Baebies, Inc. a company developing digital microfluidics technology for newborn screening and pediatric testing.

In parallel, ASM is hosting their usual Wednesday lunchtime seminar at the Nikko Hotel across the street from the Hilton, this year the topic is “Covering 3D Devices”.

And be back in the Hilton for the afternoon sessions, beginning at 1.30 pm.

Session 33: Process and Manufacturing Technology — Ge Channel Devices

We start with CVD-grown Ge/GeSn/Ge quantum well (QW) p-MOSFETs with transverse uniaxial tensile strain, reportedly giving ~7% mobility enhancement leading to a record high mobility (33.1). The CVD process enables a low thermal budget of 400oC.

The second presentation is invited – Seiichi Miyazaki of Nagoya U. is speaking on “Processing and Characterization of Si/Ge Quantum Dots” (33.2), detailing their research on silicon quantum dots with a germanium core.

Then we explore (33.3) high performance Ge CMOS with quantum well-structured channels a single MoS2 capping layer. The MoS2 confines the carriers within the Ge layer, reducing scattering at the dielectric interface and improving performance.

33.4 demonstrates a silicon-passivated Ge NMOS gate stack, with LaSiO doping at the HfO2/SiO2 interface, that is compatible with 3D structures and has improved PBTI reliability and electron mobility.

The fifth paper of the session discusses Ge finFETs fabricated by neutral beam etching and oxidation, which gives low-defect, smooth surfaces and improved performance compared with conventional reactive ion etching (33.5).

Lastly, there is a description of junction-less GAA n-FETs that use selective laser annealing on epi-Ge on SOI (33.6).

Session 34: Nano Device Technology — Devices Based on Quantum and Resistive Switching Phenomena

Now we get into the realm of quantum dots and qubits; in 34.1 we hear a study of coupled phosphorus donors with MOS quantum dots, giving two-axis control of a two-electron spin logical qubit. 34.2 deals with silicon-based charge qubits with coherence times and operating temperatures two orders of magnitude larger than other reported semiconductor systems.

Nanomagnet networks are explored in 34.3, which are apparently ideal for Ising computing (a method of solving combinatorial optimization problems). VO2 is used for a two-terminal hysteretic voltage switch in 34.4, since it can be voltage-induced to change from metal to insulator and back; in this case it is applied to analogue signal processing.

The same phenomenon is utilised to make low-voltage artificial neurons, that can be voltage-scaled down to 0.3 V (34.5), and threshold switches made with Ag/HfO2 are used as selector switches for PCM-based cross-point memory in 34.6.

Atom-switches (atomic-scale metal-filament switches) are integrated with silicon MOSFETs (34.7) to give ‘atom-switch FETS’ with extremely low leakage current, low operating bias, and sub-threshold swing of less than 5 mV/decade.

The last paper of the day (34.8) presents two dimensional (2D) RRAM devices using multilayer hexagonal boron nitride (h-BN) as the active switching layer; the cyclical release and diffusion of B ions are the key physical mechanisms responsible for switching, forming a boron (B)-deficient conductive filament.

Session 35: Circuit Device Interaction — 3D Systems, Enabling Technologies and Characterizations

This session starts with an invited talk by Fabien Clermidy from CEA-LETI (35.1), reviewing “New Perspectives for Multicore Architectures using Advanced Technologies”, showing how back-end NVM, monolithic 3D integration (CEA-LETI’s CoolCube), and 3D stacking can be used to build more power-efficient systems.

TSMC expands on their InFO (integrated fan-out) technology to build inductors into the stack for integrated voltage regulators to couple with their 16-nm finFET devices (35.2). The InFO substrate was used in volume in the iPhone 7 series, so it will be interesting to see how it has evolved – we already have silicon-based trench capacitors included in the package.

35.3 discusses on-chip high-Q magnetic inductors for power conversion efficiency greater than 90%; 35.4 examines ESD diodes in a bulk GAA-NW process; 35.5 characterizes the hold-time margins of flip-flop arrays across a range of process/temperatures/voltage/aging conditions in Intel’s 22-nm finFET process.

The last presentation models the thermal resistance of the back-end interconnect and finFETs in face-up and face-down formats (35.6).

Session 36: Modeling and Simulation — Materials and Interfaces

The effects of surface roughness scattering (SRS) and how it limits carrier mobility in finFETs and GAA-NW FETs are modelled in 36.1, and the performance improvement in GaN devices given by nitridation is investigated in 36.2.

Manipulating Spin Polarization and Carrier Mobility in Zigzag Graphene Ribbons using an Electric Field” is the topic of an invited lecture by Christophe Delerue of IEMN (36.3). Density functional theory simulations were performed on HfO2/SiOxNy/SiGe stacks with a range of Si/O/N compositions (36.4), and measured experimentally, confirming that lower defect density results from a sub-stoichiometric SiON layer.

36.5 examines PBTI in InGaAs NW-FETS with Al2O3 and LaAlO3 gate dielectrics; simulations seem to show that Al2O3 performs better than LaAlO3.

Contact resistivities in n-type III-V materials are given more extensive modelling in 36.6, indicating higher contact resistivity than earlier models. The last paper (36.7) investigates the transport mechanisms of diamond-like carbon films, since these are now becoming of interest for high-voltage devices. A polarization effect was modelled in a TCAD tool, giving good agreement with experiments.
Chronologically the last paper is due at 4.30 pm – by then a lot of attendees will have headed for home, especially West-coasters who want to get home today.

We should not forget the exhibitors, either – at the time of writing we have:

Cambridge Press

Celadon Systems



Global TCAD

GMW Associates

Park Systems


Proplus Design Solutions




The exhibits are open all three days of the conference, with free coffee available – seeing as there are no coffee breaks during the sessions, it might be good to take time out and change pace in the exhibit area.

I will definitely be suffering from information overload at the end, and becoming brain-numb; but with 233 papers and an average of six parallel sessions at any one time, plus the offsite events, that’s not really surprising. On the other hand, where else do we go to get all this amazing stuff?

Time to unwind, maybe do a little holiday shopping, and go for an indulgent meal.



  • -J. Cho et al., “Si FinFET Based 10nm Technology with Multi Vt Gate Stack for Low Power and High Performance Applications”, VLSI 2016, pp. 12 -13.