Monthly Archives: July 2010

Winbond Adopts Qimonda’s Buried Wordline Technology – Metal Gates Come to DRAMs

Before Qimonda’s unfortunate demise last year, they delivered an impressive paper at IEDM 2008 [1] describing a “buried wordline” (BwL) DRAM stack-cell structure. This was a marked change from their earlier technology, as until this point all of their product had been based on planar wordline structure with trench-style storage capacitors sunk into the die substrate.

Even when we compare BwL-stack with conventional stack DRAM structures, there’s a major shift, because the buried wordline uses a tungsten metal-gate transistor – the first metal-gate transistor since the aluminum-gate days of the early ‘70s!

The Qimonda slide below shows the difference in structure; on the left is the buried wordline (in red), sunk into the substrate silicon, and on the right is an oriental competitor using a spherical recess-channel transistor (with the tungsten part of the gate highlighted in red).

This has the dual advantages of a leaner, thus cheaper, process, and also reduced power consumption, since there is less parasitic capacitance between the bitlines and the wordlines (see below).

We weren’t entirely sure that we had the BwL process when we got the Winbond 1-Gb DDR2 SDRAM parts, but the first cross-section we did in our analysis cleared that up – the white dots below the capacitor stack are the buried wordlines.

The TEM shot below shows them in close-up – you can also see that the bitlines are a W/TiN/polySi stack, also used as a gate conductor in the peripheral transistors.

Winbond’s new SDRAMs are not only a really cool, step-function change in technology, they are also unique as a volume production part – no-one else is making them at the moment. And they are in volume production, we have also found them in a point and shoot camera. Winbond has introduced the technology at the 65-nm node, but they also have 46-nm parts under development.
One other point was made by Qimonda before they went under, that this technology is particularly suitable for a cell shrink from the current 6F2 to a 4F2 format, enabling even more cost savings by reducing die size.

Elpida has also licensed the process, so given the cost and performance advantages, we can likely look forward to BwL product from Japan; and who knows what other manufacturers might go that way?

[1] T. Schloesser et al., “A 6F2 Buried Wordline DRAM Cell for 40nm and Beyond” , Proc IEDM 2008, pp. 809-812