Monthly Archives: December 2015

Intel/Micron Detail Their 3D-NAND at IEDM

By Dick James, Senior Technology Analyst, Chipworks

On the Monday afternoon at IEDM the key paper for me was the Intel/Micron talk on their 3D-NAND flash part (paper 3.3), which is currently sampling to customers. Samsung put their V-NAND flash on the market last year, but that uses charge-trap technology, whereas the Intel/Micron device has adapted conventional floating gate technology to the vertical direction.

This is the first-generation product, with 32 active tiers plus additional layers for dummy wordlines and source and drain select gates. A vertical channel surround-gate structure is used for the flash cells. The CMOS decoders and sense-amps are situated under the NAND flash array, which saves significantly on die area. It appears that this product will be a 256-Gb memory, or 384 Gb when the TLC version is introduced. Die size is 168.5 mm2, giving a bit density of 1.52 and 2.28 Gb/mm2 for the MLC and TLC devices.

Intel/Micron 3D-NAND flash die (Source: Intel/Micron/IEDM)

Intel/Micron 3D-NAND flash die (Source: Intel/Micron/IEDM)

The wordlines/control gates are horizontal polysilicon layers with an ONO inter-poly dielectric, and the floating gates are also polySi. The vertical channel and tunnel dielectric are formed in holes etched through a horizontal polySi/oxide stack.

EM cross-section of vertical-channel 3D-NAND structure  (Source: Intel/Micron/IEDM)

EM cross-section of vertical-channel 3D-NAND structure (Source: Intel/Micron/IEDM)

The process is shown below; the cell hole is first etched through the wordline tiers, and then the control gate is recessed back and the inter-poly dielectric is formed. The floating gate is then deposited, and etched back to form an isolated floating gate in each cell; the tunnel-oxide is formed, and the polySi channel is deposited to line the hole in the stack.

Process flow of vertical-channel 3D-NAND stack formation  (Source: Intel/Micron/IEDM)

Process flow of vertical-channel 3D-NAND stack formation (Source: Intel/Micron/IEDM)

M cross-section of 3D-NAND stack  (Source: Intel/Micron/IEDM)

(Source: Intel/Micron/IEDM)

An image of the full stack is shown on the right; I see 38 wordline layers, plus a thick polySi layer at top and bottom of the stack, presumably for the drain and source select transistors. There are two tungsten metal layers below the stack for the decoders and sense-amps, and also the wordline drivers; and it looks like the M3 bitline is also tungsten. There is another metal level above used for power busses and global interconnects, but we don’t know if that is copper or aluminum.

Putting the wordline drivers under the array is claimed to keep the wordlines short, but it raises some questions – how are the wordlines contacted from below? Do we have the sort of staircase at the ends of the wordlines that we saw in the Samsung V-NAND, and could it be inverted? (Can’t imagine that!)

The vertical channels contact what looks like a polySi sourceline at the base of the stack; it’s a bit clearer in this schematic:

Schematic of base of 3D-NAND stack  (Source: Intel/Micron/IEDM)

Schematic of base of 3D-NAND stack (Source: Intel/Micron/IEDM)

While the NAND cells are floating gate cells, we can see that the source and drain select devices are single gate oxide transistors.

The larger size of the cell improves the performance since it has a higher cell capacitance – more electrons can be stored, and a better natural Vt distribution (~50%) is achieved. (Note that at 20nm planar, less than 10 electrons gave 100mv Vt shift!)

Number of electrons/100mV Vt shift (left), and Vt distribution vs 20-nm planar flash  (Source: Intel/Micron/IEDM)

Number of electrons/100mV Vt shift (left), and Vt distribution vs 20-nm planar flash (Source: Intel/Micron/IEDM)

The cell geometry also means that the cell/cell interference is reduced – again, comparing to the 20nm planar chip;

Cell/cell interference of 3D-NAND vs planar NAND  (Source: Intel/Micron/IEDM)

Cell/cell interference of 3D-NAND vs planar NAND (Source: Intel/Micron/IEDM)

We will see what the commercial part looks like when we get our hands on one, likely in the first few months of next year. Unfortunately there are no scale bars on any of the images, so we have no feel for what the actual dimensions are; though probably not too different from the Samsung, which is classed as a 40nm device.

There are actually not too many features in common with the Samsung chip – vertical stacking with 32 active layers, and that’s about it. Otherwise, charge-trap technology vs floating-gate; polySi wordlines vs tungsten; metallization below the stack, vs none; and maybe a completely different way of accessing the wordlines.

For now, we wait and see!

A Look Ahead at IEDM 2015

By Dick James, Senior Technology Analyst, Chipworks

In the second week of December, the good and the great of the electron device world will make their usual pilgrimage to Washington D.C. for the 2015 IEEE International Electron Devices Meeting. To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.”

That’s a pretty broad range of topics, but from my perspective at Chipworks, focused on the analysis of chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy.

In the last few weeks I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.


Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorials on a range of leading-edge topics:

  • Electronic Control Systems for Quantum Computation, David DiVincenzo, Aachen University
  • Advanced CMOS Device Physics for 7nm and Beyond, Scott Thompson, University of Florida
  • Thin Film Transistors for Displays and MoreTom Jackson, Penn State University
  • Nanoscale III-V Compound Semiconductor MOSFETs for Logic, Luca Selmi, University of Udine
  • RF and Analog Device TechnologiesAnthony Chou, GlobalFoundries
  • Implantable MEMS and Microsystems for Neural Interface, Eusik Yoon, University of Michigan

The first three are from 2.45 – 4.15, and the remainder from 4.30 – 6.00. This year I hope to make it to Scott Thompson’s session on 7 nm and below, and possibly the GF tutorial on RF/analog at 4.30.

On Sunday December 14th, we start with the short courses, “Emerging CMOS Technology at 5 nm and Beyond” and “Memory Technologies for Future Systems”.

Last year the process short course was “Challenges of 7nm CMOS Technology”, so I guess we’ve moved on a node; though I still need convincing that the 10-nm process architectures are locked down as yet – the launches seem to be sliding a bit, to the back end of 2017, based on the quarterly stock analyst meetings that I’ve perused.

The 7-nm course has been organized by Yuan Taur, UCal San Diego, winner of the J.J. Ebers Award three years ago. He introduces it bright and early, at 8.30 a.m.

The first session is a four-hander on Device Options and Tradeoffs, with Mark Lundstrom and Xingshu Sun, Purdue University, Dimitri Antoniadis, MIT and Shaloo Rakheja, NYU presenting – we’ll see how they sub-divide the topics, but this is the time to get the low-down on the I-V Theory of Nanotransistors, III-V MOSFETs, Nanowire FETs, Band-to-Band Tunnel FETs, and 2D channel Materials.

Second up is Bruce Doris of IBM, discussing Process Integration Challenges and to follow, his IBM colleague Takeshi Nogami goes into more detail about BEOL Process Challenges . Starting the afternoon Krishna Saraswat (Stanford University) looks at Emerging Interconnect Technologies, then we have Tony Yen from TSMC reviewing Advanced Lithography (maybe we’ll get a hint of when EUV will become real), and the last talk of the day is by Asen Asenov (Glasgow University/Gold Standard Simulations) on Variability and Design for Manufacturability.

It now seems that 10nm, and probably 7nm, will be silicon-based, so we’ll see what the guys predict for 5nm; new channel materials, nanowire transistors, and how will they integrate into a manufacturable process? What will be the effects on the performance of the basic logic blocks? What will device reliability be like with the potential new materials/structures? Hopefully we’ll find out here!

The era of big data, and the big systems that will result from the internet of things, will put huge demands on the associated memory systems, so a memory review and look-ahead is appropriate; Dirk Wouters of Aachen University has organized the parallel course on our Sunday.

We start at a more civilized 9.15, and at 9.30 Rob Aitken of ARM is up with a look at the System Requirements for Memories, setting the context for the subsequent sessions. The next two talks review conventional memories; DRAM by Changyeol Lee, from SK Hynix, and Flash by Youngwoo Park of Samsung Electronics, with lunch in between.

Emerging memory is split into ReRAM and PCM, with Daniel Ielmini, (Politecnico di Milano) instructing, and STT-MRAM, from Thibaut Devolder, a CNRS Research Associate, Universite Paris-Sud.

I would call both courses a full day, seeing as we finish at ~5.30 p.m., but it’s worth sticking around to the end.

If you have the stamina, at 6.00 Leti is hosting a Devices Workshop at the Churchill Hotel, across the street from the Hilton. 


Monday morning we have the plenary session, with three pertinent talks on the challenges of contemporary electronics:

  • Moore’s Law at 50: Are we planning For retirement?, by Greg Yeric, ARM
  • Quantum Computing in Si, by Michelle Simmons, University of New South Wales
  • Silicon for Prevention, Cure and Care: A Technology Toolbox of Wearables at the Dawn of a New Health System, by Chris Van Hoof, Imec

In keeping with IEDM’s tradition of intellectual overload, after lunch we have eight parallel sessions!

Session 2 starts a track on Nano Device Technology, in this case with papers on Ge and other Group IV Devices; six presentations, including an invited paper (2.4) by Y-C Yeo (et al.) of TSMC on “Germanium-based Transistors for Future High Performance and Low Power Logic Applications”.

Session 3 gets us into the Memory Technologies track, discussing PCRAM and Flash, with the first three papers on 3D-NAND, two on PCRAM, and one on integrated one-time programmable memory (OTP). The one most likely to draw a crowd is an invited talk (3.3) by Intel/Micron about their floating-gate 3D-NAND flash (sampling at the moment, judging by their last quarterly financial call).

Samsung started shipping their V-NAND last year, but that uses charge-trap storage, in which the electrons that make up the memory bits sit on a silicon nitride layer; the Intel/Micron device uses the conventional floating-gate method used in planar flash, where the electrons are stored on a polysilicon floating gate. It’ll be interesting to see the difference!

Plan-view TEM images of Samsung V-NAND flash array

Plan-view TEM images of Samsung V-NAND flash array

Macronix is getting into the 3D-NAND game too (3.2), but their device uses a single-gate, flat-cell thin film transistor with an ultra-thin body that they have dubbed “single-gate vertical channel” (SGVC).

The gates are horizontal, defined by layer thickness, and the channels are vertical polySi stripes; this seems to be a charge-trap device, and the theory seems to be that “the design is not as sensitive to CD variation and is said to have potentially more than four times the memory density of GAA vertical channels at the same scaling node.”

Schematic of Macronix 3D-NAND flash cells (paper 3.2)

Schematic of Macronix 3D-NAND flash cells (paper 3.2)

The other 3D-NAND paper is from imec (3.1), replacing the polySi channel with InGaAs.

The two PCRAM talks (3.5, 3.6) discuss different phase-change materials, GaSb-Ge and ALD Ge-Sb-Te; and the OTP paper (3.4) from UMC/National Chiao Tung University claims a “Newly found Dielectric Fuse Breakdown” that gives “a smallest memory cell array which can be easily integrated into state-of-the-art advanced CMOS technology”.

In session 4, we take a look at Circuit Device Interactions – this is a Focus Session on Beyond von Neumann Computing, with nine presentations discussing how neuromorphic, brain-inspired computing can be implemented in our electronic world.

Session 5 starts the Modeling and Simulation track, reviewing Physical Modeling for Advanced Devices, Power Devices, and Memories, which covers off a pretty broad swath of technology, from avalanche breakdown in diamond (5.2), through GaN-on-silicon (5.3), to RRAM (5.4) and 3D-NAND (5.5, 5.6).

Integrated Thin Film Transistors (TFTs) are discussed in session 6, as part of the Display and Imaging Systems track. I didn’t know that polysilicon nanowires counted as TFTs, but we have two papers (6.1, 6.3) on that topic, and 6.2 is a study of a finTFT. We get into more conventional areas with an invited talk (6.4) on “TFT Backplane Technologies For Advanced Array Applications”, then we have three presentations on oxide-based TFTs to finish up the session.

Reliability and Characterization of Resistive RAM and BEOL Processes is the topic in session 7. In 7.1 TSMC discusses the use of on-chip charge collectors formed from antenna-coupled floating gates, used to study the actual potential on transistor gates during plasma charging stress.

SK Hynix participates in a study (7.2) on copper diffusion in through-silicon vias (TSVs), which is timely now that their High-Bandwidth Memory (HBM) has just appeared on the market.


Optical cross-cection of SK Hynix HBM stack

Optical cross-cection of SK Hynix HBM stack

Wafer Level Chip Scale Package (WLCSP) stress on high precision mixed-signal ICs is discussed by NXP in 7.3, again timely given the number of these we are seeing in mobile phones these days.

TSMC reviews TDDB lifetime models for back-end structures (7.4), and the last three papers look at RRAM reliability.

Session 8 is the first of the Process and Manufacturing Technology track, on 3D Integration and BEOL. We have a study of a self-forming Ta-Mn-O copper barrier layer from IBM/GLOBALFOUNDRIES (GF) in 8.1, which may give us a clue as to what we might see in their 10-nm back end; followed by Xilinx/Tohoku U (8.2) looking at wafer/wafer bonding of over 100,000 3-µm electrodes.

Disco Corp impressed me a few years ago by showing that they could thin wafers down to 7 µm thick – now they are claiming 2.6 µm in 8.3. They have looked at thinning effects on DRAM performance; 5.6 µm is OK, 2.6 µm is not.

TSMC also examine performance effects with thinned wafers and backside through-vias (8.4), and STMicroelectronics contributes to the next two papers, an invited talk (8.5) on 3D integration, and at the transistor end of the scale, a low-k spacer aimed at FDSOI technology (8.6).

The last two presentations are on monolithic 3D integration, where front-end layers are stacked rather than completed wafers, an intriguing concept, but with significant thermal challenges.

Session 9 reviews Advanced Compound RF and Power Devices; I could go through these in detail, but for the sake of brevity I’ll just say that five of the six papers discuss GaN devices, and the exception is about a vanadium oxide-on sapphire RF switch with a record switching cut-off frequency of 26.5THz (9.3).

Then in the evening we have the conference reception at 6.30, through until 8 pm. This year is the International Year of Light, plus the 50th Anniversary of Moore’s Law, so IEDM is celebrating with a special laser light show – should be fun!



In the morning we have another seven parallel sessions, starting at 9 am, with session 10 on RRAM in the Memory Technology track. The first paper (10.1, from Micron) is an invited discussion of “Non Volatile Memory Evolution and Revolution”. Judging by the authors, most of the papers are research, but in 10.5 Tsing-hua U/TSMC report an RRAM that uses a FinFET transistor for the “select” gate and an adjacent FinFET’s HfO2-based dielectric film for a storage node of the RRAM cell, in a 16nm process; and 10.7 is a consideration of RRAM use for security applications from GF.

Schematics and TEM Cross-section of finFET RRAM (10.5)

Schematics and TEM Cross-section of finFET RRAM (10.5)

Session 11 is the second Circuit Device Interaction session, this time on CMOS Scaling and Circuit/Device Variability. It kicks off with a paper by Renesas on 8T SRAM design in (presumably) TSMC’s 16-nm process (11.1), followed by a discussion from GF on self-aligned double patterned (SADP) BEOL use for a sub-10nm SRAM bitcell (11.2).

Samsung is up next (11.3), with a study on BTI variation in finFET SRAMs, then TSMC discusses magnetic thin-film inductors integrated into CMOS (11.4); Cadence gives an invited talk on the simulation of the variability of reliability of IC design (11.5); imec looks at the self-heating effects of bulk FinFETs from the 14nm to the 7nm node (11.6); and layout dependent aging in HKMG devices is detailed by Peking U. (11.7, with heavy SMIC involvement) in the last paper.

Session 12 is another on Modeling and Simulation, this time on 2D and Organic Semiconductor Devices. Black phosphorus devices are covered off in the first two papers, (12.1, 12.2), and 2-D tunnel FETs are examined in 12.312.5. Paper 12.6 is an invited talk on “Charge Transport Modelling in Organic Semiconductors” from the University of Rome, and the last paper (12.7) discusses the nature of metal-graphene contacts.

We move into the medical arena in session 13, a focus session on Silicon-based Nano-Devices for Detection of Biomolecules and Cell Function, with six invited papers on bio-analysis and measurement.

Flash and Novel Device Characterization and Reliability is the subject of session 14, starting with an imec paper (14.1) on Scanning Spreading Resistance Microscopy (SSRM) of a finFET, using diamond-based probe tips to scrape off material as the surface is repeatedly scanned to create a 3-D resistance profile.

Tunnel FETs are studied in the next two talks (14.2, 14.3), then we have two Si nanowire papers, again from imec (14.4, 14.5). U Tokyo details work on the reliability of Ge gate stacks in 14.6, and NAND flash reliability is the topic of 14.7 and 14.8.
Session 15 is the second in the Process and Manufacturing Technology track, this time on Moore and More; the first three presentations (15.115.4) discuss Ge and III-V devices, then we have an invited talk (15.5) on nanocarbon interconnects. Paper 15.6 reports on a photonic BiCMOS process, and in the last paper we hear about thin RF-SOI CMOS on flexible substrates (15.7).

Diamond-shaped Ge nanowire (paper 15.4)

Diamond-shaped Ge nanowire (paper 15.4)

30µm-thick RF-SOI CMOS circuits laminated on a flexible substrate (paper 15.7)

30µm-thick RF-SOI CMOS circuits laminated on a flexible substrate (paper 15.7)

The speaker at the conference lunch will be Pat Tang, VP of Product Integrity, Amazon, presenting on “Working backwards from the Customer to Physics of Failure in Consumer Electronics Reliability”. This talk will examine a product integrity vision based on 3 technical strategies:

  1. Working backwards from the customer to physics of failure
  2. Design for reliability through simulation tools;
  3. Development of customer-use centric standards using stress-strength analysis.

Pat joined Amazon in 2010 to lead Product Integrity and is responsible for the architectural integrity and product reliability of Amazon’s Kindle Fire tablets, e-readers, Fire TV and Fire Phone products. He was at Apple before that, where he was the reliability manager responsible for the qualification of Mac products such as the Macbook Pro, Macbook Air, iMac, MacPro, AppleTV and the first prototypes of iPad, so familiar with many of the products that have changed our lives in the last decade.

Session 16 is a focus session on Advances in Wide Bandgap Power Devices, part of the Power and Compound Semiconductor Devices track. As such we have eight invited talks, beginning with a review of “State-of-the-Art GaN Vertical Power Devices” (16.1) from Toyota.

Then imec looks at “200mm GaN-on-Si Epitaxy and e-mode Device Technology” (16.2), followed by Intel (16.3) discussing high-k GaN MOS-HEMTs. Paper 16.4 also reviews GaN power devices, and in 16.5 CEA-Leti steps back a bit to examine GaN epi on silicon and packaging topologies in the context of power electronics.

In 16.6 MIT details recent work on GaN-only normally-off transistors, HRL Labs talks about increasing the switching frequency of GaN HFET converters in 16.7; and the session finishes with STMicroelectronics giving a (presumably) more commercial survey of “SiC- and GaN-based Power Devices: Technologies, Products and Applications” (16.8).

Session 17 looks at Neuromorphic Computing Techniques in the circuit/device interaction track; definitely at the academic end of the scale for me, although seven of the eight papers use phase-change or resistive memory as synapses, so if this style of computing takes off that seems to bode well for emerging memory.

M/NEMS Resonators, Sensors and Actuators are considered in Session 18, covering sensor arrays (18.2), nanowires (18.3), transducers (18.4, 18.6), resonators (18.5), and energy harvesting (18.7).

The next parallel session is another focus session, this time on Flexible Hybrid Electronics (Session 19). Mostly research reviews, but paper 19.3 details an ultrathin Si-based flexible NAND flash memory, and 19.4 describes changing advanced CMOS electronics into a flexible and stretchable form.

Transistor Ageing, Variability and the Impact on Circuit Design is the subject of Session 20; NBTI is the topic of 20.1, off-state self-heating in scaled technologies (presumably including finFETS) is dealt with in 20.2, and more specifically self-heating in ETSOI is covered in 20.3. Paper 20.4 discusses hot-carrier aging, and “Technology Scaling and Reliability: Challenges and Opportunities” is an invited review in 20.5.

Samsung surprised me with the launch of their 14-nm finFET chip in this year’s Galaxy phone, and we get a peek at the “the extensive 14nm FinFET reliability characterization work” carried out by them in paper 20.6.

Random telegraph noise vs timing data investigated in a 32nm test chip in 20.7, and Rob Aitken of ARM gives an invited talk on “Implications of Variability on Resilient Design” in the last talk of the session (20.8).

Session 21 is the third in the Process and Manufacturing Technology track, on Advanced Modules and FinFET Devices. This looked like it might be the session where we get key papers on new production processes (such as the Samsung 14-nm), but I think we’re out of luck. Having said that, we do have some interesting papers on the program.

IBM starts off with a discussion (21.1) on “Understanding and Mitigating High-k Induced Device Width and Length Dependencies for FinFET Replacement Metal Gate Technology”. In the abstract it says that the gate fill metal is important to obtain a flat Vt-W response; given that finFET gate width is quantized, I’m curious to see what they have to report.

GLOBALFOUNDRIES gives an invited paper “Variation Improvement for Manufacturable FINFET Technology” (21.2), though it considers a 90-nm CPP process, not the Samsung-based 14-nm process now ramping up, which has a CPP of 78 nm. Gate stack, junction, and gate height variation were identified as key contributors to threshold voltage variation; I think we’ve seen that demonstrated before, but GF’s take will be of interest.

In paper 21.3 Tsing Hua U. reports on a bi-layer stacked gate dielectric, claiming improved drive current due to enhanced carrier mobility, resulting from less remote scattering caused by fewer charged oxygen vacancies.

Tokyo U. tries to clarify the SiO/HfO interaction in the common HKMG gate stack in 21.4, and in 21.5 they study “Preferential Oxidation of Si in SiGe for Shaping Ge-rich SiGe Gate Stacks”, which uses the different oxidation kinetics of Si vs Ge to optimize the gate stack.

Paper 21.6 is an imec study of Ge nFETs, looking at Si surface passivation and La band engineering; and in a joint work with Samsung (21.7) we hear about the contact resistance of Si:P source/drain epi with Ge pre-amorphization and Ti silicidation.

The last talk (21.8) is another imec joint paper, this time with ASM, detailing the use of phospho-silicate glass (PSG) to dope source/drain extensions. Last year we heard about Intel using PSG for solid-phase doping the base of the fin to reduce punch-through – now another example of this decades-old doping technique being re-used!

We go from finFETs to Steep Slope Transistors in session 22, with the first four papers discussing tunnel-FETs (TFETs), starting with an invited review by Intel (22.1). SMIC tells us in 22.2 that they’ve integrated TFETs into one of their foundry processes, and Forschungszentrum Jülich and MIT report on their TFET work in 22.3 and 22.4.

Papers 22.5, 22.6 detail studies on HfZrOx FETs, and the last presentation (22.7) describes a new type of SOI FET with a super-steep subthreshold slope of less than 6 mV/decade.

That brings us to the end of the afternoon, and Applied Materials is again hosting a panel on “The Changing Face of Non-Volatile Memory” at the Omni Shoreham Hotel on Calvert Street NW from 6.15 – 7.40 pm. They usually cater us well, so once we’re sated from the hospitality we can wander back to the Hilton for the conference evening panels:

Is there a potential for a revolution in on-chip interconnect?”, and;

Emerging Devices – Will they solve the bottlenecks of CMOS?”

This year we are back to two panels, but the first is portrayed as more of an election, so we have the following candidates:

  • The incumbent: Rod Augur, GlobalFoundries
  • We can design around it: John Wilson, nVidia
  • Nano/novel materials or devices to the rescue: Azad Naeemi, Georgia Tech
  • Active Interconnect: Toshi Sakamoto, NEC
  • Monolithic 3D: Maude Vinot, CEA
  • Multilithic 3D: Paul Enquist, Ziptronix

Moderated by Paul Franzon of North Carolina State University.

The parallel panel has Heike Riel, IBM Research as moderator, with Supriyo Bandyopadhya (Virginia Commonwealth University), Wilfried Haensch, also of IBM Research, Adrian Ionescu, EPFL, Carlo Reita, CEA-LETI, Sayeef Salahudin, UC Berkeley, and Frank Schwierz, Technical University of Illmenau as the distinguished panelists.


Wednesday morning has sessions 25 – 31; S25 is another Circuit Device Interaction session, with the intriguing title of “More than Moore – Value Added Technologies”. As a session, it’s bracketed by Toshiba, with two papers – the first, 25.1, reports on the use of magnetic tunnel junction (MTJ) memory for L2 and L3 cache memory in a CPU. They claim that with this technique, CPU power and chip area can be reduced 65 % and 37 % compared to conventional SRAM based CPU.

The second Toshiba talk (25.8) describes multi-gate oxide, dual work-function (MGO- DWF)-MOSFETs, with asymmetric LV-source/HV-drain junctions. This structure is reported to have an FMAX of 150 GHz, making it a contender for a low-power RF power amplifier.

We stay with RF in 25.2, but in a completely different context, as TSMC plugs their InFO fan-out packaging scheme in “High Performance Passive Devices for Millimeter Wave System Integration on Integrated Fan-Out (InFO) Wafer Level Packaging Technology”. There has been a lot of press gossip about the possible use of InFO for next year’s Apple A10 processor, so it’s a different spin to see InFO used down at the RF end of a phone.

25.3 is also an RF paper, this time discussing a reconfigurable 3/5 GHz, 0.13 μm CMOS low-noise amplifier, flip-chip integrated with a four-terminal phase-change RF switch. Intel is co-authoring this with Carnegie Mellon U. and John Hopkins U., so could this be using their EMIB co-packaging technology?

TSV-free monolithic 3D-IC stacking is the subject of 25.4, layering ultra-thin body devices and using CO2 far-infrared laser annealing (CO2-FIR-LA) technology for dopant activation. This is claimed to avoid device degradation, and a test chip with logic circuits, 6T SRAM, ReRAM, sense amplifiers, analog amplifiers, and gas sensors was fabricated to demonstrate the practicality of the scheme.

Next we have an invited review (25.5) of “New Devices for Internet of Things: A Circuit Level Perspective”; IoT had to show up somewhere!

If you know what Physically Unclonable Functions (PUFs) are, then paper 25.6 may be of interest – a “Robust and Compact Key Generator Using Physically Unclonable Function Based on Logic-Transistor-Compatible Poly-Crystalline-Si Channel FinFET Technology”.

IBM goes opto in the penultimate paper 25.7, looking at the integration of CMOS, RF and optoelectronic devices to enable low-cost O-band datacom transceivers.

In S26 we get back to memory. The first four papers, 26.126.4 detail a variety of STT-MRAMs, a 40-nm macro in 26.1, and a 28-nm macro in 26.2, while 26.3 reports a double magnetic tunnel junction device; and 26.4 studies the size dependence of the thermal stability of perpendicular STT-MRAM.

Samsung discloses some of the technology in their 20-nm DRAM in 26.5; we’ll see if it agrees with what we found in the part that we looked at! They refer to the use of “honeycomb structure and air-spacer technology” as being capable of taking us into the 1x-nm generations.

Air spacer between bitline and storage node contact in Samsung 20-nm DRAM (26.5)

Air spacer between bitline and storage node contact in Samsung 20-nm DRAM (26.5)

Next up, SH Hynix has a talk on HKMG transistors in DRAM peripheral circuitry (26.6), something we have speculated about but not yet seen. The last paper, 26.7, reveals a one-transistor SRAM cell using a lateral MOS for access, and intrinsic vertical open-base bipolar structures for self-latch function.

Layered 2D Materials and Devices: From Growth to Applications is the topic of Session 27; from the look of the abstracts, we have seven invited talks which will give us a comprehensive review of the state of 2-D materials in electronic devices, predominantly graphene and molybdenum sulphide.

We go back into the world of Compact Modeling in session 28; the first two talks look at modeling zinc oxide and IGZO thin-film transistors (28.1, 28.2) used in displays. In 28.3 we get into finFETs with Asen Asenov’s, group, Gold Standard Simulations, examining the effects of the gate edge roughness and fin edge roughness.

Paper 28.4 looks at modeling graphene FETs for RF applications, 28.5 analyses STT-MRAMs, and the last paper (28.6) is an invited review, “Physics-based Compact Modeling of Charge Transport in Nanoscale Electronic Devices”.

Session 29 is an example of IEDM broadening its take on electron devices, since this session considers Devices for In Vitro Bioanalytics and In Vivo Monitoring. So for me there are new concepts such the field-effect control of ions in nanofluidic transistors (NFTs) in 29.1, ion-sensitive FETs (29.2, in this case fabricated in SOI-CMOS), and pH imaging sensors using CCDs (29.3).

We also have disposable ‘electronic microplates’ in 29.4 that use mechanically-flexible interconnects and TSVs to connect the electrodes on a CMOS biosensor to the electrodes on the electronic microplate, while keeping physical separation, and a CMOS-based “High Density Optrode-electrode Neural Probe” (29.5).

The last two papers report on “an ultra-thin (5um) implantable system using organic light emitting diodes and organic photodetectors in a reflectivity monitoring system suitable for hemodynamic measurement of the brain” (29.6), and a microbubble blood pressure sensor mounted on an acupuncture needle in 29.7.

A completely different world from chips in mobile phones, though I don’t doubt that app’s will be developed for some of them!

Advanced Imagers and Photodetectors are dealt with in session 30; Olympus is first up (30.1), with “Multi-storied Photodiode CMOS Image Sensor for Multiband Imaging with 3D Technology”, using two stacked imagers that function individually for optimized performance.

Olympus stacked image sensor with RGB light imager on top and IR sensor below (30.1)

Olympus stacked image sensor with RGB light imager on top and IR sensor below (30.1)

Panasonic reports on an organic photoconductive film sensor in 30.2, then we have an invited paper from NHK Labs (30.3), also on an organic photoconductive image sensor.

A “BSI Image Sensor with Stacked Grid Structure” is discussed by TSMC in 30.4, and 30.5 is a photo-detector paper demonstrating a GeSn multiple-quantum-well-on-Si avalanche photodiode. A “Selenium/CMOS Hybrid Digital X-ray Imager” is described in 30.6; another stacked sensor, this time with a CMOS image sensor overlaid with a chlorine-doped crystalline selenium photo-conversion layer, is detailed in 30.7.

We return to power and compound semiconductor devices, in the form of III-V: FETs, Photonics, Si Integration in session 31. The first paper, 31.1, is on “Gate-All-Around InGaAs Nanowire FETS”, by imec et al., then we have “Vertical InAs Nanowire MOSFETs on Si” from Lund University (31.2), followed by an MIT talk (31.3) on “Quantum-size Effects in sub 10-nm fin width InGaAs FinFETs”.

Lund University returns in 31.4 with “Single Suspended InGaAs Nanowire MOSFETs”; followed by an invited paper by U. Tokyo discussing “CMOS Photonics Technologies Based on Heterogeneous Integration of SiGe/Ge and III-V on Si” (31.5).

MIT is back with a report on an InGaSb p-channel FinFET in 31.6, and the last paper of the session (31.7) is from imec again, on an InGaAs TFET with claimed superior SS reliability over a MOSFET.

After the morning sessions, the IEDM Entrepreneurs Lunch features Abbie Gregg, President of Abbie Gregg, Inc. (AGI), an engineering consultancy specializing in microelectronics process analysis and the design, startup and operations of clean laboratories and manufacturing facilities.

We are back to the Nano Device Technology track – Beyond CMOS Technologies in S32 after lunch, and U. Texas/Austin has the first paper in 32.1, looking at 2D nanomaterials, which would seem ideal for flexible electronics, in this case fabricating RF transistors.

32.2 describes a transition-metal dichalcogenide (TMD) body FinFET with back-gate control, postulated as a possible candidate for 2-nm technology, and 32.3 details a single-layer CVD molybdenum disulphide FET.

The next talk (32.4) is not a device report; it describes a method for separating semiconducting carbon nanotubes (CNTs) from metallic CNTs. The last two papers have spintronics as the topic, with an invited talk on “Spintronic Majority Gates” (32.5), and a demonstration of spintronic switch prototypes that encode information in a magnetic domain wall (32.6).

Session 33 has Emerging Nanodevices and Nanoarrays as the subject, beginning with two papers on vacuum nanoelectronics. MIT has fabricated (33.1) nanoscale cold cathodes (tiny electron guns) built from arrays of nanowire (NW) field emitters, with a current density of >100 A/cm2. Each emitter (6-8nm tip diameter) sits atop a vertical silicon nanowire (10µm tall, 100-200nm in diameter). The nanowire acts as a current limiter to protect the emitter from possible damage from heating and arcing.

Top - schematic of field-emission array. Bottom left – SEM cross-sectional view of Si NW current limiter with gate oxide removed to show details; right, emitters are shown

Top – schematic of field-emission array. Bottom left – SEM cross-sectional view of Si NW current limiter with gate oxide removed to show details; right, emitters are shown

33.2 is a simulation study of proximity effects on transmission efficiency and crosstalk in field emission vacuum microelectronic devices.

Next up is a MEMS plasma generator (33.3) designed for use in liquids, followed by an invited review (33.4) of “Nanoarrays for Disease Detection via Volatolomics” – it appears that volatolomics is the profile analysis of volatile organic compounds which are by-products of metabolic and pathological processes, and are emitted from various body fluids including breath, skin, urine, blood, and others.

Flexible graphene Hall sensors are described in 33.5, then “Suspended AlGaN/GaN Membrane Devices … for Ultra-low-Power Air Quality Monitoring” (33.6) finishes the session.

Modeling of III-V and Ge Materials and Alternative CMOS Device Architecture are dealt with in session 34. Intel gives the first presentation, discussing “CMOS Performance Benchmarking of Si, InAs, GaAs, and Ge Nanowire n- and pMOSFETs” (34.1), hopefully a summary of some of the wide-ranging R&D they have been doing in the last few years.

The next paper (34.2, U. Tokyo) discusses the intrinsic properties of Ge films in terms of phonon and electronic structures, providing critical parameters for device modeling. In 34.3, IBM looks at replacement metal gate resistance in FinFETs, coming to the conclusion that TiN gate fill is better than TiN/W for highly scaled gate lengths.

Process variation effect (PVE), work function fluctuation (WKF), and random dopant fluctuation (RDF) in 10-nm high-k/metal gate gate-all-around silicon nanowire MOSFET devices are studied in 34.4 (National Chiao Tung U.); with the result that the NW device has greater immunity to RDF, while suffering from PVE and WKF.

Intel is back in 34.5, in a “Study of TFET Non-ideality Effects for Determination of Geometry and Defect Density Requirements for Sub-60mV/dec Ge TFET”; and finally, ETH Zurich discusses InAs-GaSb/Si heterojunction TFETs in 34.6.

The last session (numerically), session 35, covers GaN Material and Device Interactions. MIT/Synopsys start the session off (35.1) with “Design Space and Origin of Off-State Leakage in GaN Vertical Power Diodes”, in which dislocations were identified as the main off-state leakage mechanism for GaN vertical diodes on different substrates; the authors claim that “designed GaN vertical diodes demonstrate 2-4 orders of magnitude lower leakage current while supporting 3-5 times higher electric field, compared to GaN lateral, Si and SiC devices.”

The next paper (35.2, ON Semi et al.) reports on the correlation between the off-state vertical leakage of 650V rated GaN-on-Si power devices and the dynamic Ron.

In 35.3, HKUST demonstrates a power FET with photonic-ohmic drain (PODFET) using a HEMT-compatible process on a conventional AlGaN/GaN-on-Si power electronics platform. It appears that photons are synchronously generated with the switching channel current, and they pump electrons from deep surface/bulk traps, improving the device dynamic performance.

Imec/ON Semi have been looking at how different parts of AlGaN/GaN buffers on Si contribute to the observed current collapse in devices, comparing three different types of buffers, namely stepped buffers, low temperature AlN interlayer buffers, and superlattice buffers (35.4).

Infineon et al. (35.5) report on AlGaN/GaN MIS-HEMTs with a fluorine-passivated dielectric/AlGaN interface, causing a modification of the “native” surface donors, leading to a fundamentally different device and defect behavior; potentially a new direction for reducing VTh drifts or defect engineered devices.

We finish the session with an invited review of “Steep Subthreshold Swing TFETs: GaN/InN/GaN and Transition Metal Dichalcogenide Channels” (35.6, U. Notre Dame et al.).

Chronologically the last papers are due at 3.40 pm – by then a lot of attendees will have headed for home, especially West-coasters who want to get home today.

I will definitely be suffering from information overload and becoming brain-numb, but with 230 papers and an average of six parallel sessions at any one time, plus the offsite events, that’s not really surprising. On the other hand, where else do we go to get all this amazing stuff?

Time to unwind, maybe do a little holiday shopping, and go for an indulgent meal.