By Dick James

IEDM this year was its usual mixture of academic exotica and industrial pragmatica (to use a very broad-brush description), but the committee chose to keep us all waiting until the Wednesday morning before we got to the CMOS platform papers. Of course, the talk we were all anticipating was Intel’s Chris Auth on “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects”.

Deliberate or not, Intel has been teasing us with release dates for their 10-nm products, and as yet there have not been any out in the market for the analysts to get their hands on and expose the secrets. TSMC and Samsung we have seen, but not Intel (and arguably, they are closer to 14-nm technology). Needless to say, the room was full, and Chris did the usual Intel preamble about being ahead of the 2x shrink trend, and achieving 100M transistors/mm².

 

The claim is that density increases by a factor of 2.7 from the 14nm generation, using the metric announced by Mark Bohr at the Technology and Manufacturing Day (TMD) earlier this year:

 

The paper states that this was achieved by “use of SAQP w/193nm immersion lithography, improved transistor matching to enable fewer fins in the standard cell library and novel process features to enable tighter layout.”

The table below shows the design rules and shrink from the 14-nm process:

Any pitch 40 nm or below needs quad-patterning (or LELELE), so the fins, M0 and M1 use SAQP. Compared with SADP, Intel’s SAQP needs four additional steps, one deposition on the sidewall spacers from the original mandrel, and three etch steps. In addition to the feature shrinks, there are technology changes in the standard cell layout. The dummy gates at the cell boundaries have gone, replaced by a single gate spacing; and the gate contact is now over the active gate, ending the need for isolation space to fit in the contact.

The 14-nm process had a dummy gate at the edge of each cell, on the end of adjacent fins, similar to this image of a 22-nm device;

The 10-nm cell uses a dummy gate spacing between fin ends, which saves a gate pitch when packing two cells together, a claimed 20% cell area saving.

 

 

In actual fact there is no dummy gate in the finished product, just the fin etched where a single dummy gate would be. This was shown in the presentation, but it is not in the paper, but Samsung did something very similar in their 10-nm offering:

 

In fact, a dummy polySi gate is used, allowing source/drain formation without risking the fin edge; but for these particular gates the polySi removal etch goes a bit further, and etches the fin to separate the cells.

The second layout change is to shift the gate contact into the active transistor area, over the functional part of the gate (see below).

 

Such tight alignment with the source/drain (diffusion) contacts requires the development of self-aligned contacts to the gate, and modification of the self-aligned diffusion contacts that were already in use at 14-nm and 22-nm.

To do this, two etch-stop materials and two selective etches are used. After gate formation it is etched back and the cavity is filled with silicon nitride, as in earlier generations; the contact is then put in and also etched back, and the cavity is filled with silicon carbide. Then there is a selective etch to open the gate contact, which does not touch the SiC in the contact cavity, and a second selective etch removes the SiC from the contact cavity, but does not affect the gate contact periphery. Clearly this sequence is reliant on excellent etch selectivity between the different materials.

There are other innovations in the contact stack – the contacts themselves are cobalt, giving >60% line resistance reduction, and there is a conformal titanium layer wrapped around the source drain epi, as well as a thin nickel silicide layer on the PMOS epi. This is claimed to give ~1.5x contact resistance reduction.

The fins are SAQP-defined with a 34-nm pitch, 7 nm width (at ½-height), and 46 nm height. Intel appeared to have backed off on the 53-nm fin height that they announced back in March. 46 nm is still an increase from the 42 nm of the 14-nm process, just not as ambitious; if memory is accurate, that is the same as the 14+ fin height. I guess the taller fin could be looking forward to the 10+ or 10++ generation. In the Q&A we were told that the fin height is tunable with a range of ~10 nm, and 46 nm is at “the low end of the mid-range”.

In fact, if you use the fin pitch as calibration, the fin height in Intel’s image is ~52 nm, and close examination reveals that it is the same image as that shown in Kaizad Mistry’s TMD talk last March.

And if we compare this pic with the 14-nm device, it appears that the solid-source punch-stop diffusions introduced at 14-nm are present, since we can see the seal layer(s).

 

This allows the fin to be un-doped in the channel, with options for four or six V_ts (low, standard and optional high V_ts) with differing work-function metals. Source/drain epis are in-situ doped and provide strain enhancement, though we are not told if that is N- or P-MOS or both, nor is SiGe mentioned, though I would assume it is still used for PMOS stress. NMOS drive is also enhanced by interlayer dielectric stress, giving a ~10% improvement (from my notes – the paper says 5%).

With a smaller fin pitch the implant angle needed for doping is also shrinking; I measured it as less than 30^o, compared with the 52^o and 41^o of the 22- and 14-nm processes, but I am told that if the implant has a twist (i.e. angled with respect to the fin orientation), then it is till feasible to get implants into the right location.

Additionally, the k-value of the sidewall spacers has been lowered, to reduce the parasitic contact-gate capacitance by 10%, and my notes also say that the gate fill has been changed to cobalt.

With a 46-nm fin height the gate width should be ~97 nm, compared with the ~85 nm of the previous generation (or the same as the 14+). If the 53-nm fin height is used, gate width is likely ~110 nm. Minimum gate length was stated to be 18 nm.

All of this transistor engineering leads to a NMOS Idsat of 1.78 mA/µm and Idlin of 0.475 mA/µm at 0.7 V and 10 nA/µm, increases of 71% and 100% compared to 14-nm FINFET transistors, for minimum Lg devices. Similarly, PMOS shows drive current gains of 35% Idsat and 55% Idlin. Steep subthreshold slopes (~70 mV/dec.) and very low DIBL (~70 mV/V) are also found.

The middle- and back-end stack has thirteen metal layers (including M0), with cobalt used in M0 and M1 to replace copper. This gives a 2x resistance reduction, and 5 – 10x electromigration improvement. Self-aligned double patterning (SADP) is used at Metal 2 – Metal 5, and a cobalt cap (no liner, as in TSMC) is also used on M2 – M5 to improve electromigration. Low-k dielectrics are used on eleven layers out of the thirteen, and in the Q&A it was noted that it is the same low-k as in the 14-nm process.

The SRAM cells are scaled by a factor of ~0.6, so that the low-voltage 1:2:1 (fins in Pull-Up:Pass-Gate:Pull-Down transistors) cell goes from ~0.059 µm² to ~0.0367 µm², and the high-density 1:1:1 cell shrinks from ~0.050 µm² to ~0.0312 µm². (The TSMC and GF/IBM/Samsung 7-nm cells announced at IEDM16, presumably 1:1:1 cells, were 0.027 µm².) There is also a high performance 0.0441 µm² cell. Ring oscillator performance at 0.7 V was 20% better than the 14-nm device.

The cell height is 272 nm, so with a 34 nm fin pitch, we have eight fin spacings per cell; but we tend to lose two fins in the centre to allow for well boundaries, and one each at top and bottom under the Vdd/Vss lines, implying 2x two-fin transistors in the minimum standard cell. That agrees well with the comments in the paper about “aggressive reduction in fin usage, improving transistor density.”

Back in March we were told that the 10-nm process shrinks beyond the usual 50% to 37% of the 14nm technology:

And that this actually brings them back on to a two-year cadence from the 45-nm node, assuming high-volume production as of the second half of this year.

It’s a bit close to the end of the year for that to happen, but if we see product in the New Year they won’t be too far off – we look forward to it!

I had hoped to fit in some commentary about the GLOBALFOUNDRIES 7nm paper given in the same session, but in the interest of brevity I will have to make a separate blog, maybe in the New Year.

Part 1 of Dick James’ preview can be read here. 

By Dick James

Wednesday

Most of the sessions Wednesday morning are limited to five papers, since we have a second plenary session (30) at 11.10 am.

Session 28: Memory Technology – In-memory Computing

28.1 looks at the modeling-based design of brain-inspired spiking neural networks with RRAM learning synapses. A comprehensive model for spiking neural networks based on spike-timing dependent plasticity in RRAM synapses is presented.

A dual-mode computing (DMc) ReRAM macro structure with a dual-function voltage-mode self-write termination (DV-SWT) scheme is proposed in 28.2, to achieve both memory and fundamental computing-in-memory (CIM) functions (AND, OR and XOR operations). A 16Mb DMc-ReRAM full-function macro was fabricated using 1T1R HfO ReRAM devices and 0.15um CMOS process. The measured delay of the CIM operations is less than 14ns, which is 86+x faster than previous ReRAM-based CIM works.

 

In 28.3 a new method for fast and robust compressed sensing recovery of sparse signals using computational memory (CM) is proposed. (CM performs certain computational tasks within resistive memory units.) Large-scale experimental demonstrations using more than 256k phase-change memory devices are presented along with an in-depth device analysis and array-level considerations.

Next up is an invited paper that presents data-aware NAND flash memories (28.4). By recognizing the data value, sophisticated data management such as storing important data in reliable memory cells, or adaptively optimizing read voltage are realized. Consequently, intelligent computing such as image recognition with deep neural networks, data compression and disaggregated hybrid storage can be achieved.

Given the processes mentioned, this (28.5) looks like a GLOBALFOUNDRIES-sponsored paper, on a reconfigurable NAND/NOR logic gate based on a single ferroelectric FET (FeFET) in 28 nm HKMG and 22 nm FD-SOI FeFET technology. The gate uses hafnium oxide as the ferroelectric material with a pull-up device connected in series.

Session 29: Circuit and Device Interaction – Advanced Platform Technologies

Intel 10nm

This is the session that a lot of us will be waiting for – Chris Auth of Intel is first up (29.1) with “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects”. 

 

The transistors feature rectangular fins with 7 nm fin width and 46 nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon. Self-aligned quadruple patterning (SAQP) is used for critical layers such as fins and minimum metal (34 nm and 36 nm pitches, respectively). Four or six work-function metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices. NMOS and PMOS current is 71% and 35% greater, respectively, compared to 14-nm FinFET transistors. For high density, a self-aligned  contact over active gate process and elimination of the dummy gate at cell boundaries are introduced, as described in the Technology and Manufacturing Day last March.

Intel appeared to have backed off on the 53-nm fin height that they announced back in March (above), so the final fin profile could be different, especially if they are actually rectangular. 46 nm is still an increase from the 42 nm of the 14-nm process, just not as ambitious; I guess the taller fin could be looking forward to the 10+ or 10++ generation, definitely one for the Q & A!

There are 12 metal layers of interconnect, with cobalt in the lowest two layers that yield a 5-10x improvement in electromigration and a 2x reduction in via resistance, and ultra-low-k dielectrics throughout the interconnect stack. Three different types of SRAM cells are detailed, a high-density 0.0312 µm² cell, a low voltage 0.0367 µm² cell, and a high-performance 0.0441 µm² cell.

29.2 is an invited talk from S. Barraud of CEA-Leti; “Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs”, reviewing recent progress on GAA-NW and NanoSheet (NS) MOSFETs. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power- performance optimization.

IBM/Samsung/GF are also looking at nanosheets in 29.3, in which a quantitative performance evaluation of horizontal nanosheet structures across a wide range of sub-7nm design spaces is presented.

 

Intel 22FFL

Intel also announced their 22FFL process in March, now we get a paper on it (29.4); clearly aimed at the foundry business and IoT products, it appears to an upgrade from the 22-SoC process [1]. Or maybe it’s a relaxed 14-nm process, we’ll have to see the transistor profile to make that call. The raw dimensions, as you’d expect, are in between.
We still have double-patterned fins, but the gate and metal are single-patterned, and the SRAM cell size puts it close to the 22-nm node. The process combines high-performance, ultra-low power logic and RF transistors; the high-performance transistors show 57%/87% higher NMOS/PMOS drive current compared to the 22-nm technology. New ultra-low power logic devices reduce bitcell leakage by 28x compared to a regular SRAM cell, and an RF device with optimized layout has been developed and shows excellent fT/fMAX of 230 GHz/284 GHz and 238 GHz/242 GHz for NMOS and PMOS respectively.

Other SoC features are high resistance substrate, deep N-well isolation, precision resistors, MIM capacitors, and high-Q inductors.

The final talk (29.5) is a late-news submission from GLOBALFOUNDRIES on their upcoming 7-nm platform (don’t forget, GF are skipping 10 nm). It features 3^rd-generation SAQP finFET architecture, and SADP BEOL metallization, with an improvement of 2.8X in routed logic density and >40% performance over the 14nm reference technology. Multiple Vts are derived from “a unique multi-work-function process”, giving low-voltage SRAM response and highly scaled memory areas. The HD 6-T bitcell size is 0.0269 um². The technology uses immersion lithography, but is also designed to adopt EUV for specific levels, for cycle time benefit and manufacturing efficiency, when EUV is ready.

 

Session 30: Plenary Session II

This year we have a second plenary session squeezed in with the other sessions, so that the awards associated with the traditional Tuesday conference lunch can be presented. After that we have a plenary paper (30.1), “Development of Sustainable Smart Society based on Transformative Electronics”, from M. Ogura of Nagoya University. The title belies the rest of the abstract, since it focuses on gallium nitride defects and GaN nanorod devices:

“Defects which cause leakage under a high-voltage reverse-biased condition were identified in GaN pin diodes grown on freestanding GaN substrates. The performances of GaN-based horizontal-heterostructure superjunction high-electron mobility transistor and a GaN-nanorod-based vertical pn-superjunction diode were simulated. A vertical pn-superjunction was fabricated using GaN nanorod growth technology.”

 

Session 31: Modeling and Simulation – Simulations of Nano-devices

31.1 is an invited study of time-resolved energy currents in a molecular optoelectronic junction made of two donors and an acceptor, sandwiched between two electrodes and excited by a Gaussian femtosecond laser pulse. Features of the direct energy currents are thus correlated to the intra-molecular structure.

Gate-induced-drain-leakage (GIDL) in 2D FETs is evaluated by UCal Santa Barbera/Micron using a novel quantum transport methodology (31.2). GIDL is a key issue in access transistors, and the results establish the advantages of certain 2D semiconductors in greatly reducing GIDL, and thereby support use of such materials in future memory technologies.

UCal Santa Barbera presents again (31.3), on “How to Derive the Highest Mobility from 2D FETs – A First-Principle Study” – a comprehensive mobility modeling framework for 2D-semiconductor FETs is developed, and applied to study the impact of synthesis technology, defect concentration, electric field, and channel/dielectric materials on the mobility.

In 31.4 a unified surface potential based physical compact model for both unipolar and ambipolar 2D-FETs is developed and verified by device measurements, including the influence of extensive disorder effects on transport. This is implemented in Verilog-A for evaluating the possibility of digital and RF applications with 2D-FETs.

GLOBALFOUNDRIES presents the next paper (31.5), describing a quantitative model for switching asymmetry in p-MTJs, by combining a 4×4 tunnelling conductance matrix derived using NEGF formalism, and a 4×4 ferromagnetic conductance matrix derived from the Valet-Fert equation. It provides qualitative and quantitative agreement with switching voltages in spin torque experiments observed in IBM, Everspin and GLOBALFOUNDRIES hardware data.

Session 32: Process and Manufacturing Technology – 3D Integration

32.1 is an imec-led review of the different variants of sequential 3D integration, and the potential challenges to achieve a realizable solution. The benefits observed due to sequential scaling at a die level are analyzed and quantified.

More CEA-Leti work in 32.2; they have been doing a lot of work with laser annealing and Solid Phase Epitaxy Regrowth (SPER), and now double SPER with two amorphization/recrystallization steps, which has the advantage of doping the bulk of the S/D junctions. This enables a low-temperature FinFET process to be demonstrated, with gate-last integration and self-aligned contacts; devices exhibit performances close to those of the high temperature process of reference.

We have an invited presentation from Tohoku U. next (32.3), on new materials and processes for advanced Si devices. Co contact plugs and amorphous Co-Ti barriers showed a good adhesion for MOL, with limited growth of Co silicide, and a low contact resistivity of the order of 10-9 Ωcm2 on both n+ and p+ Si. For BEOL, a CVD-MnOx layer could be formed conformally in high-aspect ratio contact holes, and an ALD-MnOx layer of 1.2 nm thick showed a good diffusion barrier property at 400 ^oC. For 3D integration, TSV of 10 μm diameter and 80 μm depth could be filled with low resistivity sintered Cu paste without voids.

32.4 is an imec study of wafer-to-wafer hybrid bonding, using SiCN in combination with Cu pads of unequal size and surface topography, formed by CMP processing, to give electrically yielding 300 mm-bonded wafers with pad pitches of 1.44 μm down to 0.72 μm.

Liquid jet impingement cooling of high power devices is considered in 32.5, again by imec, using a 3D-shaped polymer cooler.

 

Session 33: Power Devices – Development of GaN Power Devices Technologies

TSMC has a smart GaN power platform (33.1), with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, and the 2nd level integration has high-low side on-chip integration on a 100 V technology platform.

33.2 is a study of reverse-bias stability and reliability of hole-barrier-free E-mode LPCVD-SiNx/GaN MIS-FETs. With limited hole-generation, the devices deliver small NBTI values, even without a hole-barrier. In reverse-bias stress, the SiNx gate dielectric, while exhibiting a negative valance-band-offset with GaN, acts as a plug to holes, and hole-induced degradation can be greatly contained by limiting gate-bias to a few volts below VTH.

Toshiba details improved GaN MOSFETs (33.3) with drastically suppressed positive bias temperature instability (PBTI), by reducing impurity densities in the SiO₂ gate dielectric; they were controlled by heat treatment after dielectric deposition.

Defect bands are found in carbon-doped GaN (33.4); these layers, crucial for GaN HEMT buffers, show non-Arrhenius thermal behavior of capacitance transients related to the trapping/detrapping dynamics of leakage current in a wide temperature range. The model developed indicates that conduction via defect band controls both processes, redefining the way III-N:C containing layers should be investigated.

Proton irradiation is used to achieve zero dynamic-Ron in GaN-based power HEMTs (33.5). The results are explained by considering that proton irradiation increases the leakage through the uid-GaN channel layer. This increases the detrapping rate, and leads to the suppression of dynamic-Ron at high VDS.

Session 34: Focus Session – Optoelectronics, Displays and Imagers – Silicon Photonics

This is the last focus session of the conference, with another five invited papers from purveyors and researchers into Si photonics. Luxtera announced partnership with TSMC in March this year, so maybe in 34.1 we’ll hear how that is going, since the topic is “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain”.

34.2 is imec’s take on the technology; “Reliable 50Gb/s Silicon Photonics Platform for Next-Generation Data Center Optical Interconnects”. Their platform claims to support single-channel data rates of 50Gb/s and above – advanced process options include 50 GHz GeSi electro-absorption modulators, and high efficiency thermo-optic phase shifters.

South of the border from imec, we have the Grenoble cluster describing their “Developments in 300mm silicon photonics using traditional CMOS fabrication methods and materials” (34.3). Japan’s Photonics Electronics Technology Research Association (PETRA) looks at “Advanced devices and packaging of Si-photonics based optical transceiver for optical interconnection” (34.4) as a way keeping system costs down – highly accurate assembly processes in optical coupling are needed, but they are not always cheap.

Lastly, NTT reviews their recent achievements in various energy-efficient nanophotonic devices based on photonic crystals (34.5). The strong light confinement of these devices enables large enhancement of light-matter interactions, and ultra-small capacitance for OE/EO conversion devices; they demonstrate that the energy consumption can be reduced down to fJ/bit or less.

 

Session 35: Modeling and Simulation – Progress in Modeling Methodology and Approaches

35.1 presents the theory, implementation and application of a new quantum transport, NEGF based modelling approach employing a full-band Empirical Pseudopotential (EP) Hamiltonian, enabling complete, self-consistent simulations for both FETs and Tunnel FETs in Si or in Ge, and with geometrical features in line with upcoming CMOS technologies.

35.2 is an invited talk discussing first-principles-based quantum transport simulations of nanoscale field effect transistors made of Ge, Si, strained-Si, and few-layer black phosphorus channels.

In a joint paper by GLOBALFOUNDRIES and Synopsys (35.3), density functional theory (DFT) is used to calculate TCAD parameters to describe dopant diffusion in Si, SiGe and Ge. The dopant profile simulated in TCAD with calculated parameters is in good agreement with experiment.

We get into the TCAD simulation of SiC CVD in 35.4, simulating trench filling for SiC super-junction devices. 35.5 studies the conductance of doped carbon nanotubes (CNTs) as a possible candidate for BEOL interconnects; circuit-level simulations predict up to 88% signal delay improvement with metal-doped vs. pristine CNT. This was validated by electrical measurements of Pt-salt doped CNTs with up to 50% of resistance reduction.

 

Session 36: Nano Device Technology — Device Technologies for Disruptive Computing

In 36.1 we look at van der Waals (vdW) heterojunctions of MoS₂ and VO₂; the sharp vdW interface enables a tunable diode-like characteristic, and this can be extended to tunable rectifiers, photodiodes and field effect transistors. The next paper (36.2) proposes and demonstrates a stochastic computing unit with a single MTJ; it can perform addition and multiplication operations and requires no additional logic gates.

In 36.3, it is shown that compact spin-torque nano-oscillators can form sub-micron neurons; and that they can naturally implement reservoir computing with high performance, and detail the recipes for this capability.

A STDP synapse with outstanding stability based on a novel insulator-to-metal transition FET is detailed in 36.4, based on a gate-controlled insulator-to-metal- transition FET. Since a metallic channel is used, stochastic phenomena have little effect, giving high stability with a large dynamic range and very low power consumption.

The last paper (36.5) demonstrates a CMOS-compatible double quantum dot spin qubit that is all-electrically controlled without the need for external components such as micromagnets, that could complicate integration. Universal control of the qubit is achieved through spin-orbit-like and exchange interactions. Using single shot readout, we show both DC- and AC-control techniques.

 

Session 37: Process and Manufacturing Technology — Advanced Transistor Technologies

37.1 is a study of 5-nm-thick ferroelectric Y-doped HfO₂ on p+ Ge; the investigation indicates that stable ferroelectric characteristics are maintained down to 5 nm by controlling doping and capping effects. The cycling performance showed no wake-up behavior, and no obvious degradation after 108 cycles.

In 37.2 IBM/GLOBALFOUNDRIES studied the relative impacts of germanium content vs. strain on the performance of SiGe channels in strained SiGe p-FinFETs and planar devices on a strain-relaxed buffer (SRB) substrate. Last year GF/IBM/Samsung gave a paper on a SRB-based 7-nm process [2], and we looked at it in a follow-up blog.

This looks like further work to set some more parameters; the devices had different strain configurations, Ge channel compositions and surface properties. The inclusion of planar devices likely provides a baseline, but also may have useful data for the FDSOI processes at GF (no mention of FDSOI in the abstract). The fin shape is more rectangular than in last year’s paper – is the process evolving that way?

By comparing the transistor electrical properties of SiGe pFETs on SRB with those on Si substrate, the influence of strain and Ge content in the channel on device performance is decoupled from factors such as gate stack quality, reliability, and carrier transport.

The authors found that, independent of strain, increasing Ge content led to unstable gate stacks with greater interface trap charges and relatively low hole mobility, although it improves NBTI reliability. Carrier transport is predominantly controlled by the channel strain, and a (100) substrate crystal orientation helps optimize the effects of strain for both n- and p-FinFETs.

37.3 is an invited IBM talk on gate-stack engineering for gate-first and RMG transistors, so again keeping consideration of FDSOI applications. Key process details are disclosed to achieve optimized devices with near-ideal SS, excellent NBTI, mobility and transconductance at scaled-EOTs. Aggressively-scaled fins with W_FIN=6.4nm and excellent short-channel characteristics are also demonstrated.

imec/Applied Materials claim the first circuit built with Si nanowire transistors in 37.4 . They built functional ring oscillator test circuits using stacked Si NWFETs, with devices that featured in-situ doped source/drain structures and dual-work-function metal gates. A SiN STI liner was used to suppress fin deformation and improve shape control; a high-selectivity etch was used for nanowire/nanosheet release and inner spacer cavity formation, with no silicon reflow; and a new metallization process for n-type devices led to greater tunability of threshold voltage.

National Taiwan University also claims a first in 37.5, this time the first stacked GeSn pGAA-FETs. Good crystalline quality is achieved from CVD-grown stacked GeSn layers. Using Ge barriers as sacrificial layers and an ultrasonic-assisted hydrogen peroxide etching technique, the GeSn 60 nm channel has record high Ion of 1850 uA/um, with SS=88 mV/dec.

 

Session 38: Memory Technology — STT-MRAM

Avalanche Technology seems to have been in stealth mode, but in 38.1 they present a bi-directional threshold switching selector and integrated one selector/one perpendicular MTJ (1S1R) device. The selector shows an On/Off ratio above 1E+7, 1 pA leakage current, 0.3 V threshold voltage, and fast speed (10 ns).

Next up is an invited review by Seung Kang of Qualcomm; “MRAM: Enabling a Sustainable Device for Pervasive System Architectures and Applications” (38.2)

With its unique attributes and tunability, MRAM is poised to become a unified memory subsystem that can revamp the architectures of emerging ultra-low-energy systems, and has potential to transform computing-centric architectures at advanced nodes.

IBM and Samsung give a joint paper (38.3) on the impact of four key parameters on the switching efficiency of STT-MRAM devices with perpendicular magnetic anisotropy (p-MTJ): device size, device resistance-area product, blanket film Gilbert damping constant (α), and process temperature. Optimization of the p-MTJ materials eliminated the performance degradation observed in 400ºC-processed devices. Additionally, 400ºC-compatible double MTJs showed 1.5x improvement in switching efficiency compared to single MTJs with identical free layers.

In 38.4 TDK- Headway Technologies takes their expertise in magnetic analysis (they make magnetic recording heads) to probe the magnetic properties of STT-MRAM devices down to sub-20 nm using spin-torque ferro-magnetic resonance (ST-FMR).

Measurements of the anisotropy field (Hk) of devices down to 20 nm using ST-FMR are reported, and it is shown that Hk increases for decreasing sizes. Using micromagnetic simulations, they developed a simple model to fit Hk size dependence, allowing the quantification of magnetic edge damage for various process conditions.

Etching magnetic tunnel junction (MTJ) cells at small dimensions and very dense pitch is still challenging for high density STT-MRAM. This paper (38.5) avoids MTJ etching, and demonstrates MTJ nano-patterning at very narrow pitch (pitch=1.5F, F=MTJ dot diameter) by growing the MTJ material on pre-patterned conducting non-magnetic pillars without post-deposition etching.

38.6 also describes 400°C-compatible p-MTJ stacks; top-pinned stacks with a new synthetic ferromagnetic stack pinning layer design is used to demonstrate free layer off-set control and low current switching in 30nm CD devices.

 

Session 39: Characterization, Reliability and Yield — Advanced Reliability Characterization and Circuits

In paper 39.1, a set of two- and three-dimensional analysis techniques are combined to clarify the switching and failure modes of resistive switching in state-of-the-art TiO₂-based vacancy modulated conductive oxide memory. 39.2 examines ultra-fast (<1 ns) electrical characterization of the self-heating effect and its impact on hot-carrier injection in 14nm finFETs, capturing the heat generation and dissipation process in the transistor channel.

Now that 14nm is a mature process, U. Minnesota/Intel are characterizing soft error rates (SER) in combinational logic gates (39.3), using a NAND/NOR readout chain. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data, capturing the impact of various circuit parameters on SER.

In 39.4 the statistical behaviors of read current noise and retention in a 1Kb filamentary analog RRAM array are investigated. The conductance distribution of different levels is found to change with time, and the physical mechanism of this retention degradation is explained. From the experimental data, a compact model is developed in order to predict the statistical conductance evolution, which can effectively evaluate the impact of read noise and retention degradation in neuromorphic computing systems.

The last paper (39.5) is an invited presentation from Carnegie Mellon U., on “Combatting IC Counterfeiting Using Secure Chip Odometers”. The odometers employ chained one-shot binary aging elements that use intentional accelerated device aging to measure the use and age of the chip. A prototype secure odometer was taped out on a 1.2mm x 1.7mm test chip in a 65nm bulk CMOS process as a proof-of-concept.

 

Session 40: Sensors, MEMS, BioMEMS — MEMS for Internet-of-Things (IoT)

High-Q silicon fin bulk acoustic resonators (finBARs) are described in 40.1; high-aspect-ratio fins are etched in the silicon substrate and covered by aluminum nitride films to enable efficient electromechanical transduction of bulk acoustic resonance modes with large coupling coefficient (kt2), resulting in unprecedentedly high quality-factors (Q) in ultra- and super-high- frequency (SHF) regimes.

A monolithically 3D-printed pressure sensor with excellent sensing performance was demonstrated (40.2). The porous-structured dielectric was formed by casting an elastomer prepolymer into 3D-printed water-soluble templates. The flexible electrodes were monolithically 3D-printed using a conductive thermoplastic as well. Finally, the sensors were applied to the e-skin and wearable healthcare monitoring system.

A triboelectric nanogenerator (TENG) composed of porous conductive-polymer and PTFE wrapping wires, is detailed in 40.3. The TENG generated a short-circuit current for a long duration and great output performance. A model based on parallel connection of the finite capacitors was developed, and validated by comparison between experiment and calculated results.

In 40.4 a self-powered broadband (20 Hz ~ 2000 Hz) electromagnetic-induced vibration sensor, a remote temperature sensor, and a first stage read-out circuit MEMS, are integrated heterogeneously in compact packaging.

40.5 describes a refractive index sensor formed from aluminum nanohole arrays on vertical Ge PIN photodiodes; the interaction of plasmonic resonances and thin-film reflection within the PIN layer stack enables sensitivities comparable to Au sensing systems showing FOM* up to 14.
Chronologically the last paper is due at 3.40 pm – by then a lot of attendees will have headed for home, especially West-coasters who want to get home today.

I will definitely be suffering from information overload and becoming brain-numb, but with 228 papers and an average of seven parallel sessions at any one time, plus the offsite events, that’s not really surprising. On the other hand, where else do we go to get all this amazing stuff?

Time to unwind, maybe do a little holiday shopping, and go for an indulgent meal.

 

Reference

• -H. Jan et al., “A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra Low Power, High Performance and High Density SoC Applications”, IEDM 2012, pp. 44 – 47.
• Xie et al., “A 7nm FinFET Technology Featuring EUV Patterning and Dual Strained High Mobility Channels”, IEDM2016, pp. 47 – 50