By Dick James, Senior Technology Analyst, Chipworks
It’s spring in the north-eastern part of North America, and that means it’s the time of year for the Advanced Semiconductor Manufacturing Conference, in the amiable ambiance of Saratoga Springs, New York. The conference took place a couple of weeks ago, on May 16 – 19.
As the name says, ASMC is an annual conference focused on the manufacturing of semiconductor devices; in this it differs from other conferences, since the emphasis is on what goes on in the wafer fab, not the R&D labs, and the papers are not research papers – some are better described as “tales from the fab”! After all, it’s the nitty-gritty of manufacturing in the fab that gets the chips out of the door, and this meeting discusses the work that pushes the yield and volumes up and keeps them there.
I always come away impressed by the quality of the engineering involved; not being a fab person myself any more, it’s easy to get disconnected from the density of effort required to equip a fab, keep it running and bring new products/processes into production. Usually the guys in the fab only get publicity if something goes wrong!
There were 96 papers spread over the three days, 60 presentations and 36 posters, and the highest attendance ever at 350+ (registration was actually closed on day 1 – we ran out of room!). In addition we had keynotes from Don O’Toole of IBM and Christine Furstoss of GE Global Research, a tutorial on Nanoscale III-V CMOS by Jesús del Alamo from MIT, and to finish the Wednesday afternoon there was a panel discussion on “Moore’s Law Wall vs. Moore’s Wallet, and Where Do We Grow From Here?”. Bob Maire of Semiconductor Advisors wrapped up the conference Thursday lunchtime with a talk on China’s effect on the semiconductor biz; “Mergers & Acquisitions in the Semiconductor Industry – Could China Cause Continued Consolidation?”
I guess it’s a reflection of the location, but 46 out of the 96 papers were from Silicon on the Hudson – GLOBALFOUNDRIES, IBM, and CNSE/G450 affiliates. Having said that, there were papers from the likes of Samsung, TSMC, and UMC, not to mention NXP, Infineon, ON Semi, and others, plus some academic and student papers. It’s always tough to get papers from far afield these days, especially with tightening travel budgets and visa requirements, not to mention the gut desire to keep internal information in-house.
And of course Chipworks usually has an offering, though we missed out last year due to personal circumstances, otherwise it would be twelve years in a row. It’s a bit of an odd fit, since we are a service company that doesn’t make anything; but we do take the leading edge chips apart, and it seems the fab guys at the conference like seeing the competition’s stuff – and their own – since, if you’re deep into running the fab, you don’t get much of a chance to look at the final product.
And, now that we’ve been presenting since 2005, our papers are actually a condensed history of the technology from the 90-nm era down to 14-nm finFETs – if you read the references at the end of the blog you’ll see we’ve covered a fair spread of technology, not just logic transistors, but also flash and DRAM memory.
The initial reason for my submitting a paper back in 2004 for the 2005 conference was that ASMC that year was co-located with Semicon Europa – and I liked the idea of a trip to Munich! We were also a growing company, and starting to flex some of our marketing muscles by presenting at, rather than just attending conferences. In that context, the 2005 conference was a success, since Tom Cheyney, editor of the now-defunct Micro magazine, invited me to write regular articles for the publication, and that led to a series of articles and blogs that is still going.
Looking back at the older presentations, they really are a trip down memory lane – remember that first Intel 90-nm transistor with embedded silicon-germanium source/drains for the PMOS? We looked at that in 2005 .
The compressive stress given by the SiGe turned out to be a very effective tool for cranking up the strain in the channel, to the extent that PMOS and NMOS drive currents are now comparable, definitely a different design paradigm from the days of my youth.
And it turned out that the technology was transferable to high-k, metal-gate (HKMG) finFETs – witness the latest 14-nm Intel PMOS device:
Taking a different tack, IBM was already using SOI, but before they used embedded stress techniques, the SOI layer was only 45 nm thick – not quite FDSOI, but thinner than their current (GLOBALFOUNDRIES) HKMG offering that uses 80-nm thick SOI.
As you can see below, things are considerably more complex these days!
When it comes to memory, 90-nm DRAM was the order of the day, and the recessed channel array transistor (RCAT) had just been introduced:
Now we have 10-nm class (likely 18-nm) 8-Gb DRAMs, though the latest I reviewed at ASMC  was a 26-nm 4-Gb part in 2013 – that was three generations ago!
In the meantime we have seen the introduction of buried tungsten saddle-fin transistors for the wordlines (buried wordlines – BWL), ZAZ (zirconia/alumina/zirconia) high-k capacitor dielectrics, and air-gaps; shrinking cell area by more than a factor of ten. The node definition has also moved from half the M1 pitch to half of the active silicon pitch, nothing stays the same in our business.
I didn’t talk about flash that first year, but a couple of years later  the leading edge was a 62-nm, 8-Gb part, and 50-nm was starting to come into production. The conference that year was in Stresa, on Lake Maggiore in Italy, one of the more exotic locations that we’ve been to.
The latest in planar flash in 2013  was a 19-nm Toshiba 128-Gb device:
We still have the conventional floating gate/control gate structure, but cell size has shrunk by an order of magnitude, we have air gaps between cells, and in order to keep effective coupling between control gate and floating gate, the aspect ratio of the floating gate has increased from ~1.3 to ~4.8.
In 2016, of course, we have planar flash down to the 15-nm generation, including the use of high-k dielectric, and we are into the third-generation vertical flash parts.
So much for then and now – this year’s conference had 15 different sessions:
- Contamination Free Manufacturing (CFM)
- Advanced Metrology I & II
- Defect Inspection I & II
- Factory Optimization I & II
- Advanced Equipment and Materials Processes
- Yield Enhancement & Yield Learning
- Advanced Equipment/CFM
- Advanced Patterning/CFM
- Advanced Process Control (APC)
- Yield Enhancement
- 3D TSV
Including a poster session for shorter papers that covered all the above topics.
The subjects of individual papers ranged from improvements to chemical-mechanical planarization, through threshold voltage variations in HKMG gates due to non-uniform alloying, to ‘smart manufacturing’ in legacy 200mm fabs, and multiple papers on virtual metrology – i.e. a broad swath of the practical wafer manufacturing problems to fab loading algorithms and everything in between. The detailed schedule can be found here, and no doubt the proceedings will be available through IEEE Xplore in due course.
Next year’s ASMC will again be in Saratoga Springs, on May 15 – 18; we hope to see you there!
- James, 2004 – The Year of 90-nm: A Review of 90 nm Devices, Proc. ASMC 2005
- James, Low-K and Interconnect Stacks – a Status Report, Proc. ASMC 2006
- James, Nano-Scale Flash in the Mid-Decade, Proc. ASMC 2007
- James, From Strain to High K/Metal Gate – the 65/45 nm Transition, Proc. ASMC 2008
- James, Design-for-Manufacturing Features in Nanometer Processes – A Reverse Engineering Perspective, Proc. ASMC 2009
- James, Recent Innovations in DRAM Manufacturing, Proc. ASMC 2010
- Fontaine, Recent Innovations in CMOS Image Sensors, Proc. ASMC 2011
- James, High-k/Metal Gates in Leading Edge Silicon Devices, Proc. ASMC 2012
- James, Recent Advances in Memory Technology, Proc. ASMC 2013
- James, 3D ICs in the Real World, Proc. ASMC 2014
- James, High-k/Metal Gates in the 2010s, Proc. ASMC 2014
- James, Moore’s Law Continues into the 1x-nm Era, Proc. ASMC 2016