Back in 2005 Samsung made an announcement that they would be shipping eight die stacked in the same package. At the time it seemed remarkable, but we didn’t see it any time soon after that, so it got lost in the noise of other package developments and the increasing TSV (through-silicon vias) hype.

Last year we commented, in the now defunct Semiconductor International, on a 16GB Sandisk Micro-SD flash card that had nine die stacked together, thinned to a remarkable 30 µm each.

Now Samsung have delivered, in the new iPhone; our 32-GB version had one Samsung flash part within, a K9PFG08U5M (below), which their part number decoder reveals as a 256 Gb MLC (multi-level cell) NAND flash device.

One digit decodes as ‘ODP’, which isn’t clarified, but once the chip was taken off the board and x-rayed, we could see eight dies, so octal-die package seems to work. It doesn’t show up too well in plan-view, but a side-view x-ray makes it clear enough:

So, having seen the x-ray, I asked one of our lab guys to see if he could section one of the wire bond stacks that we can see in the above image. The bonds at opposite ends of the package aren’t in the same plane, so we can only get one set of bonds, but to me he did a pretty good job.

The package, including substrate, is ~0.93 mm thick, and the die stack is ~670 µm high. Die thicknesses vary from 55 – 70 µm, with the thickest die at the bottom. Thinner than the 1.4 mm announced in 2005, and not quite the 0.6 mm quoted in last year’s ‘ultra-thin’ release, but impressive nonetheless.

What surprised me, when I looked closely at the section, was how close to the top surface the top wirebond loop is – that’s 25-µm wire, so it looks to be less than 10 µm from surface – that’s minimising encapsulant for sure!

Every time we tear down something like the iPhone, it is clear that it’s not only the chip technology that makes these toys possible; they wouldn’t be the same without the parallel developments from the TAP part of the business, not to mention the software.

Still, as with the Sandisk, it poses the question: If we can build stacks of dies like this with wire bonding, will through-silicon vias ever become economic in the commodity chip arena?

Before Qimonda’s unfortunate demise last year, they delivered an impressive paper at IEDM 2008 [1] describing a “buried wordline” (BwL) DRAM stack-cell structure. This was a marked change from their earlier technology, as until this point all of their product had been based on planar wordline structure with trench-style storage capacitors sunk into the die substrate.

Even when we compare BwL-stack with conventional stack DRAM structures, there’s a major shift, because the buried wordline uses a tungsten metal-gate transistor – the first metal-gate transistor since the aluminum-gate days of the early ‘70s!

The Qimonda slide below shows the difference in structure; on the left is the buried wordline (in red), sunk into the substrate silicon, and on the right is an oriental competitor using a spherical recess-channel transistor (with the tungsten part of the gate highlighted in red).

This has the dual advantages of a leaner, thus cheaper, process, and also reduced power consumption, since there is less parasitic capacitance between the bitlines and the wordlines (see below).

We weren’t entirely sure that we had the BwL process when we got the Winbond 1-Gb DDR2 SDRAM parts, but the first cross-section we did in our analysis cleared that up – the white dots below the capacitor stack are the buried wordlines.

The TEM shot below shows them in close-up – you can also see that the bitlines are a W/TiN/polySi stack, also used as a gate conductor in the peripheral transistors.

Winbond’s new SDRAMs are not only a really cool, step-function change in technology, they are also unique as a volume production part – no-one else is making them at the moment. And they are in volume production, we have also found them in a point and shoot camera. Winbond has introduced the technology at the 65-nm node, but they also have 46-nm parts under development.
One other point was made by Qimonda before they went under, that this technology is particularly suitable for a cell shrink from the current 6F2 to a 4F2 format, enabling even more cost savings by reducing die size.

Elpida has also licensed the process, so given the cost and performance advantages, we can likely look forward to BwL product from Japan; and who knows what other manufacturers might go that way?

[1] T. Schloesser et al., “A 6F2 Buried Wordline DRAM Cell for 40nm and Beyond” , Proc IEDM 2008, pp. 809-812