Tag Archives: manufacturing

Cross-point ReRAM Integration Claimed by Intel/Micron

The Intel/Micron joint-venture now claims to have successfully integrated a Resistive-RAM (ReRAM) made with an unannounced material in a cross-point architecture, switching using an undisclosed mechanism. Pilot production wafers are supposed to be moving through the Lehi fab, and samples to customers are promised by end of this year.
HP Labs announced great results in 2010 on prototype ReRAM using titania without the need for a forming step, and then licensed the technology to Hynix with plans to bring a cross-point ReRAM to market by 2013. SanDisk/Toshiba have been working on ReRAM as an eventual replacement for NAND Flash for many years, with though a bi-layer 32Gb cross-point ReRAM was shown at ISSCC in 2013 they have so far not announced production.
Let us hope that the folks in Lehi have succeeded where HP/Hynix and SanDisk/Toshiba among others have so far failed in bringing a cross-point ReRAM to market…so this may be a “breakthrough” but it’s by no means “revolutionary.” Until the Intel/Micron legal teams decide that they can disclose what material is changing resistance and by what mechanism (including whether an electrical “forming” step is needed), the best we can do is speculate as to even how much of a breakthrough this represents.
—E.K.

Batteries? We don’t need no stinking batteries.

We’re still used to thinking that low-power chips for “mobile” or “Internet-of-Things (IoT)” applications will be battery powered…but the near ubiquity of lithium-ion cells powering batteries could be threatened by capacitors and energy-harvesting circuits connected to photovoltaic/thermoelectric/piezoelectric micro-power sources. At ISSCC2015 in San Francisco last week, there were several presentations on novel chip designs that run on mere milliWatts (µW) of power, and the most energy efficient circuit blocks now target nanoWatt (nW) levels of power consumption. Two presentations covered nW-scale microprocessor designs based on the ARM Cortex-M0+ core, and a 500nW energy-harvesting interface based on a DC-DC converter operating from 1µm available power was shown by a team from Holst Centre/imec/KU Leuven working with industrial partner OMRON.

Read more on this in MicroWatt Chips shown at ISSCC available at SemiMD.

—E.K.

Oscar for DMD Inventor Hornbeck

Texas Instrument Oscars 1Kudos to Dr. Larry J. Hornbeck, the extended team at Texas Instruments (TI) that has worked on Digital Micromirror Device (DMD) technology, and to the TI executives who continued to fund the R&D through years of initial investment losses. Hornbeck has been awarded an Academy Award® of Merit (Oscar® statuette) for his contribution to revolutionizing how motion pictures are created, distributed, and viewed using DMD technology (branded as the DLP® chip for DLP Cinema® display technology from TI).

The technology now powers more than eight out of 10 digital movie theatre screens globally. Produced with different resolutions and packages, DLP chips also see use in personal electronics, industrial, and automotive markets. The present good-times with DMD are enjoyed only because TI was willing to make a major long-term bet on this novel way to modulate pixel-arrays, which required building the most complex Micro-Electro-Mechanical System (MEMS) the world had ever seen.

Development of the DLP chip began in TI’s Central Research Laboratories in 1977 when Hornbeck first created an array of “deformable mirrors” controlled with analog circuits. In 1987 he invented the DMD, and TI invested in developing multiple money-losing generations of the technology over the next 12 years. Finally, in 1999 the first full-length motion picture was shown with DLP Cinema technology, and since then TI claims that the technology has been installed in more than 118,000 theaters around the globe. We understand that TI now makes a nice profit from each chip.

“It’s wonderful to be recognized by the Academy. Following the initial inventions that defined the core technology, I was fortunate to work with a team of brilliant Texas Instruments engineers to turn the first DMD into a disruptive innovation,” said Hornbeck, who has 34 U.S. patents for his groundbreaking work in DMD technology. “Clearly, the early and continuing development of innovative digital cinema technologies by the DLP Cinema team created a definitive advancement in the motion picture industry beyond anyone’s wildest dreams.”

—E.K.

Micro-Buckled 3D Silicon Scaffolds

3Dsilicon_CompressiveBucklingA new silicon microstructural solution announced this month is so powerful in creating 3D patterns from 2D surface machining that I just have to share. The figure shows 3D silicon microstructures formed by compressive buckling. The method can be used to create objects with features as small as 100 nm that could be useful for developing new technologies for medicine, energy storage and even brain-like electronic networks. Note that the silicon is surface-machined using standard MEMS processes, and that all manner of silicon circuitry and thin-film sensors could be integrated into this silicon.

Colleagues from the University of Illinois at Urbana-Champaign, Northwestern University, Zhejiang University, East China University of Science and Technology, and Hanyang University created the new 2D-to-3D fabrication technique. Their trick is that after all other surface machining they chemically modify the square anchors in the surface pattern such that they are sticky. After the 2D pattern is released it is transferred onto a sheet of stretched silicone rubber. Allowing the rubber to relax back to its natural shape draws the squares toward each other, while the rest of the silicon buckles upwards. Using this type of controlled buckling, the team managed to produce a variety of elaborate 3D shapes.

The researchers even produced structures with multiple levels of elevation by designing shapes in which the relief of stress in the initial 2D shape would create further buckling, raising another part of the shape further. John Rogers of the University of Illinois at Urbana-Champaign, who is part of the micro-buckling team looks forward to an electronic cell or tissue scaffold, “A lot of the people that we talk to are enthusiastic about what you can do when you go from a passive scaffold to something that embeds full electronic functionality.”

The research is published in Science.

—E.K.

ASML Books Production EUV Orders

TSMC commits to two tools for delivery next year

Maybe, just maybe, ASML Holding N.V. (ASML) has made the near-impossible a reality by creating a cost-effective Extreme Ultra-Violet (EUV @ ~13.5nm wavelength) all-reflective lithographic tool. The company has announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance. While costs and throughputs are conspicuously not-mentioned, this is still an important step for the industry.
Perhaps acquiring Cymer to get the source-technology in-house for tighter integration was important. Perhaps evolutionary improvements crept along by tough engineering rigor. Perhaps the industry got lucky. One way or the other, ASML has had the goal of delivering not just hardware but functional uptime/availability using very complex EUV technology, and now it seems to be on the cusp of making it happen. The company claims that current EUV tools are available 50% of the time, at unspecified source power levels.
At its Investor Day in London today, ASML outlined its expected opportunity to grow net sales to about EUR 10 billion and to triple earnings per share by 2020, an indication of the confidence the company has in its technology and employees. Much of the growth will be in Deep-UV immersion tools, and in so-called “Holistic Lithography” products to deliver advanced correction capabilities. An example of Holistic Litho is Source-Mask-Optimization (SMO) that can be used for triple-patterning of a 48nm minimum pitch metal layer using DUV immersion in a Litho-Etch-Litho-Etch-Litho-Etch (LELELE) flow, such that the Depth-of-Focus (DoF) can be increased from 70 to 86nm. Holistic EUV means that SMO can reduce the dose required to get 120nm DoF from 46 to 20 mJ/cm2 for a 45nm minimum pitch metal layer.
The presentations can be found at the company’s website.
— E. K.

Nakamura Co-Wins Nobel for Blue LEDs

The Nobel Prize in Physics 2014 was awarded jointly to Isamu Akasaki, Hiroshi Amano, and Shuji Nakamura “for the invention of efficient blue light-emitting diodes which has enabled bright and energy-saving white light sources”. In the late 1980s red and green LEDs had been around for decades, but despite large programs in both academia and industry there had been almost no R&D progress in blue LEDs (this editor did process R&D in an LED fab in that era). Then Akasaki and Amano at the University of Nagoya showed work on improved p-doping in GaN due to electron irradiance, leading to p-n junctions to make diodes.

Structure of a blue LED with a InGaN/AlGaN double heterojunction [Source: S. Nakamura, T. Mukai & M. Senoh, Appl. Phys. Lett. 64, 1687 (1994)].

Structure of a blue LED with a InGaN/AlGaN double heterojunction (Source: S. Nakamura, T. Mukai & M. Senoh, Appl. Phys. Lett. 64, V1687, 1994).

From 1989 to 1994, Shuji Nakamura worked at Nichia Chemicals in Tokushima, Japan where he led a small team of co-workers to achieve a quantum efficiency of 2.7% using a double heterojunction InGaN/AlGaN (see Figure). With these important first steps, the path was cleared towards the development of efficient blue LEDs and solid-state white lighting. Nakamura-sensei is now a Professor of Physics at the University of California, Santa Barbara, and co-founder of Soora Corp. where GaN-on-GaN technology is used to increase efficiency through the elimination of the buffer-layers needed with saphhire substrates. The “Tales of Nakamura” article at IEEE Spectrum provides an excellent summary of this extraordinary man’s life story, including the US$600M payout from Nichia that was reduced to US$8M by a higher court.
Incandescent light bulbs lit the 20th century; the 21st century will be lit by LED lamps with high lm/W efficiency. The most recent record is just over 300 lm/W, which can be compared to 16 for regular light bulbs and close to 70 for fluorescent lamps. As about one fourth of world electricity consumption is used for lighting purposes, the LEDs contribute to saving the Earth’s resources.
Shine on!
—E.K.

IBM Shows Graphene as Epi Template

Last month in Nature Communications (doi:10.1038/ncomms5836) IBM researchers Jeehwan Kim, et al. published “Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene.” They show the ability to grow sheets of graphene on the surface of 100mm-diameter SiC wafers, the further abilitity to grow epitaxial single-crystalline films such as 2.5-μm-thick GaN on the graphene, the even greater ability to then transfer the grown GaN film to any arbitrary substrate, and the complete proof-of-manufacturing-concept of using this to make blue LEDs.

(Source: IBM)

(Source: IBM)

The figure above shows the basic process flow. The graphenized-SiC wafer can be re-used to grow additional transferrable epi layers. This could certainly lead to competition for the Leti/Soitec/ST “SmartCut” approach to layer-transfer using hydrogen implants into epi layers.
No mention is made of the kinetics of growing 100mm-diameter sheets of single-crystalline GaN on graphene. Supplemental information in the online article mentions 1 hour at 1250°C to cover the full wafer, but the thickness grown in that time is not mentioned. From first principles of materials engineering, they must either:

A) Go slow at first to avoid independent islands growing to form a multicrystalline layer, or
B) Initially grow a multicrystalline layer and then zone anneal (perhaps using a scanned laser) to transform it into a single-crystal.
In either case, we would expect that after just a few single-crystalline atomic layers had been either slowly grown or annealed, that a 2nd much-higher speed epi process would be used to grow the remain microns of material. More details can be seen in the EETimes write up.
—E.K.

Chasing IC Yield when Every Atom Counts

Increasing fab costs coming for inspection and metrology
ITRS2013_Yield_overviewAt SEMICON West this year in Thursday morning’s Yield Breakfast sponsored by Entegris, top executives from Qualcomm, GlobalFoundries, and Applied Materials discussed the challenges to achieving profitable fab yield for atomic-scale devices (Figure source is the ITRS 2013 Yield Chapter). Due to the sensitive nature of the topic, recording was not allowed and copies of the presentations could not be shared.
Qualcomm – Geoffrey Yu
Double-patterning will be needed for metal and via layers as we go before 90nm pitch for the next generations of ICs. Qualcomm is committed to designing IC with smaller features, but not all companies may need to do so. Fab costs keep going up for atomic-scale devices…and there are tough trade-offs that must be made, including possibly relaxing reliability requirements. “Depending on the region. If you’re in an emerging region maybe the reliability requirements won’t be as high,” said Yu. Through-Silicon Vias (TSV) will eventually be used to stack IC layers, but they add cost and will only be used when performance cannot be met with cheaper solutions. “An early idea was to use TSV for logic:memory,” reminded Yu, “but then there was innovation to LPDDR4 allowing it deliver the same bandwidth with one-half the power of LPDDR3, which delayed TSV.”
GlobalFoundries – Harry Levenson
“A more expensive part could provide a better value proposition for a customer,” reminded Levenson as he discussed the challenges of inspecting next-generation commercial ICs in high-volume manufacturing (HVM). “We still have clear demand for products to run in HVM at the leading edge, but we are now in the world of double-patterning and this applies to optical inspection as well as imaging.” Requirements for inspection and imaging are different, but he same physics applies. In imaging Depth of Focus (DoF) of ~140nm is generally preferred, while the same used for inspection  of a <140nm thin film would to induce noise from lower-levels. We can’t do e-beam inspections due to too much energy concentration needed to get acceptable throughput (and the challenge gets worse as the pixel area is reduced, inherently slowing down throughput). However, e-beams are helpful because they can detect open contracts/vias in metal levels due to the conductivity of electrons providing additional contrast compared to any possible optical inspection.
Applied Materials – Sanjiv Mittal
Mittal discussed how the CMOS transistor gate formation process has increased in complexity over the last few device generations:  8x more unit-process steps, 3x higher fab cost, 50x lower defects needed for yield. “The challenges are immense,” admitted Mittal. “What happens when you try to work on yield improvement when you’re ramping volume? At the same time you’re trying to improve yield by making changes, you’re trying to increase the volume by not making changes.”
Entegris – Jim O’Neill
O’Neill is CTO of the combined Entegris post-merger with ATMI, and was recently director of advanced process R&D for IBM. Since Entegris provides materials and sub-systems, in the simplest cases the company works to improve IC fab yield by minimizing defects. “However, the role of the materials-supplier should change,” averred O’Neill. “The industry needs bottle-to-nozzle wet chemistry solutions, and applications-based clean gas delivery.” In an exclusive interview with SST/SemiMD, O’Neill provided as example of a ‘wetted process solution’ a post-CMP-clean optimized through tuning of the brush polymer composition with the cleaning chemistry.
ITRS Difficult Challenges for Yield 2013-2020

  • Existing techniques trade-off throughput for sensitivity, but at expected defect levels, both throughput and sensitivity are necessary for statistical validity.
  • Reduction of inspection costs and increase of throughput is crucial in view of CoO.
  • Detection of line roughness due to process variation.
  • Electrical and physical failure analysis for killer defects at high capture rate, high throughput and high precision.
  • Reduction of background noise from detection units and samples to improve the sensitivity of systems.
  • Improvement of signal to noise ratio to delineate defect from process variation.
  • Where does process variation stop and defect start?

—E.K.

Moore’s Law is Dead – (Part 4) Why?

We forgot Moore merely meant that IC performance would always improve (Part 4 of 4)

IC marketing must convince customers to design ICs into electronic products. In 1965, when Gordon Moore first told the world that IC component counts would double in each new product generation, the main competition for ICs was discrete chips. Moore needed a marketing tool to convince early customers to commit to using ICs, and the best measure of an IC was simply the component count. When Moore updated his “Law” in 1975 (see Part 1 of this series for more details), ICs had clearly won the battle with discretes for logic and memory functions, but most designs still had only single-digit thousands of transistors so increases in the raw counts still conveyed the idea of better chips.

MooresLaw_1965_graphFor almost 50 years, “Moore’s Law” doubling of component counts was a reasonable proxy for better ICs. Also, if we look at Moore’s original graph from 1965 (right), we see that for a given manufacturing technology generation there is a minimal cost/component at a certain component count. “What`s driven the industry is lower cost,” said Moore in 1997. “The cost of electronics has gone down over a million-fold in this time period, probably ten million-fold, actually. While these other things are important, to me the cost is what has made the technology pervasive.”

Fast forward to today, and we have millions of transistors working in combinations of “standard cell” blocks of pre-defined functionalities at low cost. Graphics Processor Units (GPU) and other Application Specific Integrated Circuits (ASIC) take advantage of billions of components to provide powerful functionalities at low cost. Better ICs today are measured not by mere component counts, but by performance metrics such as graphics rendering speed or FLOPS.

The limits of lithography (detailed in Part 2 of this blog series) mean that further density improvements will be progressively more expensive, and the atomic limits of physical reality (detailed in Part 3) impose a hard-stop on density at ~1000x of today’s leading-edge ICs. “If we say we can`t improve the density anymore because we run up against all these limitations, then we lose that factor and we`re left with increasing the die size,” said Moore in 1997.

Since the cost of an IC is proportional to the die size, and since the cost/area of lithographic patterning is not decreasing with tighter design-rules, increasing the die size will almost certainly increase cost proportionally. We may not need larger dice with more transistors, however, as future markets for ICs may be better served by the same number of transistors integrated with new functionalities.

International R&D center IMEC knows as well as any organization the challenges of pushing lithography and junction-formation and ohmic contacts to atomic limits. In the 2014 Imec Technology Forum, held the first week of June in Brussels, president and chief executive officer Luc Van den hove’s keynote address focused on the applications of ICs into communications, energy, health-care, security, and transportation applications.

TI has been making ICs since they were co-invented by Kilby in 1959, and over a decade ago TI made a conscious decision to stop chasing ever-smaller digital. First it outsourced digital chip fabrication to foundries, and in 2012 began retiring digital communications chips. Without continually shrinking components, how has TI managed to survive? By focusing on design and integration of analog components, in the most recent financial quarter the company posted 58% gross margin on $3.29B in sales.

At The ConFab last month, Dr. Gary Patton, vice president, semiconductor research and development center at IBM, said there is a bright future in microelectronics (as documented at Pete’s Posts blog).

The commercial semiconductor manufacturing industry will see only continued revenue growth in the future. We will process more area of silicon ICs each year, in support of shipping an ever increasing number of chips worldwide. More fabs will be built needing more tools and an increasing number of new materials.

Moreover, next generation chips will be faster or smaller or cheaper or more functional, and so will better serve the needs of new downstream customers. ASICs and 3D heterogeneous chip stacks will create new IC product categories leading to new market opportunities. Personalized health care could be the next revolution in information technologies, requiring far more sensors and communications and memory and logic chips. With a billion components, the possibilities for new designs to create new IC functionalities seems endless.

However, we are past the era when the next chips will be simultaneously faster and smaller and cheaper and more functional. We have to accept the end of Dennard Scaling and the economic limits of optical lithography. Still, we should remember what Gordon Moore meant in 1965 when he first talked about the future of IC manufacturing, because one factor remains the same:

The next generation of commercial IC chips will be better.

Past posts in the blog series:

Moore’s Law is Dead – (Part 1) What defines the end.

Moore’s Law is Dead – (Part 2) When we reach economic limits,

Moore’s Law is Dead – (Part 3) Where we reach atomic limits.

Future posts in this blog will ruminate about new materials, designs, and technologies for next 50 years of IC manufacturing.

E.K.