Subu Iyer of IBM addressed the evolution of high end memory + logic systems.

Die may be attached face to face or face to back which  allows for multi die stacking. The stacking process is very sensitive to die warpage and the handling of thin die and controlling their warpage is reportedly one of the key challenges.

James Lu of RPI reported on a novel partition and assembly approach that combines both the electromagnetic (EM) and analytical simulations to accurately model and analyze several through-silicon-via (TSV) based 3D power delivery networks, which are composed of various stacked-chips,

Due to the very large CTE difference between In and Si vs Cu and Si, InAu μ-bumps induce a huge amount of tensile stress (> 300 MPa) in the stacked die even at bonding temperature as low as 200C

The variations in electrical behavior due to thinning for PMOS and NMOS of Poly Gate devices are less than 2%; for HKMG devices, the variations are less than 1.7%. The device characteristics are preserved after the thinning process.

They conclude that the impact of wafer thinning, stacking, and TSV proximity effects to Poly and HKMG CMOS devices are analyzed. Little to no degradation to device performance due to TSV manufacturing demonstrates successful integration of state-of-the-art CMOS technology. This work provides essential information for future 3DIC integration.

For those of you interested in the difference between future high performance memory and mobile memory, Sitaram Arkalgud of Sematech has put together a nice slide addressing the differences

Arif Rahman, co-chair of the program, gave a presentation on the status of Altera 2.5D FPGA program with TSMC. They will combine FPGAs with a variety of technologies enabled by a high-speed chip-to-chip interface. Altera’s 20nm product portfolio will include die stacking capabilities. They see TSV process capability in place at foundry, IDM and leading OSATs.

Part 3 in our look at the 2012 RTI 3D-ASIP.

ST Ericsson / CEA Leti
The Wioming program was first described by ST Ericsson at last years 3D ASIP conference [see IFTLE 86, "3D Headlines at the RTI 3D ASIP part deux"].

Ogunseitan added that  "Although widely hailed as safer than compact fluorescent bulbs, which contain dangerous mercury, they [LEDs] weren’t properly tested for potential environmental health impacts before being marketed as the preferred alternative to inefficient incandescent bulbs, now being phased out under California law."

First things first:

In a recent Yole webcast, Eric Mournier took a market look at thin wafer bonding and processing.

Wafer thinning is required in a number of high growth microelectronic areas.

Thin (< 100μm) and even ultra-thin semiconductor wafers (< 40μm) are in demand for:

— Reduced package thickness
— Better heat dissipation / thermal management
— Increased TSV density

This brings up issues since the thinned wafers are more vulnerable to stress and the dies can warp and break.

Yole sees the following wafer thinning roadmap:

By 2017 memory will dominate the thinned wafer application space:

The major players will be the expected memory "Big 3" of Samsung, Hynix, and Micron:

They see greater than 10M wafers going through temporary bonding in 2017, which would be approximately 8% of total thinned wafers. The power and 3DIC markets will drive temporary bonding on carrier.

This will result in a temporary bonder / debonder market of $250M in 2017.

For all the latest in 3DIC and advanced packaging in 2013, stay linked to IFTLE………….

Continuing our look at the 2nd annual GaTech 2.5D Interposer Conference (for part one, see IFTLE 125: 2012 GaTech Interposer Conference, part I):

Ahmer Syed of Amkor took a look at micro bump electromigration issues. Issues inherent to electromigration have been around a long time [see IFTLE 56, "Electromigration at the 2011 ECTC"]. It is known that current densities on 10K A/cm² will induce EM within a few hours.

When we look at 2.5/3D we have radically changed the dimensions involved as shown below.

There is a 20�? increase in interconnect density from BGA to μbump and a 10�? reduction in pitch and ball diameter. Yet for the μbumps shown below they saw no failures even after 16K hrs of operation.

They conclude that:

– For WLCSP and BGA joints, they see Cu consumption and failure around the circumference

– For μbumps, they see copper conversion and IMC formation either during assembly or during current/temp stressing, but they see very long life

– While current carrying capacity for BGA and FC joints are in the expected range, μbumps can carry much higher current than theoretically predicted.

– Cu pillar bump interconnects provides the highest current carrying capability.

Nagesh Vordharalli of Altera quoted an IMEC study which shows that the sweet spot for maximum bandwidth will come from interposers with RDL lines/spaces ~3μm. Nagesh feels that silicon based interposers need to be in the 1-2 cents/ mm range to compete with future high density laminate technology.

Professor Joungho Kim of KAIST shared his assessment of Si vs. glass interposer electrical performance. Imajo developed comparative data for double sided interposers with 10μm TGV/TSV on 40μm and 100μm pitch. TSV had oxide insulator thickness of 0.5μm. He proposes that interposer type will depend on IO count and bandwidth requirements as shown below.

Nobu Imajo of AGC reported on their ongoing activities to develop low-cost, high-density glass interposers. AGC is looking at EN-A1 glass because of its better CTE match to silicon. They use an e discharge process to form the TGV. They are currently working with 60um TGV on 100μm pitch. Below we see 300μm thick glass with 60μm TGV (entry) and 40μm (exit).

They are working on metallizing the TGV with copper. For thinner substrate structures, a glass carrier will be required.

Representing Yole Développement, I reported that 2.5D/3D interposer revenues in 2017 is expected to reach $1.37B, or 15% of the packaging substrate market value.

By 2017 Yole expects silicon interposers to exceed the revenue of their glass counterparts by at least 3.5:1. During the panel session, I indicated that to me it is highly unlikely that we will see OSATS buying flat panel display lines to produce glass interposers. It is much more likely that we will see current flat-panel producers become aware of the potential market for glass interposers and enter the market themselves.

For all the latest on 3D IC and advanced packaging stay linked to IFTLE……………

Many of the world’s 3D elite meet the 3^rd week of November at the 2^nd annual GaTech 2.5D Interposer Conference which focused on the technology and performance of silicon and glass interposers. Chairs Tummala and Garrou assembled an expert panel of many of todays fabricators and users to deliver keynote addresses and answer attendee questions on where we are and where we are going. This meeting is sponsored by IEEE CPMT, IMAPS, iNEMI, and SEMI.

Sitaram Arkalgud outlined SEMATECH’s comprehensive 2.5/3D program which includes:

They see bonding going through an evolution which leads towards thermal compression copper-copper bonding on a less than 30μm pitch. Arkalgud reported that current copper-copper bonding occurs at 400°C with a throughput of 0.5 wafers/hour. The SEMATECH goal is to develop a process that can improve on both of those criteria.

They claim to have demonstrated a low time / temperature process (245°C / 5 min) on patterned wafers and have a tool concept proposed which could increase wafer throughput to 30 WPH.

The current SEMATECH roadmap for copper-copper bonding and thin wafer handing is shown below.

Jon Greenwood of GlobalFoundries shared their thoughts on "collaboration" and how important this is for complex infrastructures like 2.5D or 3D. Since both UMC and GlobalFoundries appear to be behind TSMC in the introduction of a qualified 2.5D process [see IFTLE 122: TSMC officially ready for 2.5D, Apple order impact on TSMC] and they have both publically supported a collaboration approach vs. the TSMC "one-stop shopping approach, presenting arguments for this approach was not unexpected. Greenwood indicated that 3D is being focused in Fab 8 in NY while 2.5D solutions are being focused in Fab 7 in Singapore. Process development was done in conjunction with IMEC in Belgium and Fraunhoffer ASSID in Dresden. They specifically call out the Big 4 OSATS as their assembly partners.

Matt Nowak of Qualcomm, long an advocate 3D technology, reported that Qualcomm has now built "thousands of parts" and does not see anything stopping high-volume manufacturing (HVM) except cost.

Qualcomm defines high density for 2.5/3D as: 5-10μm TSV, AR ~ 10:1; 1K-10K TSV / μbumps; 10’s μm bump pitch. They see the following categories evolving:

Nowak indicates that Qualcomm will require a price of ~$2 for a 200 mm² high-density silicon interposer. The high-density aspect is out of the reach of those proposing low-cost "coarse" interposer fabrication and the pricing appears significantly out of reach for the pricing structure for dual damascene foundry-based fine interposers.

For all the latest on 3D IC and advanced packaging, stay linked to IFTLE………………

First and most importantly, in the US we just had our "Thanksgiving" holiday weekend. This means I was with granddaughters Hannah and Madeline in NYC for the Thanksgiving parade and then a long… long… long shopping time at the American Girl store. Here they are posed in front of American Girl. For those keeping track they are now 8 and 5.

Now back to the technology………… With the recent announcement by STATSChipPAC (SCP) that they are offering eWLB as a platform for 2.5D-3D packaging solutions [link] IFTLE thought that it was a good time for a review of the status and future of fan-out WLP (FO-WLP).

Nanium

In October, Nanium, one of the first semiconductor companies to build volume capacity for 300mm eWLB wafers in late 2010, announced that it has shipped its 200 millionth eWLB component for wireless communications and other applications.

Nanium announced that they had recently adapted eWLB technology for consumer MEMS, stacked die DRAM multichip packages for high-capacity memory applications, mixed-signal RF ASIC, and heterogeneous integration within System-in-Package (SiP).

Steffen Krohnert, Nanium’s director of technology, reports that "Intel usage of the eWLB packages is for wireless consumer products (modems, RF, SoC), mainly baseband and RF chips, and also for full low-cost mobile phone on SoC…we even see increasing volumes and higher number of products in eWLB coming from Intel Mobile Communications (IMC), which is now part of the new Intel Mobile and Communications Group (MCG) and we see interest in other parts of MCG such as the Connectivity Group (MWG)."

Krohnert also reports Nanium has " ~ 20 R&D projects with semiconductor companies to implement eWLB for their products." Examples for new eWLB markets and applications include "stacked memory, heterogeneous integration for medical and security SiP, mixed-signal ASIC, RF and high-power dissipation applications, ASIC + MEMS SiP, PMU, optoelectronics/ fiber optics SiP, mm-wave/ 60GHz radar products… long-term we plan also to introduce eWLB in automotive applications, e.g. MEMS + ASIC SiP."

Yole Developpment

Yole Developpment has recently updated its "FOWLP & Embedded Die Packages" report [link]. The FOWLP market is said to have reached the $100M market last year with Nanium and SCP representing 81% of this production mainly driven by Intel Mobile’s volume demand on eWLB production.

Lionel Cadix, market & technology analyst at Yole Développement, indicates that "This young industry will need to wait until 2015-2016 to reach $200M, as the demand will shift from IDMs to leading fab-less wireless IC players, such as Qualcomm, Broadcom, Mediatek, etc… and will be supported by the solid infrastructure of ‘top 4’ major assembly houses."

He continues with the observation that "low reliability on large package body size and lack of flexibility in the IC to package co-design process are the two main factors limiting the wide adoption of FOWLP technology in the wireless IC market. Indeed, FOWLP technology imposes a specific redesign of the chip for efficient integration into the package: both Infineon and ST Ericsson (who already have products on the market) spent almost 18 month to redesign their baseband and RF-Transceiver SoCs in order to place the pads at optimized locations and match with a single RDL, 0.5mm board pitch eWLB package design. FOWLP is a restrictive package technology for most of the world’s IC designers to adopt efficiently, especially fabless chip companies. This is why only big semiconductor IDM companies having IC-to-package co-design environments well established in-house can drive and support the initial growth of this new wafer-level-packaging platform at its early stages."

Cadix reports that OSAT players ADL (TW), Amkor and NEPES (SG) are reading production and TSMC and SPIL are expected to have production ready in 2013-2014.

Infineon (GE) was the first company to commercialize its own eWLB packaging technology in an LGE cell-phone in early 2009 (see cross section below) Infineon’s chip is a wireless baseband SOC with multiple integrated functions (GPS, FM radio, BT…). The same eWLB product has also been in production in Nokia handsets since 2010.

LGE (wireless baseband), Samsung (baseband modem), and Nokia ( baseband modem and RF transceiver) have used eWLB in their cell phone products.

Deca Technologies

Chris Scanlan, VP of product management for Deca Technologies, recently gave a presentation entitled "Adaptive Patterning for Panelized Packaging" which described the company’s M-Series platform of embedded die (FOWLP) packaging.

Scanlan reported that their new process avoids the current pick-and-place positional accuracy and mold compound shrinkage issues inherent to current FOWLP processes. Die position accuracy of < 10μm and rotational accuracy of < 0.1° are typically required which in turn requires slow pick-and-place speed.

In Deca’s "Adaptive Patterning" process, die with copped studs (think copper pillar bump) are placed onto a carrier and molded into a 300mm wafer. Wafers are then removed from the carrier and planarized to reveal the copper studs. The wafer is imaged and the position of each die is imported into a proprietary software.

Connections are then made between the standard pad positions and the actual positions of the placed die. Deca has not disclosed the lithography process, but we do know that there are no traditional glass masks involved — which certainly helps explain their claimed fast turn around time. Industry conjecture is that some sort of laser processing is involved.

Customers have not been identified, although parent Cypress is probably one of them. Deca says it is "sampling to a limited set of customers with broader availability planned for 2013."

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE……………………

Insight into Intel and 3DIC

For those of you that haven’t read Ed Sperling’s recent interview with Intel’s CTO Mark Bohr in Semi Manuf and Design, it contains some interesting comments on the 3D area [link]:

SMD: Where do stacked die fit into your roadmap?

Bohr: 3D stacked die have advantages, but only for certain market segments. You have to be very clear about what problem and what market segment you are trying to serve.

For a small handheld application where a small footprint and form factor are key and power levels are low, it probably makes good sense to use 3D stacking. For desktop, laptop and server applications where form factor isn’t as valuable and power levels are higher, 3D stacking has some problems that make it not an ideal solution.

And his thoughts on interconnect…

SMD: Is the interconnect [on chip] becoming more problematic?
Bohr: If you talk to a designer 10 years ago you would have heard the same thing. Maybe now they’re saying, ‘This time we’re really serious.’

SMD: How about new interconnect technology?
Bohr: It’s hard to replace copper and low-k other than by making lower k. But at least in the low-power cell phone market, stacking chips does help to minimize some of the interconnect issues, particularly between the logic and the memory chips.

SMD: You’re referring to through-silicon vias?
Bohr: Yes.

SMD: So if Intel is planning to get into that market, the company is experimenting with that technology right now?
Bohr: Yes, and we’ve been public about exploring TSV and 3D technology for a couple years. Although there are some challenging technology aspects, the real issue is cost. Doing TSVs and stacking chips — especially these custom Wide I/O chips — is expensive. So this might be a better engineering solution in terms of density, performance and power, but will the market bear the added cost? Not all markets will bear the higher cost.

Intel to use DDR4 with TSV starting in 2014?

Despite these comments, IFTLE would be remiss if we didn’t point out that rumors continue to swirl that Intel will use 3D stacked DDR4 memory in their Haswell-EX platform for enterprise computing [link].

Since Haswell will feature microprocessors with 12-14 cores, it will benefit from lower memory power consumption, higher memory bandwidth, and the memory capacity that DDR3 simply cannot provide. DRAM makers will make high-capacity DDR4 chips using through-silicon-via (TSV) technology that will allow to increase capacity of memory chips at a very fast rate. For servers, special switches will be introduced to avoid one module/one channel limitation.

Samsung DDR4

Indeed, Samsung demonstrated its next-generation DDR4 chips and memory modules at the Intel Developer Forum. Samsung showed a 300mm wafer of DDR4 die processed using 30 nm technology, insinuating that it could start production of DDR4 anytime the infrastructure became ready. Samsung plans to take DDR4 module speed for 2014 servers [like Haswell-EX?] to 2.666 GHz. Eventually, Samsung and Intel intend to boost the effective clock-speeds of DDR4 server memory modules to rather whopping 3.20GHz.

It is reported that in DDR4 memory sub-systems every memory channel will support only one memory module. To enable the highest-possible memory capacities, DRAM makers will use TSV stacking to make high-capacity DDR4 chips. Special switches will be used in server modules to avoid this module/one channel limitation.

Amazon in talks to buy TI’s mobile chip business?

Last month Texas Instruments announced plans to shift its focus away from its mobile processor business (~ $650M sales) and target broader markets such as industrial clients in the car industry, and Wall Street has speculated it could be sold.

Now, according to a report from Israeli newspaper Calcalist, Amazon is said to be in "advanced negotiations" to acquire this business from TI. This would be a step towards vertical integration for production of its Kindle tablets and could indicate an interest in entering the smartphones business. TI’s processors are used in Amazon’s Kindle Fire tablet. Amazon CEO Bezos reportedly touted TI’s industry strength at their new tablets recent launch. Speculation has existed for more than a year that Amazon could sell its own smartphone but Bezos has not addressed those rumors. The 1.0 GHz dual-core Texas Instruments 4430 OMAP application processor runs the Kindle Fire [link].

Reuters reports that Amazon declined to comment on the report. TI said it does not comment on rumors but said in an email to Reuters: "The smartphone market has become a less attractive long-term opportunity for TI … and we are re-profiling our investment accordingly."

If this sounds strange, why is it that different than Microsoft with its traditional business model of licensing operating systems to PC manufacturers, who will this month will launch the "Surface tablet," which it designed itself?

Communications to surpass computers as leading application for ICs

Our friends at IC Insights in their study, "IC market drivers 2013: A study of emerging and major end-use applications fueling demand for integrated circuits," forecasts communications applications to pass computer applications as the leading end-use for ICs starting in 2014 and lasting through at least 2016. The IC communications market is forecast to grow 9.2% in 2012 to $90.0 billion from $82.4 billion in 2011, and increase 11.7% to $100.5 billion in 2013, breaking the $100-billion level for the first time. The total communications IC market is forecast to reach $114.4 billion in 2014, 4.6% more than the $109.4 billion computer IC market. From 2011 to 2016, the communications IC market is forecast to grow by a cumulative annual growth rate (CAGR) of 14.1%, reaching $159.5 billion at the end of the forecast period. The communications segment accounted for 31.2% of worldwide IC sales in 2011 and the computer end-use segment 41.7%. By 2016, these two segments will flip-flop, with communications forecast to represent 42.2% of the total IC market, compared to 34.0% for the computer segment.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…………