The 3D TSV announcements keep coming at a “fast and furious” pace and are becoming hard for all of us to keep up with. One announcement (this past week) and one rumor, are very important for the forward momentum of 3D IC integration.

A few weeks ago Mark Durcan, COO of Micron, at the IEEE ISS meeting in Half Moon Bay, commented that Micron is ”sampling products based on TSVs” and that “Mass production for TSV-based 3-D chips are slated for the next year or 18 months” [see IFTLE 33, “ Micron 3D Response, Sematech Standards, Leti 300 mm Line” ]

Now, Micron has announced that it is using TSV technology to address the longstanding problem referred to as the "memory wall". [see “Micron to reveal tech it says increases chip speed 20-fold” ]


For those that are interested, the seminal paper in the area appears to be “Hitting the Memory Wall: Implications of the Obvious” by Wulf and McKee in the March 1995 issue of Computer Architecture News which can be read here [link]. It presents an interesting discussion of the bounds on processor performance imposed by memory performance. Historically, processor performance has improved by about 60% per year, whereas the corresponding improvement in memory access time has been less than 10% per year. Latencies are dominated by DRAM access times which has changed VERY slowly over last 20 years. DRAM performance is constrained by the capacity of the data channel that sits between the memory and the processor. No matter how much faster the DRAM chip itself gets, the channel typically chokes on the capacity. Systems are not able to take advantage of new memory technologies because of this latency issue.

Brian Shirley, vice president of DRAM Solutions at Micron claims that their “hyper memory cube” technology “â??¦offers a 20-fold performance increase while reducing the size of the chip and consuming about one-tenth of the power”. They reportedly accomplish this by stacking memory on top of a controller layer (shown in the Micron fig below as logic layer) and connecting with TSV. The “wide bus” from the controller layer to the CPU is reportedly “hugh” (possible 512 bits ??)


Shirley commented “Performance needs are most dire in networking and cloud computing. One-hundred gigabit Ethernet routers and switches and cloud computing servers require everything they can getâ??¦â??¦this is our way of giving them a fire hydrant.”

They hope to see the memory cube technology in server and networking markets as early as 2012, with significant volumes in 2013, and could then start to work their way toward the consumer space in 2015.

The overall concept of the control layer reminds IFTLE of the structures that Bob Patti of Tezzaron has been showing for the past 5 years (see below)

Although Intel will not confirm, rumors persist that the key to Ivy Bridge’s reported performance is its stacked memory and silicon interposer [see: “Intel puts GPU memory on Ivy Bridge” ]


Rumors are that Ivy bridge will use LPDDR2 memory, possibly with a speed of only 1066MHz, and that memory stacking technology could bring it up to 1GB. The memory is then stacked upon a silicon interposer. The reason a silicon interposer is essential for Ivy Bridge is the large width of the low-power memory. Since 512 bit brings with it high pin and trace counts, which would require more layers and increase cost. The interposer decreases the required on chip layers and reducing the overall cost.


IFTLE has taken the rumors a step further. IFTLE thinks it is possible that the following patent application [ see: US 7,841,080 B2 ] entitled “Multichip Packaging using an Interposer with Through Vias” which describes having a CPU on an interposer with stacked DRAM and a voltage regulator may be related to the Ivy Bridge implementation.


Ivy Bridge may be Intel’s first product introduction with TSV. We’ll know for sure one they release the information and/or once Ivy Bridge is released and analyzed by someone like Chipworks.


One additional comment. It is likely that the use of an interposer (if true) reveals that Intel agrees with Xilinx [ see: IFTLE 23, “Xilinx 28 nm Multidie FPGAâ??¦” ] and indeed true 3D stacking (memory directly bonded to logic circuits with TSV) is not yet available and/or ready for “prime time” â??¦.yet.

For all the latest in 3D integration and advanced packaging stay linked to Insights from the Leading Edgeâ??¦.




Like the IEEE ESTC meeting held in Europe [see IFTLE 26 Adv.Pkging at the 2010 ESTC] , Asia’s IEEE EPTC meeting, held every year in Singapore, is a sister meeting of the IEEE ECTC.

Electromigration
The recent interest in electromigration is due to a number of issues including the drive to Pb free bumps, the trend towards increased IO density resulting in smaller and finer pitch bumps, and the introduction of 3D IC structures. The concurrent increase in power density is requiring chip-to-package interconnect to carry more current per interconnect. Since electromigration reliability is a direct function of interconnect dimensions and metallurgy, any new interconnect developments need to be characterized for electromigration reliability.
Solder composition and under bump metallization (UBM) are key factors that are known to affect electromigration failure. It is well known that increasing current density has a negative impact on electromigration. Reduction in bump size leads to an increase of current density with current density increasing as a square function of the bump diameter.

Yoo of Nepes reported on their investigation of the impact of UBM (under bump metallization) on electromigration for copper pillar bumps (CPB) and various UBM metallizations (Cu 5μm UBM, Cu 10μm UBM, Cu/Ni UBM ) in conjunction with SnAg solder bumps of various sizes, at a constant current density of 5.09x104A/cm2.
MTTFs, obtained from Weibull plots are summarized in the Table below. MTTF (20% resistance increase) became longer as test temperature was lowered for each bump structure. At 150 C, MTTF followed the order: CPB > Cu/Ni > Cu 10μm > Cu 5μm. Life time of CPB was 35times longer than Cu 5μm UBM/solder bumps under the same conditions.

Fan out or embedded wafer level packaging (e-WLB) remains a red hot packaging topic only rivaled by 3D IC. [ see IFTLE 22, “Sources for Fan Out WP Continue to Expand” ] In the opinion of IFTLE, FO-WLP is this decades BGA and we will see it replacing the BGA format in many application spaces. While the last decade saw the explosive growth of fan in WLP, FO-WLP takes over as a WLP technology when the package size must be larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects.

One of the most well known examples of FO-WLP is the “eWLB” developed by Infineon and there consortium consisting of ST Micro, STATSChipPAC and ASE.


STATSChipPAC presented data on thermal electrical and mechanical performance. In the table below we see that thermal modeling shows that an eWLB and an equivalent FC-BGA show equivalent thermal performance.

The figure below depicts Q performance comparison of inductors made by different processes/options. An inductor made directly above an active IC has a Q peak is around 26. The same inductor made from the STATS thn film IPD (integrated passive device) process has a Q max of~ 30 whereas if made on mold compound in the FO area, its peak Q can be 35.

The figure below shows comparison of parasitic values of RLC for fcBGA and eWLB at 1GHz. For resistance, eWLB has 68% less value than fcBGA. Moreover, eWLB has 66% less inductance value and 39% less capacitance compared to fcBGA. It is mainly due to shorter interconnection in eWLB.

In Rf applications such as power amps (PAs) , the PA chip and a IPD can be combined into a 2 die eWLB as shown below.

ST Micro, STATSChipPAC and Infineon gave a presentation on the next generation eWLB concepts. They listed the next generation variations of the eWLB as:

1) enabling two or more layers of routing
2) expanding the package size to 12x12mm
3) allowing for thinner packages and side by side chips within the eWLB
4) double sided Package on Package (PoP) eWLB


With optimized design, 12x12mm eWLB successfully passed 500 cycles of TC [40/125C, 2cycles/hr.).
Thinner packages can provide better board level reliability as well as lighter and thinner profile at the system level. eWLB can be thinned down to 250 um thickness. The critical technical challenges included handling the thin wafer and grinding and removing of the Si/epoxy material together using the same process steps. There was found more than 60% increase in thermal cycling performance with thinner eWLB and drop reliability also improved significantly.

Another approach will be double sided interconnection reminiscent of the Amkor TMV structures as show below.

Songdong Cho, Sr engineer in the Samsung system LSI group spent the conference besieged by questions from attendees on the Samsung (memory group) announcement that occurred the day before the meeting. [see IFTLE 27, “The Era of 3D IC Has Arrived with Samsung Commercial Announcement”]

Cho first led the attendees through the evolution of Samsung 3D IC technologies:

– 2006 Samsung announces memory stacking technology

-2007 DRAM stacked memory package using TSV

-2008 TSV for CMOS image sensors mass production

– 2008 memory + logic on silicon interposer – start development

-2010 announce DRAM stacked memory with TSV commercialization

(all of these can be found in past editions of PFTLE and IFTLE)

Cho indicated that mobile products will require more than 25 GB/sec bandwidth in ~ 2012 and therefore “..wide I/O memory with TSV is the only solution” There will be two platforms for the systems LSI group: Interposer and memory on logic as shown below.

– High AR TSV filling
– Cu extrusion
– Stress impact on devices
-Copper contamination (through sidewall and during backside processing)


By eliminating voids during the plated copper filling they were able to achieve 99.57% via chain yield.


Cho lists (3) ways to deal with Cu extrusion:


– Tungsten TSV
– Cu TSV last backside
– Via size and depth reduction


They have determined a workable depth vs diameter space using the 3rd option which results in less than 0.2 um extrusion. [ recall this was first shared with us by Bob Patti – see PFTLE 53, “You Can’t Always Get What You Want”]


They worry about copper contamination when backside processing due to a decrease in the gettering layer (see previous discussions in PFTLE 117, “On copper diffusion, gettering and the denuded zone”]


Cho indicates that they will not use W because of the severe wafer bow that even 1 um of W imparts to a 300 mm wafer. They also see severe Si cracking and IMD cracking due to the high W stress.

Cho expects to see mass production from his side of the business in 2013.

Eric Beyne – IMEC


Conference co-chair Eric Beyne, program director for advanced packaging and interconnect at IMEC . The IMEC standard processes have been discussed several times previously [ see PFTLE 122, “3-D IC at the IEEE ISSCC” ; PFTLE 93, “ Semicon TechXPOTs” ]


Beyne indicates that high speed graphics applications are demanding 512 GB/sec memory bandwidth and thus agrees with the consensus that 3D with TSV is the only way to go.


The POR for their 3D TSV middle process (3D-SIC) is 5 x 50 um which looks like it is becoming an industry standard.


Their wafer thinning technology achieves a less than 1.6 um TTV for a 300 mm wafer thinned to 50 um.

Yannou focused on the use of 3D interposers for 2.5D technology and offered the following proposed interconnect gap timeline showing that silicon / glass interposers offer 10x more resolution and finer pitches than traditional organic substrates.

Arif Rahman, principle engineer at Xilinx gave further details on their next generation FPGA choices that have been reported recently [ see IFTLE 23 , “Xilinx 28 nm Multidie FPGAâ??¦”]


When asked about their choice of a silicon interposer for their next generation FPGA, Arif Rahman commented that “ it appeared to be the most manufacturable way to offer product performance during our required timeline” which I interpret as “”full 3D is not quite to the point that we were ready to bet the farm on it”


The interconnect on the interposer is done at 65 nm technology. In terms of scalability Rahman noted that the technology was currently limited by “â??¦how big an interposer you can get”

Note: After the conference Arif left word that he had moved to Altera – interesting !


Larry Smith – Sematech


In their 3D program update, Smith indicated that after much study and consultation with its members, Sematech was focused on 5 x 50 um copper vias middle with AR = 4-10 and pitch of 10-50 um. Their status assessment is shown below:

Lisa McIlrath, CEO of R3Logic was one of the first to understand and tackle the EDA requirements of 3D IC technology. [ see PFTLE 102, “The Four Horseman of 3D IC” ]


She had what was probably the quote of the conference when she astutely stated “3D Integration will become mainstream when it is the best economic alternative” Simple yet accurate ! From her design perspective she feels that this will occur by maximizing IP re-use.


Philippe Royannez – IME


IME 3D technology has been discussed previously [see PFTLE 98, “ TSMC Confirms 3D Intent / Singapore Launches 3D IC Consortium “ ]


Philippe Royannez, Director Sytem & Digital IC at A-STAR updated activities at IME in Singapore. Royannez indicates that their 300 mm line will be fully operational n the 2nd- 3rd quarter of 2011.


In keeping with the cost reduction theme, Royannez indicated that IME “ has solutions to most of the technical challenges now. The real focus now needs to be making these solutions low cost. “


When it comes to EDA Royannez notes that “designers understand the theoretical benefits of TSV but cannot quantify it precisely and don’t quite understand what to do to use them” He notes that 3D IC EDA flow “is more evolution than revolutionâ??¦all the ingredients are there” but then quickly added “..for true 3D IC, that is the spreading of blocks across layers, certainly we’re not quite there yet, but for initial 3D programs we are in pretty good shape”


In an interesting blood pressure monitor application Royannez made the point that we need to be focused on system level integration. In this application shrinking the size of the circuits and making them faster will not have any impact on the size of the battery which will continue to drive the overall size of the device.


Tzu Kun Ku – ITRI


The ITRI Ad-STAC ( Adv Stacked system Technology and Applications) program has been detailed previously [see PFTLE 105 “Taiwanese Focus on 3D IC”]


The ITRI 3D program currently covers both chip stacking with TSV and the use of 3D interposers. There are currently 120 technologists assigned to their program (80 design, 40 process development). Their TSV formation roadmap is shown below. Their 300 mm line is in place and their baseline process is scheduled to be completed end of this year.







This week we begin a look at activities at the RTI 3-D Architectures for Semiconductor Integration and Packaging Conference ( 3d ASIP) held in Dec 2010 in Burlingame CA . This is the longest running 3D conference (since 2003) and is focused on both technical developments and the commercial infrastructure. Once again an excellent group of commercial technologists and business people were assembled to share their views on the commercialization of this technology.

Lets first take a look at the Keynote presentations:

Subramanian Iyer, IBM


Confirming what PFTLE and IFTLE readers have been reading for several years now Iyer points out that :


– Scaling, strain engineering, and improved materials (eg. Hi K) will continue to improve performance , though at diminishing rates and certainly with diminishing returns


– A combination of voltage supply reduction, power budget constraints and design IP migration suggest that the days of dramatic raw performance gains are over


– Performance must come from elsewhere – Low latency memory integration provides significant system leverage


Iyer commented that he had spent the last 10 years of his life “..trying to get more memory closer to the processor”. Iyer indicated that integrating large amounts of low latency memory is one of the biggest challenges for modern multi-core processor design. Since modern processors contain 60-70% embedded memory, taking that memory off chip and using TSV to make such memory low latency and high bandwidth can in fact cut the size of the processor chip by as much as 50%. In addition placement of thin film deep trench decoupling caps can give a 5-10% performance improvement by stabilizing the power distribution.


Iyer labeled TSV as “..a necessary evil” which “..mess up logic or memory designs”. He adds that the TSV designs need to be done efficiently and adds that “..today we can do this with about a 5% penalty on the DRAM”


Iyer gave us indications for the first time that all vias middle are not equal. In fact he suggested that for some circuits intercepting at layer 4 might be the best circuit option. “..integration into oxide vs low K levels can be advantageous since they are much stronger and able to withstand the stresses that the TSVs generate on the structure” Iyer adds that one is “.. always trading off integration difficulty vs lower wirability capability due to blockage of the interconnect layers by the TSV.

Douglas Yu – TSMC

Dr. Yu, Sr Director of the Interconnect and Packaging Division, focused his presentation on the overall issues of packaging advanced node chips and how that relates to the future requirements for TSV and 3D stacking.


Yu indicates that with the rapid cost increases imposed by scaling TSMC sees chip scaling migrating into “system scaling” and 3D technology as being part of that whole movement.


Yu sees copper TSV and vias middle becoming the industry standards (as IFTLE has predicted for many years now) and he sees the copper protrusion issue as being solved [ see IFTLE 34 “3D IC at the 2010  IEDM” and “Cu protrusion, keep-out zones highlight 3D talks at IEDM” for details ]. They are currently comfortable with 50 um wafer thickness although they expect to go lower.


When asked about their commercial commitment to silicon interposers Yu responded “ Yes we will offer commercial silicon interposers as we have recently announced with our customer [Xilinx]" [ see IFTLE 23, “Xilinx 28 nm Multidie FPGAâ??¦”]


Yi-Shao Lai – ASE


Dr Lai filled in for Ho Ming Tong , who we were told was called away for an internal corporate meeting involving “a big investment for 3D IC”. Later in the day we heard from ASE that the budgeting was approved.


Lai indicated that ASE felt the industry was in much better shape for 3D IC then it was 3 years ago when ASE began looking at this technology in earnest.


Echoing the feeling of many participants Lai commented that the infrastructure could only be built by everyone “â??¦sharing critical information without leaking proprietary know how” Lai also requested further standardization of the supply chain. “ ..if chips will come from 3 or 4 foundries and the OSATS are chosen to do the backside processing and stacking, must the incoming materials be standardized so that OSATS can have a standard process for minimized cost? “


Anton Domic – Synopsys


Anton Domic, Sr VP and GM at Synopsys tried to give the EDA perspective on the migration from 2D to 3D. The theme for Synopsys, a late entrant into the 3D arena was that 3D was “heating up”.


Much is being made in other blogs about the comparison Domic made about 3D integration CoO. He indicated that 3D IC had a 5% impact on 300 mm wafer production and compared that to SOI (5%) and high k gates (10-20%). My feeling is that this was a generic statement and was made to indicate a relative comparison to things people all readily accept are happening.


We all understand that 3D is not a unit operation, it is an approach, and as such there is not one number to indicate its impact on cost. Cost modeling for 3D technology must be made on a system basis and as such there are NO numbers out there that I can say I believe yet. Now that real 3D IC technology (TSV, thinning, stacking) has been announced for memory [ see IFTLE 8, “3D Infrastructure Announcements and Rumors” ; IFTLE 27, “Era of 3D IC Has Arrived with Samsung Commercial Announcement” ] we will really begin to understand the true cost of implementing these technologies.


The same is true for and for 2.5D silicon interposers [ see IFTLE 23, “Xilinx 28 nm Multidie FPGAâ??¦”; IFTLE 27, “Era of 3D IC Has Arrived with Samsung Commercial Announcement” ]


Domic reiterated the point made by IBM’s Iyer – that TSVs are HUGE and added that TSV number and placement is crucial, mobility changes due to SPE (stress proximity effects) can be significant and thus keep out zones can be significant and that test is challenging.

When discussing silicon interposers which Domic labels “there already” because of the Xilinx announcement, Synopsys offers the following Implementation flow:

For all the latest on 3D IC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦..

With the general belief that CMOS is becoming economically if not technically less and less viable as the industry continues to scale, it is to be expected that we will be seeing more and more 3D IC presentations at the IEEEs premier IC conferences namely the ISSCC (Int Solid State Circuits Conference) and the IEDM (Int Electronic Device Meeting).
At the 2009 IEDM TSMC researchers called 3D IC “an enabling foundry technology for 28 nm and beyond” after they studied the impact of 3D thinning ( to ~ 50 μm) and fine pitch bonding on strained and unstrained 40 nm Cu / ELK CMOS and Koyanagi and co-workers from Tohoku University examined the electrical implications of mechanical stress / strain and metal contamination on thinned 3D LSI.[ see PFTLE 117, “ On Copper Diffusion, Gettering and the Denuded Zone “. In 2010 3DIC became even more prominent at the IEDM.

Qualcomm
During his 2010 keynote presentation Jim Clifford, Sr VP and Operations GM indicated that scaling could get to expensive and therefore Qualcomm was backing 3D TSV technology and urged the rest of the industry to collaborate on 3D IC and invest in its infant infrastructure.

Samsung

Dr Kinam Kim, President of Samsung Advanced Institute of Technology (SAIT) in his keynote presentation on the future of silicon technology noted that conventional scaling was becoming more challenging in terms of materials, patterning and electrical performance, and now requires huge capital investments. He commented that current scaling strategy “â??¦is almost unusable for the 10 nm nodeâ??¦”.

Samsung sees mobile processors, FPGA, and high performance ASIC applications will require “ more functionality at greater speeds” which will require “… a heterogeneous device stack with a wide I/O interface and high data rates”. Kim notes that “..the semiconductor industry is adopting 3D IC technology as a promising solution for these devices”. Kim added that short term TSV based IC technologies along with 3D Si interposers will accelerate the adoption of 3D system-in-package (SiP) heterogeneous integration. “..This might be the next driver for genuine 3D IC devices in the future with tremendous benefits in footprint, performance, functionality, data bandwidth, and power”


TSMC


In their presentation on 3D integration for the 28 node and beyond, TSMC indicates that “optimized fabrication processes and materials selection are critical to achieve high device performance, yield and reliability for 3D technology integration on 300 mm wafers” . They claim to have successfully integrated 3D technology into advanced CMOS foundry processes which is “.. a major step toward 3D production”.


Of interest are the TSMC studies on Cu protrusion and its effects on device fabrication and reliability. They find that the amount and shape of protrusions, (shown in the figure below) depend on several process parameters, including the electroplating processes (ECP), electrolyte selection, impurities co-deposited with Cu, Cu grain size distribution, and post deposition annealing conditions. As the system cools down from thermal excursions, mismatches in CTE between silicon, oxide liner, and Cu fill introduces two un-desirable effects. The first effect is Cu extrusion around the center of the TSV, shown below. The second effect is liner cracking. Having the smallest CTE, the oxide liner undergoes high stresses exerted by the Cu TSV and the Si substrate. The maximum stress concentration is found to be near TSV bottom, where the majority of liner cracks were observed that causes significant current leakage.


It is also shown that residual stress remains in Si substrate after TSV processing. For devices using strain-Si technology, an active device a keep-out zone surrounding each TSV is required to minimize TSV impact on performance.

In a joint program between IBM Yorktown and National Chiao Tung Univ (NCTU) in Taiwan “oxide recessed” vs “lock & key” bonding structures were compared and contrasted.

For the lock-n-key structure, the “lock” part is achieved by recessing Cu, while the “key” part is fabricated with recessing oxide. The recessed amounts of both parts are carefully fabricated to make sure two Cu surfaces can contact during bonding. In addition, the lock-n-key structure allows oxides from both wafers to simultaneously bonded during Cu bonding (Cu-oxide hybrid bonding).

After alignment, wafers were bonded at 400°C for 1 hour under a 10,000 N force in the ambient of 2×10-4 torr. The bonded wafers were then diced and held at 200°C for 70 hr in air to test for corrosion. The lock-n-key structures show clear well-bonded structure, indicating excellent corrosion resistance whereas the Cu bonded, oxide-recessed structures have become significantly corroded. In addition, the bond strengths of lock-n-key structures are higher than those of oxide-recessed ones.


IMEC


3D induced stresses are one of the key constraints in a 3D design flow that must be controlled in order to preserve the integrity of front end devices. IMEC and some of their consortium members (Panasonic, Qualcomm, Samsung) examined the stress induced by single- and arrayed TSVs, quantifying the stress distribution and determining its impact on both analog and digital FEOL devices and circuits. Stress aware design and the right definition of keep out zone will be needed to optimize silicon area.

From stress modeling studies such and experimental data points, transistor “keep out zones” are derived for both digital and analog circuits. The IMEC researchers conclude that the KOZ for a large matrix of TSVs is over 200 µm for analog circuits and 20 µm for digital circuits and add that the complex interaction of stress components makes it difficult to use simple design rules without sacrificing large layout area. Depending on the TSV footprint and the number of TSV required different TSV placements will be optimum (single, row, matrix).

Tohoku Univ

Mechanical stress / strain in thin 3D structures was once again the topic of study for 3D technology veteran Professor Matsui Koyanagi of Tohoku University. The Tohoku group has concluded that high performance 3D-LSI require 104 to 105 micro-bumps/TSVs and a die thickness of ~ 20 μm. They find that mechanical strain/stress and crystal defects are produced in extremely thin of 3D-LSI wafers (~10 μm) not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density microbumps and underfill curing. Cu/Sn microbumps induce stress/ strain at Si wafer surface, which penetrates deeper for larger bump size and wider for smaller bump pitch. They note that this locally induced stress / strain can result in a 10% change in the ON current of p-MOS transistor.


Koyanagi also reported that the metal of the TSV and microbumps not only induce stress / strain (due to the difference in the CTE between Si and metal in thinned Si substrate but also can be the cause of metallic contamination.

For all the latest on 3D integration and advanced packaging stay linked to IFTLEâ??¦

Since the fall is always an busy time for professional meetings around the world, and nearly all microelectronic meetings are trying to give you 3D IC coverage, I’m having a tough time covering all of this information in a timely, chronological way. The major items are hitting SST as articles but the more data driven information will simply have to work its way through the que. This week an extra blog dedicated to recent 3D IC news items of interest.

Micron
With the recent Samsung announcement of stacked 3D memory products [ see IFTLE 27, “Era of 3DIC Has Arrived with Samsung Commercial Announcement”] IFTLE predicted a response from the other memory suppliers and actually asked “ Will Hynix or Micron announce next ?”

Well the answer is in and it is Micron !

Mark LaPedus at EE Times reports that Mark Durcan, COO of Micron, at the recent IEEE ISS meeting in Half Moon Bay, commented that Micron is ”sampling products based on TSVs” and that “..mass production for TSV-based 3-D chips are slated for the next year or 18 months” and that “ Elpida, Samsung, and Toshiba are also in various stages of devising TSV-based 3-D chips” [link]

Sematech

Andy Rudack at Sematech updates us on the 3D IC committees put in place by the Semi / SEMATECH alliance.

CEA-Leti (the Laboratory for Electronics and Information Technology), a long time player and recognized leader in 3D IC technology development, dedicated its 3D-integration 300mm lines this week. CEA-Leti operates 8,000-m² state-of-the-art clean rooms, on 24/7 mode, on 200mm and 300mm wafer standards.

By adding this technology to its existing 300mm CMOS R and D line, Leti now offers thecomplete package of chip design, fabrication and 3D stacking and packaging on both 200mm and 300mm wafers.

The new line will allow prototyping capabilities in alignment, bonding, thinning, and interconnects in specific integration schemes for optimized die stacks and building efficient advanced-systems solutions at 300 mm.

For all the latest in 3D IC and Advanced packaging technology news, stay linked to IFTLEâ??¦â??¦


Continuing our look at presentations from the IEEE 3DIC Conference held in November 2010 in Munich.

IBM – 3D From a Server Perspective


Jeff Burns, IBM Dir of VLSI systems at Yorktown Heights, offered the perspective that 3D technology will require many changes to architecture, VLSI design, design IP, tools, technology, and manufacturing. In total this will be much larger in scope than a CMOS technology generation, rather it will be similar to the transition from bipolar to CMOS.

We have had extensive discussions on Cu-Cu direct bonding in the past [ see PFTLE 58, “Fisk, Buckner and Pasta on the North End”; PFTLE 26, “3D Practitioners Assemble at Ft McDowell”; IFTLE 6, "Copper-Copper and IMC Bonding Studies at 2010 ECTC” ]


We have also noted that Soitec has arrangements in place to scale up and offer for license CEA Leti technology in this area [ see PFTLE 89, “The French Connection”] .


At the 2010 IEEE 3DIC in Munich Soitec presented more details on this process. Direct bonding, unlike thermo compression or eutectic bonding, is performed at room temperature under atmospheric pressure and is based on molecular adhesion between surfaces in contact. Cu-Cu direct bonding requires flat surfaces with surface micro roughness of both Cu and oxide materials of less than 1 nm for successful bonding. Soitec indicates that standard damascene copper CMP does not provide the desired surface topography needed for a successful bonding process due to Cu pad dishing and oxide erosion. An optimized CMP process has been developed to limit the surface topography between the copper pads and the surrounding oxide dielectric. The special CMP surface preparation step leads to very smooth surfaces, the micro-roughness of both Cu and dielectric surfaces beings as low as 4-5Å. In addition the CMP renders the surfaces highly hydrophilic with the contact angle below 5°. The figure below shows that the planarization steps a) and b) are common steps in damascene BEOL while the step c) represents a specific step required for Cu-Cu direct bonding.

Kansai Univ – “All Wet” Fabrication Technology


Some readers have pointed out that it has been several months since I gave a lesson on American idioms ( phrases which do not mean what the sum of the individual words mean). Certainly this Kansai Univ paper gives me the opportunity to do that.


As many of you know Alchimer has been reporting for several years on their “wet process” for insulation, barrier and seed [ see IFTLE 11, “In and Around the Moscone part 2”].


I have teased them in the past saying that I would indicate that their process was the only “all wet” process available. In general English usage in the US “all wet” means “completely wrong”. Searching for the original meaning of this idiom reveals it has been in use since the 1920’s although the origin of the meaning is unclear. I am sure the Kansai researchers are not meaning to describe their “fully wet” fabrication process as “completely wrong”.


The Kansai process uses electroless deposition of thin barrier layers of NiB and CoB catalyzed by the use of nano particles catalysts (Au, Pd, Pt) which are adsorbed on the SiO2 insulation of the TSV sidewalls that have been treated with 3-APS (3-aminopropyl-triethoxysilane coupling agent). A conformal electroless Cu layer can then be deposited on the barrier layer without catalyst by displacement plating.


Copper migration through the CoB and NiB barrier layers were examined by resistivity changes upon annealing. Cu / NiB was found to be stable up to 300 C and Cu / CoB up to 400 C.


Now, the community appears to have two options for a “fully wet” barrier and seed process.


ASET – 3D Architecture for Processor – Memory Integration


Ito of ASET described two 3D interconnection architectures (block and sandwich stacking) for stacked processor-memory LSIs. In the sandwich configuration, memory chips and processor chips are stacked alternately, and vertical interconnects in each PU-CHIP are divided into two groups: interconnects


for global communications and interconnects for local 3Dmemory communications. Compared with block stacking configuration, sandwich stacking architecture shows 38% fewer vertical interconnects for the same throughput and reduces power consumption by 21%.

In another ASET presentation Aoki of ASET detailed their studies on copper / polymer hybrid bonding technology. We have seen copper / polymer bonding previously from both IMEC [ see PFTLE 10, “3D IC at the 2010 IEEE IITC” ].


For such bonding technology the surfaces of the metal and polymer must be globally flat. ASET applied a single damascene process for forming the hybrid bonding surface. To reduce surface-step height caused by copper dishing, a technology to co-planarize both the copper and polymer was developed. Polybenzoxazole (PBO) was used as the polymer for sealing bumps because it features positive-tone photosensitivity, high chemical resistance, and high thermal stability.

As has been expressed on IFTLE many times, full 3D IC requires: TSV, thinning and bonding. As of yet there is no real clarity as to who “owns” any of these technology although there have been many boisterous claims out there being made.


In 2006 while the industry was deep in the R and D phase of 3D IC technology, I wrote a piece concerning “posturing and positioning” as the first phase of 3D IC technology commercialization [ “Posturing and Positioning in 3-D IC’s”, Semiconductor Int. April 2007]. The premise was that the 3D IC announcements at the time by Intel, IBM, Samsung, NEC, Elpida were the beginning of commercialization, stage (1) or “the bragging stage” if you will, where technology companies like peacocks strut around showing their feathers and announcing “we are the best”.


Stage (2) “real commercialization” came in 2010 when Elpida/UMC [see IFTLE 8, “3D Announcements and Rumors”]and Samsung [see IFTLE 27, “The Era of 3D IC Has Arrived with Samsung Commercial Announcement” ] announced 3D IC based memory products (albeit for late 2011- 2012). The expectation is that this will cause further announcements from competitor companies attempting to keep up in the technology race , a pattern we saw recently in the introduction of TSV technology for CMOS image sensors [see PFTLE 46,“…..on Mechanical Bulls, Rollercoasters and CIS with TSV” ].

Stage (3) I would define as the period where standardization begins to occur, the infrastructure begins to “gel” and technology ownership begins to clarify. For multilayered, complex technologies like 3D IC technology ownership is usually determined in the courts. Dec 6th 2010 is the date that initiated the technology ownership determination for “oxide bonding” technology. This is when Ziptronix filed a complaint against TSMC and Omnivision in Federal Court alleging “willful and deliberate” infringement of several patents [ USP’s: 7,387,944; 7,335,572; 7,553,744; 7,037,755; 6,864,585; 7,807,549; ] owned by Ziptronix pertaining to low temperature oxide bonding. The original SST article can be found here [link]. In question here is the use of oxide bonding for backside illumination in CMOS image sensors [see PFTLE 40, “Backside Illumination (BSI) Architecture next for Next Generation CMOS Image Sensors”]


Most of the CIS manufacturers have moved to BIS technology per a recent market study by Yole Developpment [ see “ CMOS Image Sensors Technologies and Markets -2010”].


Instead of illuminating a CMOS image sensor from the top side (front) of the die, backside illumination (BSI) collects photons from the backside so the light enters the device unobstructed by the metal and dielectric layers of the interconnect structure as shown in the figure.

Cell phone camera image sensor suppliers Omnivision, Aptina Imaging, Toshiba, Samsung and STMicro also appear ready for BSI products to appear in early 2011. Yole expects BSI technology to be responsible for a little over $1B (~17% of CIS sales) in 2012.


TSMC has presented their latest BSI technology in the paper "A Leading-Edge 0.9μm Pixel CMOS Image Sensor Technology with Backside Illumination:Future Challenges for Pixel Scaling" at the 2010 IEDM. They describe the "device wafer runs through a planarization process and is bonded with a carrier wafer. The bonded wafer is then mechanically and chemically thinned down from the bottom side of the device wafer to the target thickness". The process in question is the wafer bonding process. The qustion raised by this complaint centers around whether the accused are using oxide wafer bonding for their OmniBSI® technology, if so, whether the the oxide surfaces are treated with plasma or other chemicals and whether the Ziptronix claims in their numerous patents on the topic are indeed valid. TSMC and its subsidaries Xintec and VisEra appear ready to deliver CMOS image sensor devices to Omnivision.


Chipworks has done reverse engineering on Omnivision products such as the OmniVision OV5642 1.4 μm, back side illuminated (BSI) 5 Mp CIS [link] and teardowns of communication devices such as the HTC EVO 4G Smart Phone which they found contained the OmniVision OV8812 8 Mp Image Sensor chip (below).

BSI technology requires a solution for handling thinned wafers. A typical solution is to direct oxide bond the sensor wafer front surface to another oxide coated wafer which can then serve as a permanent “handle wafer” for the thinning operation.


Direct oxide bonding processes require extremely smooth (0.5 nm RMS) and clean surfaces which are readily achieved with standard CMP. When such SiO2 surfaces are placed into contact, they initially form relatively weak “van-der-Waals” bonds. Subsequent heating to elevated temperatures is necessary to achieve high bond strength through the formation of covalent Si-O-Si bonds. The high thermal budget required for this condensation reaction to proceed ( typically greater than 800 C) is not suitable for most devices, however, modifying the surface chemistry allows the formation of chemical bonds at significantly lower temperatures.


Recent reports from EVG indicate that oxide bonding currently has 35% better placement accuracy and better throughput than polymer bonding as shown in Table [ see PFTLE 41, “3D Integration Stays HOT at Semicon West”]

Using oxide bonding for the “back-end, bonding to carrier step” would result in low temp, high throughput bonding would result in excellent CTE match and positional accuracy.


Ziptronix technology for BSI is centered around ZiBondâ??¢ which they claim allows one to achieve significantly higher bond energy between wafers after treatment with various surface “activating and terminating” processes. The direct oxide bonding, which is initiated at low temperature, is characterized by a very high bond energy between the surfaces. One example of Zibondâ??¢ simply requires a plasma treatment followed by an aqueous ammonium hydroxide rinse. By such surface treatments bond energies in excess of 1 J/m2 are reported.

Next week we will continue our look at presentations from the IEEE 3DIC in Munich.


For all the latest on 3D IC technology and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦..

Continuing with our discussions on presentations made at the 1st IEEE 3D IC Workshop in Austin.


NC State – TSV Test prior to stack


During wafer test, it is valuable to be able to determine which TSVs are likely to yield when used, and which are not. To detect failure in TSVs, an electrical test needs to be performed before 3D integration and chip packaging. Paul Franzon and co-workers at NC State propose three methods to test Through-Silicon-Vias (TSV) electrically prior to 3D integration: (1) sense amplification; (2) leakage current monitor; and (3) capacitance bridge methods. These tests detect one or both of two failure types, pin-holes and voids. The test circuits measure capacitance and leakage current of the TSVs, and generate 1 bit pass/fail signal. All these methods can be implemented for test-before-stacking, to attempt to increase assembled yield.


The sense amplification and the capacitive bridge test structures can estimate the TSV capacitance to test void defects. The capacitive bridge circuit is more sensitive but consumes more area than the sense amplifier sensor. The sense amplification method cannot detect voids isolating less than approximately ±10% of the TSV. The potential test escape rate is proportional to what percentage of TSVs that have voids isolating 10% of the TSV capacitance or less. The leakage current test circuit can measure the resistance of dielectric layer to test leakage defects with much more sensitivity than the sense amplifier method. All the simulation results above show that the parameters of TSVs can be tested by simple circuits and the measurement data can be streamed out serially by a scan chain.


TSMC – Electrical Tests for 3D IC with TSV


Chen and co-workers at TSMC have identified five main categories of “faults” (i.e. performance failure modes) in 3DIC TSV with microbumps:
1. Faults due to miss-alignment
2. Faults in the Cu pillar
3. Faults due to impurities
4. Faults due to substrate
5. Faults in the microbump


In terms of alignment, they report two possible failure issues. The type 1 failure is due to an alignment shift which results in smaller overlap area contact and thus higher resistance. The type 2 failure occurs when there is severe miss alignment and a complete open occurs.


The second category is related to the Cu TSV. Type 3 failures come from voids in the Cu TSV which may be caused by electromigration. The resistance in the TSV becomes larger and the RC delay increases. Type 4 failure occurs due to breakage in the TSV by improper handling or other procesing issues and will result in an open circuit. The type 5 failure is due to failure to completely fill the TSV. This will also increase delay due to the higher resistance.


The third failure mode is due to impurities during processing. Type 6 failure is due to impurities between the TSV and the microbump which increase the contact resistenace and thus the signal delay time. Type 7 failure is due to impurities between the microbumps which also increases the contact resistance and thus the signal delay.


The fourth and fifth failure modes deal with failures in the substrate and failures in the microbump. Type 8 failure is due to non uniformity in the insulation liner which can result in a leakage path from the TSV to the substrate. Type 9 failure results in an open circuit from Cu TSV delamination from the substrate due to the thermal stress of the process. Type 10 failure is due to deformation of the microbumps or the wafer warping and the separation of the two microbumps causing discontinuity. Type 11 failure is due to shorts between the two microbumps.


The Table below compiles failure modes vs required testing which includes continuity, resistance, capacitance, leakage and high frequency performance

Qualcomm


In a presentation covering DFT (design for test) Qualcomms Michael Laisne concludes that there are two primary defect classes: a) interconnect related defects and b) stress related defects. Either of which could manifest itself as a “stuck-at” or speed-related failure. He lists the main causes of interconnect-related defects as:


– substrate to TSV shorts,
– parasitic capacitance or resistance between the substrate and TSV causing speed-related failure,
– capacitive coupling between adjacent TSV causing both static and at-speed failures
– microbump opens and shorts, especially due to excessive warpage (opens) and misalignment (shorts)
– shorts due to interactions with TSV’s
– shorts and opens in the RDL


ST Ericsson


Stephane Lecomte of ST Ericsson reports that the first 3D TSV application they foresee in cell phones is wide IO memory which is currently undergoing JEDEC standardization. We have recently reported on similar conclusions from Nokia [see IFTLE 19,”Semicon Taiwan 3D Forum Part 2” ]


Most of the manufacturing issues, they feel are still tied up in the business model / infrastructure / supply chain issues that have yet to be resolved. They feel that boundary scan testing will be defined within JEDEC, but that BIST remains very manufacturer dependent.

ARM

ARM presented an interesting slide depicting the Mb/sec requirements for several common devices (shown below)

Certainly we would all agree that 3D IC test has come a long way over the last few years. All of the major design and test companies are now focused on integrating products so that full 3D IC integration can become a reality in the near future. For those worried that 3D still looks like it is many years away, I refer you back to the Qualcomm presentations that indicate that first generation products do not appear to have significant roadblocks in either thermal, design or test. It is for the future generation partially or fully reconfigured structures that major changes in design and test will be needed [ see IFTLE 9, “3D in and Around the Moscone”

Lastlyâ??¦..One of the IEEE 3D Test Conference chairs requested that IFTLE model their midnight black knit shirt, so below we find our “mature” model showing off his shirt while reading the New York Times # 1 non fiction best seller “Handbook of 3D Integration” by Garrou, Bower and Ramm, available at Amazon.com !

For all the latest in 3D IC and advanced packaging in 2011 and beyond, stay linked to IFTLEâ??¦â??¦..