The Semicon Taiwan 3D Technology Forum was chaired by Ho-Ming Tong, General Manager and CTO for ASE. Speakers included representatives from Yole, Nokia, Qualcomm, UMC, SIliconware, Verigy, Applied, ITRI, IME and Sematech. The next two blogs will cover significant material from this meeting.

ASE

Dr. Tong, who some say coined the term "2.5D" for the use of silicon or glass interposers with TSV, indicated that this technology “..is ready to move to the next stage” Tong expects commercialization of 2.5D chip technology to take place in two years.

Tong notes that 2.5D IC should not be regarded as a transitional integration technology. 2.5D will enable packaging of chips in the 32-22 nm nodes where the fragile mechanical stability of the low-K dielectrics used in these products will require their bonding to an intermediate silicon interposer before final placement in a standard package.

Tong believes that commercialized products made using 2.5D IC and 3D IC technologies, including smartphones and computing applications, will hit the market in the next five years. This last comment made headlines at several news outlets [ link], which Quoted Dr. Tong as saying “ Despite tremendous progress in recent years, 3D IC with through silicon vias (TSVs) still presents significant challenges in cost, design, manufacturing, test and supply chain readiness and the technology is still three to five years away from mass production”.

After checking with Dr. Tongs colleagues in ASE I have been assured that these comments were meant to indicate that widespread use in products is still 3-5 years out but that ASE stands by the recent roadmap they shared at Semicon West this summer [ see IFTLE 9 “3D In and Around the Moscone Part 1” ] which indicates that 2.5 D readiness is imminent and full 3D for wide IO DRAM / logic bonding would be coming in the 2011 timeframe.

UMC

Shan-Chieh Chien, VP of ATD at UMC called 3D stacking with TSV the “big elephant” technology for foundries. UMC, which recently announced an alliance with Elpida and Powertech [ see IFTLE 8 “3D Infrastructure Announcements and Rumors” ] commented that logic + wide IO DRAM stacking will occur in 2011-2012 consistent with the comments of his other Asian colleagues. UMC also sees a significant future for silicon interposers indicating that UMC will use their Cu dual damascene BEOL process for passive device and fine pitch RDL on these interposers.

We’ll finish up looking at the 2010 Semicon Taiwan 3D Forum next week

the CMOS Image Sensor Market

A new IC Insights image sensor market report forecast that CMOS image sensors sales will rise 34% in 2010 to $5.2 billion from ~ $3.9 billion in 2009. Between 2009 and 2014, CMOS image sensor sales are projected to increase at a 17% compound average growth rate (CAGR), reaching $8.3 billion by 2014. CMOS image sensors dominate portable systems applications, such as camera phones, webcams in notebook computers, and other embedded cameras in handheld products, but higher-speed CMOS imagers are also being aimed at automotive systems, medical equipment, and wireless video security networks.

Assembly and Packaging Roadmap
Organized in nine major sections:

• Difficult Challenges
• Single Chip Packaging
• Wafer Level Packaging
• System Level Integration in Package (SiP)
• 3D Integration
• Packaging for Specialized Functions
• Advanced Packaging Elements
• Environmental Issues
• Cross-Cut Issues

Singe Chip Packaging:

Fine pitch copper wirebond has been introduced into the mainstream industry. [ see PFTLE 86 “Adv Pkging From Rimini”, 07/12/2009 ] Replacement of Au wire by Cu is the last frontier for packaging materials cost saving. They note that advanced nodes and low k materials will demand finer diameter wires for Au as well as Cu (below the 18 um being practiced today). While copper wirebond has been in use for power devices with 50 micron diameter wires and low IO counts, fine pitch Cu wirebond is a more recent development. Using fine pitch Cu wire diameters of less than 25 µm requires improvements in understanding of wire properties, IMC formation, wire bonding processes and equipment development and control for wire oxidation. Pd coated wire has been introduced to eliminate the need to for forming gas in production. The WB figure shown here is of a 18 µm Cu wirebond in a PBGA.

For flip chip pitch, lower than 150 µm, has been limited by availability of high-volume cost-effective substrates and high-volume defect-free underfill processes. Application for plated wafer bumping including copper pillar wafer bumping is being expanded beyond microprocessor applications.

For applications beyond the microprocessor, graphics and game processors, FC CSP packages have been developed for applications with smaller die, lower IO array pitch and low profile small package format requirements. Primary driver has been the mobile market application, and drop test is the important reliability requirement.

Molding for FC devices
A new approach presently under investigation is underfill molding (MUF) for flip chip in package solutions. While thin packages are prone to warpage, and chips with low-κ dielectrics are more sensitive to stress low modulus molding compounds are in development to minimize the problems.


Substrates
Package substrates are both the most expensive element of packages as well as the factor limiting package performance. Advances in package substrate technology will be required to meet the cost and performance projections of the Roadmap.

Handheld consumer devices are driving ever thinner substrates and finer patterns on laminate. Total thickness has been reduced to 100 µm based on 60 µm cores in high volume manufacturing. 50 µm cores and 35 µm prepregs are available but cost is still high and improvements in handling equipment are needed to take these materials to high volume. Below 35 um thickness, new high performance low cost material is required to meet the market needs.

As copper thickness shrinks in traces and plated through holes, these features become susceptible to thermal expansion in the z-direction. CTE in z-direction must be reduced to 20 ppm/degree for core materials. The typical approach is to add filler to the resin system which typically degrades other material properties or introduces process disadvantages.

Low Î?? dielectric substrates for FC-BGA are needed for high-speed transmission Incremental materials improvements enable κ~3.4 today. Materials are available with κ down to 2.8 but are still far too expensive for broad market application. There is no cost effective solution available for κ~2.5 and below. For such low κ, new reinforcement materials need to be developed as well.

Wafer Level Packaging
Wafer level packaging (WLP)is being defined as a technology in which all of the IC packaging process steps are performed at the wafer level. The original WLP definition required that all package I/O terminals be continuously located within the chip outline (fan-in design) producing a chip size package. From a systems perspective, under this definition, the limitation on WLP was how many I/O could be placed under the chip and still have a board design that can be routed.

However, new packages have recently been introduced which are “Fan-out” WLP. They are processed by placing individual sawn die into a polymer matrix that has the same form factor as the original silicon wafer. These “Reconstituted” wafers are then processed through all of the same processes that are used for “real” silicon wafers, and sawn into separate packages. The die are spaced in the polymer matrix such that there is a perimeter of polymer surrounding each placed die. This area can be used during redistribution (RDL) to “fan out” the RDL to an area larger than the original die. This allows a standard WLP solder ball pitch to be used for die that are too small in area to allow this I/O pattern without ‘growing” the die to a larger size.

Thus WLP technology can now include traditional wafer level chip size packages (WLCSP), Fan-out wafer level packages, wafer level packages with TSV, wafer level packages with Integrated Passive Devices (IPD)s. This is shown in the figure below.

SiP
The roadmap now defines SiP as “…a combination of multiple active electronic components of different functionality, assembled in a single unit, which provides multiple functions associated with a system or sub-system. A SiP may optionally contain passives, MEMS, optical components, and other packages and devices”. These may be arranged horizontally, vertically or be embedded as shown below.

Not much here that we haven’t already covered extensively in PFTLE and IFTLE. Below is a nice graphic from Intel showing the evolution of memory on logic (without timelines).

There is extensive discussion on chip package co design which the roadmap concludes will be necessary to reduce time to market and cost. There are also discussions on the specific requirements for opto, Rf, MEMS, automotive and LED packaging – the latter certainly being a hot topic recently. [ see PFTLE 123 “LCDs Coming to a Lighting Application Near You”, 3/18/2010 ]

One complaint I have about this document (same as the interconnect document) is that there are far to few primary references contained in the document ( 20 total) Roadmaps like this should be well documented with primary sources.

For all the latest on 3D IC and advanced packaging stay linked to IFTLE…….

……. previous PFTLE blogs are located at www.pftle.net……..

TSV metrology requirements include measurement of :
– depth
– Top and Bottom CD
– Via Pitch
– Sidewall angle (top and Bottom)


Nanda-tech
Nanda claims their optical inspection tool can be used for more than just identification of surface imperfections. The figure below shows inspection application areas in a number of 3D IC unit operations are possible.

ITRI demonstrated the use and of a spectral reflectometer for high density through-silicon via (TSV) inspection. The non-destructive solution can measure TSV profile diameters as small as 5 um and aspect ratios greater than 13:1. The measurement precision is in the range of 0.02 um. Typical data is compared to a SEM cross section in the fig below.

Albany nano

Pofessor Kong described his studies using X-ray tomography to determine voiding in TSVs.

McDonough of Albany presented Si stress measurements were carried out using far- field micro-Raman spectroscopy. Stress fields associated with isolated TSVs and TSV arrays were both evaluated. While results for calculated and measured were excellent for isolated TSV the TSV arrays were more complex to interpret. Ditto the anneal of stress after processing.


Olympus
Vadim Mashevsky of Olympus showed that infrared laser microscopy techniques allow imaging through bulk silicon for 3D Interconnect metrology.
Applications include:
– Overlay metrology of bonded wafers
– Overlay metrology of front side to back side wafer patterns
– Thickness metrology
– Bonded interface defect detection and defect metrology

Veeco

Novak of Veeco offers the following comments on Infrared illumination based microscopes. They :
– “See” through silicon
– Allows for alignment of stacked wafers
– Poor lateral and vertical resolution due to
– Long wavelength
– High measurement noise


White light confocal systems have:
– Good lateral resolution
– Lower vertical resolution for high aspect ratios
– Slow vertical scans
– Does not “see through silicon”


White light interferometric optical profiler
– Good lateral resolution
– Excellent vertical resolution even at high aspect ratio
– Fast vertical scans
– Mature technology, in production for decades
– Does not “see through silicon”


Below is shown 3 micron via array (vias inverted for clarity) :
Average Depth: 34.63 μm; Average width: 3.4 μm;

There are some Major events coming this fall which are exclusively focused on 3D IC including :

ASET / Tohohu Univ
Koyanagi-san Tohoku Univ went over the Japan ASTET consortiums Dream chip program [ we have discussed this program goals about a year ago, see PFTLE 104 “3D IC From the Land of the Rising Sun” 10/30/2009] .
Koyanagi showed the ASET roadmap which shows 3D stacked DRAM memory in 2012-2013.

IMEC


Paul Marchal of IMEC examined both the yield and reliability and the electrical impact of TSV induced stress. The fig below shows the possible components of stress in the 3D structure. Their goal is to set up a simulation flow to analyze stress and its impact in a packaged 3D chip-stack

Stress impact on transistor performance is shown below:

All other things being constant, smaller TSV diameter lowers stress.

IMEC’s strategy for mitigating TSV induced stress challenges:

– Process technology optimization for TSV induced stress
– Compact mechanical model, integrated in the design flow

Remaining challenges:

– combining local and global stress
– TSV impact on advanced device topologies

Qualcomm

Riko Radojcic was a busy man at Semicon speaking at both the Alchimer [ see IFTLE 11 “3D in and Around the Moscone – Part 2”, Aug 2010] ] and Sematech workshops . His assessment of 3D stress risks is shown in the slide below.

For all the latest in 3D ICs and advanced packaging information stay linked to IFTLEâ??¦â??¦â??¦â??¦..

EVG


Markus Wimplinger , Corp Tech and IP Director, shared that 3D and TSV have been a main focus for EVG during the downturn and they feel these technologies have served them very well financially.


Wimplinger sees the only 300 mm 3D line in production is the ST Micro CIS (CMOS Image Sensor) line. Line qualification is underway right now for several customers who should be finished by 4Q 2010. He predicts that some but not all of their customers will be ready for production in the 2011-2012 timeframe and that most of them will be in Asia. Those that are furthest along actually have process ground rules out to selected key customers but have not widely distributed them yet. He also notes that W2W bonding is on the upswing again after bottoming out (vs D2W) around 12 months ago.


Verigy


Mark Allison, VP of strategic Marketing indicated that Verigy is a member of both the IME (Singapore) and ITRI (Taiwan) 3D consortia. Allison reported that some of their customer base were exerting pressure for 3D IC test solutions while others appeared to be waiting to see further clarity in the infrastructure.


Some of the TSV test challenges that they have found include:


– TSV size vs probe capabilities


– making sure the DFT (design for test) probe pads don’t add capacitance and inductance to the TSV


– handling the complex functionality of the stack


Verigy is looking into putting DFT structures on interposer which is lower cost real estate.


Equipment Heavyweights Have a Change of Heart


In the past few years PFTLE and IFTLE have documented the move of Equipment heavyweights Applied Materials and Novellus into the here-to-fore shunned area of packaging. [See PFTLE 72 “Samsung 3-D ‘Roadmap’ That Isn’t”, 4/16/2009; IFTLE “…on Finding the Beef and Finally Addressing 3D IC”, June 2010]


It wasn’t so long ago that such heavyweights snubbed their nose at the packaging market. Well, the upcoming end to scaling and Moore’s Law (as we know it) sure have turned things around [ see PFTLE “IC Consolidation, Node Scaling and 3D IC”, 03/03/2010]. Topics like 3D TSV and WLP are now the darlings of the equipment industry.


Don’t get me wrong, having the big boys set their sights on packaging and 3D with TSV is positive and developments that they come up with can only improve things for all of us in the long run. With reports that 300 mm 3D lines are going intro place around the world “as we speak” it was to be expected that both would be in “full court press” mode at Semicon – and they were.


AMAT


Dr. Randhir Thakur, executive vice president and general manager of Applied’s Silicon Systems Group announced that Applied could now offer customers “…a complete toolset for all TSV manufacturing flows encompassing etch, CVD, PVD, ECD, wafer cleaning and CMP,” said. , Applied’s Maydan Technology Center and their activity at institutes like IMEC and ITRI can only help customers develop “.. a smooth transition from R and D to volume production” as they put it.


Novellus


Novellus introduced new models of the company’s VECTOR PECVD, INOVA PVD, and GxT photoresist strip systems specifically designed for WLp and 3D.


The newly-introduced SABRE 3D system addresses void-free filling, reduced copper overburden, and improved fill uniformity at higher throughputs. SABRE 3D’s modular architecture can be configured with multiple plating and pre-or-post-treatment cells for a variety of packaging applications including TSV, pillar, RDL, under-bump metallization, and eutectic and lead-free micro-bumping using materials such as copper, tin, nickel, and tin silver.


The INOVA 3D PVD reportedly provides “…superior copper sidewall coverage and ultra-low defects in high aspect ratio TSVs”. The ion-induced PVD approaches reportedly reduces the manufacturing cost of consumables for the TSV PVD process step by greater than 50 percent.


The VECTOR 3D system is reportedly able to deposit low-temperature films such as silicon nitride diffusion barriers and silicon oxide isolation and passivation layers.


The G3D photoresist strip system has been designed to quickly remove thick (20-100 micron) photoresists used in the manufacture of RDLs and pillars and to achieve residue-free strip and clean of high aspect ratio TSVs.


FPGA 3D IC Rumors


With their highly repetitive structure, FPGAs have been a natural application space for 3D IC technology although no details have been announced or published anyone on the subject. Recently there have been rumors of real work going on out there that I would be remiss I not sharing with you.


In June, in his blog on chip design magazine (link), Ed Spurling reported that although Xilinx refused to comment, “a half dozen industry sources familiar with its efforts” reported that Xilinx is developing 3D for its FPGAs. IFTLE will take it one better than that and report to you that the rumored site for Xilinx activities is Samsung. No proof here either, and no confirmation from either party just the strong rumor. Although Samsung remains deathly silent on all activities concerning 3D, trust me they will be a player.


For all the latest in 3D IC and advanced packaging technology, news and rumors stay linked to Insights From the Leading Edge, IFTLE…

ITRI

The ITRI Ad-STAC program has been discussed previously [ see PFTLE 105 “Taiwanese Focus on 3D IC”, 11/06/2009; PFTLE 99 “3D IC at ITRI”,09/24/2009. At the Suss “3D Bonding and Thin Wafer Handling “ workshop Yu-Hua Chen, Deputy Div Director, announced that there is now a team of 150 fully engaged in 3D design, build and test.

Per their previous announcements they still appear to be on time to have their 300 mm 3D line qualified by the 4Q 2010 as shown below.

Their roadmap now shows CPU + RAM stacking and memory stacking in the 2011 / 2012 timeframe, in sinc with other Pacific rim foundries and assembly houses.

In 2008 PFTLE welcomed the IEEE IITC to the 3D IC bandwagon [ see PFTLE 37 “ IITC on the 3D Integration Bandwagon”,07/07/2008 ]. In each subsequent year they have continued to expand 3D IC coverage with quality papers as is shown below for their recent June 2010 meeting.

IMEC


IMEC gave several interesting presentations at the IITC. One paper focused on the high temperature characterization of TSV capacitance, leakage and resistance. They conclude that although TSV capacitance marginally increases with the increase in temperature, TSV depletion behavior can still be exploited to reduce TSV capacitance at higher temperatures. TSV leakage measurements show that TSV oxide integrity is preserved even at higher temperatures (150C). The increase in TSV resistance matches estimations based on the positive temperature coefficient of Cu resistivity. The limited impact of temperature on measured power-delay characteristics of 2D / 3D ring oscillator circuits is due to the increase of TSV capacitance.


Another paper examined the impact of TSV – transistor proximity. Copper filled TSVs (see figure below), with a diameter of 5.2 μm and a length (height) of 22 μm, were designed and fabricated close to MOSFETs. The impact of a single TSV was examined on both PMOS and NMOS with a channel length of 0.13 μm to ~0.15 μm. For each transistor, a TSV was placed next to its active region. The distance between the edge of the channel and the TSV varied from 1.1 to 1.6 μm.

All the MOSFETs with TSVs in close proximity demonstrated normal functionality. Compared to the transistors without TSVs in proximity, no performance degradation of key transistor parameters was identified. These results show that at a minimum distance of 1.1 μm from MOSFETs, the current TSV structure has little impact on the device operation in this technology. Transistors surrounded by multiple TSVs also revealed no significant performance shift in comparison to the control cases with no TSV.


Thermal cycling between -55 and 125ºC was applied to the stacked dies. After 1000 cycles, all devices were functional and no degradation was observed with TSV proximity.


IMEC concludes that the ‘middle-TSV’ approach implemented on 130-nm CMOS technology platform has no significant impact on the electrical operation of MOSFETs and demonstrates good long-term reliability but wisely cautions that depending on technology and layout, this might not always be the case. Similar conclusions were reached previously [ see PFTLE 122, “3D IC at the IEEE ISSCC”, 03/12/2010 ]


IMEC has shared information about using a polymer TSV insulation previously [ see PFTLE 125, “3D IC at Fort McDowell”, 03/28/2010 ] In their most recent presentation they detail the processing for backside TSV of 50 and proposes two separate constructions for 50 and 100 µm thicknesses, (a) vs (b), as shown in the figure below.

For the 100 um process, a chamfered shape is used to avoid stress buildup at the Si corner. A sloped cavity is first etched then a second a vertical etch is done using a Bosch process IE process. Then a spin-on-dielectric from JSR is used to conformally coat the TSV. Polymer is then removed from the bottom of the hole by litho and dry etching. They indicate that this process is less likely to scale since it needs a big enough hole to do litho at the bottom of it.


Possible dimensions for these two TSV construction options are shown below.

QUALCOMM

Gu of Qualcomm shared possible integration challenges for high volume production. The interesting figure below shows the Si area in mm2 lost due to occupancy of TSVs as a function of aspect ratio for 100 um thick Si. They conclude that to maintain low Si area penalty ( i.e 2 mm2), the TSV aspect ratio should be approx 10 for 10,000 vias. This is true, but assumes the requirement of a 100 µm Si thickness.


As you may know as a reader of PFTLE [ see PFTLE 68, “Like Swallows Returning to San Juan Capistrano”, 03/20/2009 and PFTLE 44, “Upcoming 3D Integration events; Issues with the ITRS 3D Roadmaps”,09/11/2008], this author prefers a thinner Si (i.e. 30 um) which would lead to 1/3 the AR for the same lost area. Given all other things being equal lower AR always will equal lower cost.

More interesting to IFTLE are the comments Gu makes about plasma damage, namely “If the TSV is connected to a transistor during processing (which they are once the TSV are exposed from the backside – IFTLE), the plasma charge from wafer backside may damage the device gate oxide on wafer front side. Protection diodes are usually employed to protect transistor from plasma charge in the wafer front side. However, backside plasma light can be blocked from reaching the front side diode, which makes the protection diode less effective. Minimizing the plasma charge on backside process is important.” Certainly something to keep in mind.

IBM


Emma of IBM has been thinking about 3D IC and how to use them for a very long time. At IITC he gave a very interesting perspective on where we are in 3D IC integration and where we should be going.


Emma contends that in most commercial cases today, 3D is simply a packaging technique used to simplify integration. That its principle applications have been in high-volume markets where the costs of assembly are most important (such as cameras and cell phones); in markets where the physical size of the end-product is fixed (e.g., DIMMs); and in markets where both the power density and the inter-chip signal density are low. He contends that the goals of these applications are to make the end products simpler by integrating multiple components into a single stack, thereby enabling a single package and simplifying the subsequent assembly processes. It provides a way to continue the density scaling for a given footprint.


….modularity


Modularity, Emma contends, can be one of the main advantages by providing a potentially simpler design flow. For example, large IP blocks (or even layers in disparate technologies from different vendors) can be incorporated into such a stack. This requires that there be well-defined interfaces, communication protocols, and technology ground-rules that will be common to all of the individual components (i.e. standardization) . He believes that the overheads associated with such well defined infrastructures, rules, and protocols are potentially lower than those required to compose the system using a traditional 2D approach.


This has the effect of “volumizing” those subsystems, which reduces their costs and their times-to-market. In addition, he proposes that 3D can allow clocking, power delivery and control, and test-related logic to be incorporated in a more modular way.


…bandwidth


Scaling through-silicon-via (TSV) size and pitch in 3D enables high bandwidth and low latency interconnects among multiple device layers. This can enable massive internal bandwidth.


He also suggests we need to be considering system applications in which”… the logical elements of a system can be physically co-located in the {x,y} dimensions so that unprecedented bandwidth in the {z} dimension can allow the stack to do types of computation that would not be fathomable in 2-space”.


When taking a look at the constraints of 3D IC Emma offers that when combining differently constrained layers into a stack, 3D integration “…will tend to impose the combined constraints on each individual layer. Among those constraints are: (i) a shared power envelope (the amount of current drawn in any layer can impact the other layers when there are shared Power/GND TSVs), (ii) a shared thermal envelope for heat removal, and (iii) interactions between the layers in the form of noise (the reduced distances in the vertical direction, especially in thinned silicon will exacerbate noise issues). While not a major problem in low power systems, the first two constraints can be quite challenging for high-power and high power-density applications, like microprocessors”


He concludes “Today, the obvious uses for 3D are the ones in which the costs, power, interconnectivity, and profit margins are all fairly low. 3D offers some clear advantages in the future integration of systems: better volumetric density, lower raw power, smaller component count, and better modularity. But realizing these advantages requires solving a new set of problems in (literally) a new dimension.”

3D IC at the Upcoming IEEE CICC

Trying to keep you updated on what’s coming as well as what has transpired, I would be remiss if I didn’t mention the upcoming design activities at the IEEE CICC (Custom Integrated Circuits Conf) sponsored by the Solid State Circuits (SSC) and Electron Device (ED) societies.


3D veteran Rakesh Patel, who is now working on 3D IC with Global Foundries, informs IFTLE that CICC will be addressing 3D from a design perspective in their upcoming Sept 19-22 meeting in San Jose [link]

Their 3D forum will include:
– “3D Integration Infrastructure: Requirements to Support High Volume Production”, W. R. Bottoms, Third Millennium Test Solutions
– “3D IC – TSV Micro-bump Modeling and Design Implementation Tools”, Vassilios Gerousis, Cadence,
– “3D Packaging Evolution from an OSAT Perspective”, Raj Pendse, STATS ChipPAC
– “Challenges and Emerging Solutions for Testing TSV-Based Three-Dimensional Stacked ICs”, Erik Jan Marinissen, IMEC


In addition session 15 entitled “3D Design Considerations” will address the major 3D design topics of the day.

For all the latest on 3D IC and advanced packaging stay linked to Insights From the Leading Edge, IFTLE…………………


….Past issues of PFTLE can be accessed at http://www.pftle.net/……..

IC Insights

Bill McClean, who correctly predicted the 2010 bull electronics market in March of 2009 [see PFTLE 67 “IC Insights Predicts Fast Industry Rebound at IMAPS Global Business Council”,3/15/2009 ] stated that Samsung is now spending 20% of the worlds electronics capex (~ 10B$). He sees the next downturn coming in 2013 and does not see 450 mm wafers coming till post 2015.

Proteus Biomedical

Proteus biomedical CEO Andrew Thompson during his presentartion on how microeletronics was going to affect the medical community shared the remarkable fact that the earths 7B people only 3B of them have a pair of shoes but there are 5B cell phone subscribers! That’s a lot of barefoot people talking on the phone! Another interesting

GlobalFoundries

Gregg Bartlett, Sr VP of Technology and R&D in his plenary presentation on “The Centrality of Silicon” showed 3D IC becoming essential at the 22 nm node as shown below.

Qualcomm


Qualcomm has become one of the strongest corporate advocates for 3D IC in the world. For some of their recent activity see [PFTLE 126 “Adv Pkging at the IMAPS Device Pkging Conf”, 04/01/2010; PFTLE 125 “3D IC at Ft McDowell”, 03/27/2010 ].


At the TechXSpots “Bridging the Gap” session Steve Bezuk of Qualcomm shared his views on how 3D fits into mobile device roadmaps. Bezuk’s comment that “The constraints of the low power, mobile market present no fundamental technical barriers to 3D TSV technologies” was music to a 3D advocates ears.


He used the PFTLE “4 Horseman of the apocalypse” concept [ see PTFLE 102, “The 4 Horsemen of 3D IC”, 10/16/2009 to make his point as seen below. He notes that:
– for the heterogeneous stacking designs that they are looking at today, 2D tools appear to suffice
– no thermal issues have been uncovered that do not alreadyexist for todays 2D designs
– todays sophisticated SoC test proceedures looks thik they can do he job for entry level 3D products

Qualcomms Riko Radojcic, speaking at the Alchimer 3D workshop, echoed the earlier remarks of Steve Bezuk that Qualcomm can “manage the current design flow using current EDA products”. Riko, as a designer, indicated that 3D IC was a matter of managing choices and interactions (which are listed below) .

Riko indicated that thermal and mechanical stress considerations need to be incorporated into design enablement and stack design signoff.


ASE

Calvin Cheung at the Suss “3D Bonding and Thin Wafer Handling “ workshop indicated that ASE sees consumer markets driving the roadmaps towards 3D IC. Cheung indicated that facial recognition and bio-sensing for medical diagnostics were two applications that customers have indicated would be highly desirable if integrated on their PDAs.


During a panel Q&A session Chueng indicated that TSMC will be driving the initial use of interposers and that ASE was on board. “We will need interposers to bond 28 nm low K dieâ??¦right now it is impossible to stack such mechanically unstable materials into a stable 3D stack” Cheung also sees interposers serving as a platform for IPD (integrated passive devices) which will allow them to get decoupling caps closer to where they are needed and that “Graphics chip sets will also require solutions where the power is not channeled through the memory”, making them another potential application for interposers. At least for the first generation products.


Rich Rice from ASE at the Bridging the Gap TechXSpot, presented the following IC cost breakdown from a recent Prismark report which indicates that Packaging and assembly constitutes 16% of total shipped silicon cost.

Amkor


Bob Lanzone, at the Suss “3D Bonding and Thin Wafer Handling “ workshop indicated that Amkor is now focusing heavily on the unit operations required to handle TSV middle wafers from foundries. They have backed off their focus on backside TSV fabrication which Bob feels is well under control. Bob says that F2F (face-to-face) CoC (chip-on-chip) technology has been qualified with Cu/Sn IMC down to 40 um pitch. Below 40 um he feels Amkor will move to some form of direct Cu-Cu bonding.

Coming soon:
– 3D IC at the IEEE IITC
– Semicon coverage of Suss, Alchimer, Yole, ITRI, EVG, Sematech, Novellus, Verigy
– 3D at the design automation conference
– A look at the ITRS new roadmapâ??¦..and much more

For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edge…    
For past PFTLE blogs go to www.pftle.net)