Tag Archives: IC

The Last Technology Roadmap

After many delays, the last ever International Technology Roadmap for Semiconductors (ITRS) has been published. Now that there are just a few companies remaining in the world developing new fab technologies in each of the CMOS logic and memory spaces, each leading-edge company has a secret internal roadmap and little motivation to compare directions within fiercely competitive commercial markets. Solid State Technology Chief Editor Pete Singer covered these developments in his blog post early last year.

Rachael Courtland at IEEE Spectrum provides a great overview of the topic and interviews many of the key contributors to this last global effort. The article provides a nice graph to show how the previously predicted (in the just-prior ITRS 2013 edition) continued physical gate length reduction of CMOS transistors is now expected to stop in 2020. Henceforth, 3D stacking of transistors—perhaps built with arrays of Gate-All-Around NanoWires (GAA-NW)—will be the only way to get more density in circuitry but it will come with proportionally increasing cost.

As Gary Patton, CTO and SVP of Worldwide R&D for GlobalFoundries, mentioned during the 2016 Imec Technology Forum in Brussells, “We will continue to provide value to our customers to be able to create new products. We’re going to innovate to add value other than simple scaling.”

The 17 International Technology Working Groups (ITWGs) were replaced in 2015 by 7 Focus Teams in the last ITRS: System Integration, Heterogeneous Integration, Heterogeneous Components, Outside System Connectivity, More Moore, Beyond CMOS and Factory Integration. The final reports from each Focus Team are available for free download from Dropbox.

The IEEE Rebooting Computing Initiative, Standards Association, and the Computer Society announced a new International Roadmap for Devices and Systems (IRDS) on 4th of May this year. Paolo Gargini is leading this work that began with the partnership between the IEEE RC initiative and the ITRS, with aspiration to build “a comprehensive end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software.”

In parallel to the IRDS efforts, the Heterogeneous Integration Roadmap activities will continue as sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI and the IEEE Electron Devices Society (EDS). Bill Bottoms is leading this collaboration with other IEEE Technical Societies that share interest in the Heterogeneous Technology Roadmap as well as to organizations outside IEEE that share this common vision for the roadmap.

—E.K.

Broadening Scope of SEMICON

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Once upon a time, SEMICONs were essentially just for semiconductor manufacturing business and technology, and predominantly CMOS ICs. Back when we followed public roadmaps for technology to maintain the cadence of new manufacturing nodes in support of Moore’s Law, it was sufficient to focus on faster transistors connected with tighter wires. Now in an era that is at least partially “More-than-Moore”—as we like to refer to heterogeneous integration of non-CMOS technologies into commercial ICs—SEMICON West 2016 will focus on technologies beyond silicon CMOS such as MEMS and flexible organic semiconductors.

Alissa Fitzgerald, founder and managing member of AM Fitzgerald & Associates, will present on some of these themes Wednesday afternoon during the “What’s Next in MEMS and Sensors: Innovations to Drive the Next Generation of Growth” session (Track 2) of SEMICON’s Advanced Manufacturing Forum. Much of that growth is expected to be in sensors, microprocessors, ultra-low-power supplies, and communications chips to support the Internet of Things (IoT) connected by high-speed 5G data networks.

Flexible/Hybrid Electronics Forum at SEMICON West this year includes two full days of excellent presentations on new technologies that include thinned device processing, device/sensor integrated printing and packaging, and reliability testing and modeling. The following is the full list of forums this year:

Advanced Manufacturing,
Advanced Packaging,
Extended Supply-Chain,
Flexible/Hybrid Electronics,
Silicon Innovation,
Sustainable Manufacturing,
Test, and
World of IoT.

Partner programs include focused forums discussing trends in technology, markets, and the business of commercial IC fabrication. The industry’s default center of “More Moore” R&D is now imec in Belgium, and invited attendees of the imec technology forum (ITF) in San Francisco happening on July 11th the day before the start of SEMICON West will learn about the latest results in CMOS device shrinking from finFETs to nanowires. The next evening, French R&D and pilot manufacturing center CEA-Leti will lead a workshop detailing how to partner with the organization to bring sensor-based “More-than-Moore” technologies to market. Thursday morning will feature the Entegris Yield Breakfast Forum discussing the need for new materials handling solutions due to “Yield Enhancement Challenges in Today’s Memory IC Production.”

As the official event website summarizes: We’ve deepened our reach across the full electronics manufacturing supply chain to connect you with more key players — including major industry leaders like Cisco, Samsung, Intel, Audi, Micron, and more. New players, demand generators, systems integrators, and emerging industry segments — all connecting in one place. Keynote presentations will be provided by Cisco Systems, Kateeva, and Oracle.

—E.K.

Eloquent Executives Ecosystem Expositions

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#cmc,#confab,#namedropping

With dimensional scaling reaching economic limits, each company in the IC fab industry must rely upon trusted connections with customers and suppliers to know which way to go, and the only way to gain trusted connections is through attending live events. Fortunately, whether you are an executive, and engineer, or an investor, there is at least one must-attend event happening these days to keep you informed.

We should always start with SEMI (sponsor of SemiMD, personal friends for many years) who has always represented the gold standard for trade-shows, executive events, and manufacturing symposia around the world. I attended my first SEMICON/West in 1988, and have since attended excellent SEMICONs in Europe, Japan, Korea, China, and Singapore. This year’s SEMICON gathering in San Francisco will feature a nearly 50% increase in the number of technical sessions.

SEMI ran another excellent Advanced Semiconductor Manufacturing Conference (ASMC) in Albany this month, featuring keynotes by visionaries such as “Nanoscale III-V CMOS” by MIT Professor Jesus A. del Alamo. The panel discussion “Moore’s Law Wall vs. Moore’s Wallet, and where do we grow from here,” was moderated by industry veteran Paul Werbaneth, now with Intevac. It is clear that we will reach economic limits of scaling well before the physical limits.

Materials technology and supply-chain solutions to extend economic limits were discussed by Intel’s VP of Technology and Manufacturing Tim Hendry in a keynote at the Critical Materials Conference (CMC) held this year in Oregon in early May, as produced by Techcet CA (I am also an analyst with Techcet and co-chair of this event, while Solid State Technology was a media sponsor). David Thompson, Senior Director, Center of Excellence in Chemistry, Applied Materials showed that despite the inherent “Agony in New Material Introductions – minimizing and correlating variabilities” is possible with improved collaboration throughout the supply-chain.

The Imec Technology Forum in Brussells this month (Solid State Technology was a media sponsor) could best be described with Lake Wobegone hyperbole that all the women were strong, the men were good-looking, and everyone was above average. The big news is imec acquiring iMinds for greater synergies when integrating the latter’s algorithms with imec-ecosystem hardware for application-specific solutions. Gary Patton, now CTO and SVP of Global R&D for GLOBALFOUNDRIES, reminded everyone at ITF of the inherent speed constraints of the copper wires and low-k dielectrics needed to connect IC transistors, “As I’ve often said, It’s like you have a Ferrari but you’re towing a boat if you don’t address the interconnect delay issues.” Regardless, Patton confidently declares that, “We will continue to provide value to our customers to be able to create new products, and we will innovate in ways other than simple scaling.”

At ITF, a video was shown of imec president Luc van den Hove interviewing Gordon Moore at his beachfront home in Hawaii. Moore has always been humble and claims no special ability to forecast trends. “It would not surprise me if we reached the end of scaling in the next decade,” said Moore. “I missed the importance of the PC, and I missed the importance of the internet. Predicting the future is a difficult job and I leave it to someone else.”

Wally Rhines seemed able to predict the future when he eloquent expounded upon Moore’s Law as a special-case learning-curve in his presentation at ITF. Rhines will provide one of the keynote addresses at the ConFab in Las Vegas this year (Solid State Technology’s home event, co-sponsored by SEMI and by IEEE-CPMT). Executives from the global industry will gather to hear insights and analysis on the challenges facing all companies in the ecosystem, as we search for profitable pathways in a more complex landscape.

—E.K.

Trefonas Earns 2016 Perkin Medal

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The Society of Chemical Industry (SCI), America Group, announced on May 5, 2016 that Peter Trefonas, Ph.D., corporate fellow in Electronic Materials at Dow Chemical Co (NYSE:DOW), has won the 2016 SCI Perkin Medal. This honor recognizes Trefonas’ contributions in the development of chemicals that enable microlithography for the fabrication of microelectronic circuits. Trefonas will receive the medal at a dinner in his honor on Tuesday, September 13, 2016, at the Hilton Penn’s Landing Hotel in Philadelphia.

Trefonas made major contributions to the development of many successful products which are used in the production of integrated circuits spanning device design generations from 2 microns to 14 nanometers. These include photoresists, antireflectant coatings, underlayers, developers, and ancillary products. At the most recent SPIE Advanced Lithography conference he was part of a team that presented on the use of a resolution extension material, “Chemical trimming overcoat: an enhancing composition and process for 193nm lithography.”

He is an inventor on 61 US patents, has over 25 additional published active U.S. patent applications, is an author of 99 journal and technical publications, and is a recent recipient of both the 2014 ACS Heroes of Chemistry Award and the 2014 SPIE Willson Award. His research career began at Monsanto, and moved via acquisitions by Shipley, Rohm&Haas, and Dow.

—E.K.

RFID Playing Cards “Best Product” at Printed Electronics Europe

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Cartamundi, imec and Holst Centre (set up by imec and TNO) recently won the Best Product Award at Printed Electronics Europe for their ultra-thin plastic RFID technology integrated into Cartamundi’s playing cards. In each card, the RFID chip has a unique code that communicates wirelessly to an RFID reader, giving the cards in the game a unique digital identity. The jury recognized the potential of this technology to enhance printed electronics applications for the Internet-of-Things (IoT), as well as being a gamechanger <RIMSHOT> for the gaming industry.

Chris Van Doorslaer, CEO of Cartamundi, said, “The new technology will connect traditional game play with electronic devices like smartphones and tablets. As Cartamundi is committed to creating products that connect families and friends of every generation to enhance the valuable quality time they share during the day, this technology is a real enabler.” Imec and Cartamundi engineers will now explore up-scaling of the technology using a foundry production model.

“This is a thrilling development to demonstrate our TOLAE electronic technology integrated in the product of a partner company. TOLAE stands for Thin, Oxide and Large-Area Electronics”, stated Paul Heremans, department director of thin-film electronics at imec and technology director at the Holst Centre. “Our prototype thin-film RFID is thinner than paper—so thin that it can be invisibly embedded in paper products, such as playing cards. This key enabling technology will bring the cards and traditional games of our customer in direct connection with the Cloud. This achievement also opens up new applications in the IoT domain that we are exploring, to bring more data and possibilities to applications such as smart packaging, security paper, and maybe even banknotes.”

—E.K.

Omhi kept us Ultra-Clean

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Sadly, I just recently learned from the UCPSS 2016 website that Ohmi-sensei—Professor Doctor Tadahiro Ohmi—passed away in Sendai on 21 February 2016. As the guru of ultra-clean technology, he established the global Ultra Clean Society in 1988, founded the International Symposium of Semiconductor Manufacturing (ISSM) in 1992, served as program committee member of the UCPSS between 1992 and 2006, and was an IEEE Fellow. Ohmi was a Professor of New Industry Creation Hatchery Center at Tohoku University, after serving as a Professor at the Electronic Engineering Department, School of Engineering at Tohoku U.

Ohmi was most famous for asserting that IC manufacturing yield could be 100% if only every tool and tube in the fab were built with ultra-clean surfaces, and if all direct-materials and fluids flowing in the fab were ultra-clean. In the 1980s when IC designs and fab processes were relatively simple and HVM yields were in the 30-60% range, huge improvements came from removing “random” particles from dirty surfaces. Soon enough by the mid-1990s “clean enough” was found to be the pragmatic response to the experience of diminishing returns after yields were in the 90% range. Most famously for posterity, in 1993 Ohmi edited “Ultraclean Technology Handbook: Ultrapure Water, Vol.1”.

I first met him when UltraClean Technology, Inc. (UCTT) was founded in California in 1996 to weld ultra-clean steel from parent company Mitsubishi in a Class-1 cleanroom, and he was the genius bringing his vision of a better world to the rest of us. However, eventually UCTT separated from Mitsubishi and added Class-100 and Class-1000 assembly areas to provide “clean enough” technology…heresy to the Guru of ultra-clean; I never met him again when I worked for the company as a product manager in 2004.

As covered by EETimes in 2002, Ohmi could clearly see that something new was going to be needed in fab technology, but his vision for a way forward was an unrealizable dream:

Ohmi said his comprehensive process, from design through chip making, would create devices with 10 times better performance than today’s chips. At the same time, he said, it would squeeze design and production time to 1/40, clean room space to 1/5 and production cost to 1/10 of what’s now required.

Throughout his career he continued to look for breakthroughs to enable new generations of semiconductor manufacturing technology, recently supervising a project to develop a “next-generation flat panel display.”

An extraordinarily prolific inventor, his name is on an astonishing 592 issued US patents, based on 795 US applications filed, the most recent on December 21st of last year.

—E.K.

Andy Grove blessed us all

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Andy Grove, the man who codified the commercial IC industry dynamic as “Only the Paranoid Survive” died yesterday at the age of 79. His instinctive paranoia derived from his tragic experiences while growing up in Hungary, as referenced by Wikipedia in the prolog to “Swimming Across: a Memoir”:

By the time I was twenty, I had lived through a Hungarian Fascist dictatorship, German military occupation, the Nazis’ “Final Solution,” the siege of Budapest by the Soviet Red Army, a period of chaotic democracy in the years immediately after the war, a variety of repressive Communist regimes, and a popular uprising that was put down at gunpoint. . . [where] many young people were killed; countless others were interned. Some two hundred thousand Hungarians escaped to the West. I was one of them.

Grove was responsible for guiding Intel in the 1980s through the amazingly risky yet ultimately wildly successful strategy of abandoning memory chip production as part of a diversified product portfolio to “bet the company” on microprocessors. In the September 1997 issue of Solid State Technology, I wrote an article titled “DRAM fab strategies in Asia” that summarizes why and how US companies like Intel strategically abandoned DRAM production:

In the 1960s, US companies created the IC manufacturing industry and enjoyed virtually unchallenged world dominance through the 1970s. Japanese IC companies, though at first the junior companies in low-margin and foundry partnerships, rose to challenge the more senior US companies in the 1980s. By the latter half of the 1980s, Japan effectively owned the DRAM business and Japan`s outstanding success in IC production can be directly traced to early US manufacturing partnerships. One strategy played out by US companies with portfolios of memory chip designs was outsourcing of DRAM production to Korean companies. In so doing, US companies committed their futures to non-DRAM products such as microprocessors, DSPs, and ASICs.

Few executives have sufficient vision while leading a work-force with sufficient discipline to be able to re-invent a company in such a way. The capital equipment investments needed to create a leading-edge IC fab have always been daunting, and as Intel employee #3 who had led engineering Grove was able to see a way to leverage strategic R&D to ensure that leading-edge IC product functionalities would pull in sufficient demand to keep the fabs full. Not only did the fabs stay full, but the x86 microprocessor profit margins allowed Intel to grow to annual sales of $25 billion by the time he was replaced as CEO by Craig Barrett in 1998.

The San Jose Mercury News and EETimes have published wonderful additional remembrances of his life. Andy Grove blessed our industry by being a living example of engineering excellence and legit leadership.

—E.K.

SAQP Specs for 7nm finFETs

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As discussed in my last Ed’s Threads, lithography has become patterning as evidenced by first use of Self-Aligned Quadruple Patterning (SAQP) in High Volume Manufacturing (HVM) of memory chips. Meanwhile, industry R&D hub imec has been investigating use of SAQP for “7nm” and “5nm” node finFET HVM, as reported as SPIE-AL this year in Paper 9782-12.
The specifications for pitches ranging from 18 to 24 nanometers are as follow:

7.0nm Critical Dimension (CD) after etch,
0.5nm (3sigma) CD uniformity (CDU), and
<1nm Line-Width and Line-End Roughness (LWR and LER) assuming 10% of CD.

“Pitch walk”—variation in final pitch after multi-patterning—results in different line widths, and can result in subsequent excessive etch variation due to non-uniform loading effects. To keep the pitch walk in SAQP at acceptable levels for the 7nm node, the core-1 CDU has to be 0.5nm 3sigma and 0.8nm range after both litho and etch. In other presentations at SPIE-AL this year, the best LER after litho was ~4nm, improving to ~2nm after PEALD smoothing of sidewalls, but still double the desired spec.

The team at imec developed a SAQP flow using amorphous-Carbon (aC) and amorphous-Silicon (aSi) as the cores, and low-temperature Plasma-Enhanced Atomic-Layer Deposition (PEALD) of SiO2 for both sets of spacers. Bilayer DARC (SiOC) and BARC were used for reflectivity control. Compared to SAQP schemes where the mandrels are only aSi, imec claims that this approach saves 20% in cost due to the use of aC core and the elimination of etch-stopping-layers.

—E.K.

Litho becomes Patterning

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Once upon a time, lithographic (litho) processes were all that IC fabs needed to transfer the design-intent into silicon chips. Over the last 10-15 years, however, IC device structural features have continued to shrink below half the wavelength of the laser light used in litho tools, such that additional process steps are needed to form the desired features. Self-Aligned Double Patterning (SADP) schemes use precise coatings deposited as “spacers” on the sidewalls of mandrels made from developed photoresist or a sacrificial material at a given pitch, such that after selective mandrel etching the spacers pitch-split. SADP has been used in HVM IC fabs for many years now. Self-Aligned Quadruple Pattering (SAQP) has reportedly been deployed in a memory IC fab, too.

An excellent overview of the patterning complexities of SAQP was provided by Sophie Thibaut of TEL in a presentation at SPIE-AL on “SAQP integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications.” Use of a spacer-on-spacer process flow—enabled by clever combinations of SiO2 and TiO2 spacers deposited by Atomic Layer Deposition (ALD)—requires the following unit-process steps:
1 193i litho,
2 ALD spacers,
2 wet etches, and
4 plasma etches.

Since non-litho processes dominate the transfer of design-intent to silicon, from first principles we should consider such integrated flows as “patterning.” Etch selectivity to remove one material while leaving another, and deposition dependent on underlying materials determine much of the pattern fidelity. Such process flows are new to IC fabs, but have been used for decades in the manufacturing of Micro-Electrical Mechanical Systems (MEMS), though generally on a patterning length scale of microns instead of the nanometers needed for advanced ICs. R&D labs today are even experimenting with Self-Aligned Octuple Patterning (SAOP), and based on the legacy of MEMS processing it certainly could be done.

—E.K.

Controlling Polymers to Tune TFTs

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Thin-film transistors (TFT) created using only additive process steps could create new low-cost ICs with functionalities beyond silicon, but only if we understand how to control structures at the molecular level. Thin films of conjugated polymers such as poly(3-hexylthiophene) (P3HT) can provide useful conductivity when the electron mobilities are controlled within as well as between molecules. In producing TFTs using such organic macromolecules, we must rigorously control the deposition and annealing processes so that the right molecules line up in the right order.
Peter F. Green, Professor of Chemical Engineering, Macromolecular Science and Engineering at the University of Michigan, and his team fabricated ~55 nm thin films of P3HT using resonant-infrared matrix-assisted pulsed laser evaporation (RIR-MAPLE), as well as conventional spin-casting. The films produced by MAPLE show a higher degree of structural disorder, with localized trap sites that reduce mobility out-of-plane by an order of magnitude compared to spin-cast films.

(Source: Peter Green, University of Michigan)

The Figure shows that despite the disorder of MAPLE-deposited P3HT, enhanced carrier density at the dielectric interface allows TFTs to exhibit similar in-plane mobilities to those built using conventionally spin-coated films. TFTs were top-contact, bottom-gate designs on 300nm thermal oxide on highly doped silicon. In-plane carrier mobilities of MAPLE-deposited versus spin-cast films were 8.3 versus 5.5 (×10 -3 cm2/V/s). In principle, the ability to independently control in- and out-of-plane mobilities allows for the fine tuning of TFT parameters for different applications.
—E.K.