Tag Archives: IC

Apple Fab Speculation

Apple Corp. recent purchased an old 200mm-diameter silicon wafer fab in San Jose capable of creating as small as 90nm device features. Formerly owned and operated by Maxim, the US$18.2M purchase reportedly includes nearly 200 working fab tools. Some people outside the industry have speculated that Apple might use this fab to do R&D on the A10 or other advanced logic chips, but this old tool-set is completely incapable of working on <45nm device features so it’s useless for logic R&D.

As reported at EETimes, this old fab could be used for the R&D of “mixed-signal devices, MEMS and image sensors and for work on packaging.” Those who know do not speak, while those who speak do not know…I do not know so I’m free to join the public speculation. Mixed-signal and MEMS processing would require major re-tooling of the line, but this 15-20 year-old tool-set is nearly turn-key for wafer-level packaging (WLP). With minimal re-tooling, this line could produce through-silicon vias (TSV) or through-mold vias (TMV) as part of Fan-Out WLP (FO-WLP).

Our friends at ChipWorks have published a detailed tear-down analysis of the System-in-Package (SiP) used in the first generation Apple Watch; it contains 30 ICs and many discretes connected by a 4-layer printed circuit board (PCB). Significant power and performance improvements in mobile devices derive from stacking chips in such dense packages, and even greater improvements can found in replacing the PCB with a silicon interposer. With Apple pushing the limits on integrating new functionalities into all manner of mobile devices, it would be strategic to invest in WLP R&D in support of application-specific SiP design.

—E.K.

MPU Cores and Legal Boors

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As reported by The Register, AMD has been sued by a customer who claims that the number of Bulldozer cores in some Opteron and FX microprocessor (MPU) chips are fewer than advertised. The claim is based on the argument that a “real” MPU core has it’s own floating point unit for calculations, and that consumers were misled by product claims. I am not a lawyer (IANAL) and have no connections to either side in this case, but AMD’s website (http://www.amd.com/en-us/products/processors/desktop/fx#) now clearly indicates that cores share a Floating Point (FP) scheduler.

The Figure shows that the confusion is due to the design of the Bulldozer microarchitecture wherein a pair of cores is called a module, and each pair shares a branch prediction engine, an instruction fetch and decode stage, a floating-point math unit, a cache controller, a 64K L1 instruction cache, a microcode ROM, and a 2MB L2 cache. The lawsuit claims, “Because AMD did not convey accurate specifications, tens of thousands of consumers have been misled into buying Bulldozer CPUs that do not conform to what AMD advertised, and cannot perform the way a true eight core CPU would (i.e., perform eight calculations simultaneously).”

This is analogous to someone buying a car with a V8 internal combustion engine, and then suing the manufacturer because there are only 4 fuel injectors and not all cylinders fire simultaneously. The claim that “true” multi-cores must be capable of functioning simultaneously is like claiming that “true” multi-cylinder engines must be capable of all cylinders firing simultaneously. AMD has officially responded with the statement that, “We believe our marketing accurately reflects the capabilities of the Bulldozer architecture which, when implemented in an 8-core AMD FX processor, is capable of running eight instructions concurrently.” There seems to be little legal difference between “simultaneously” and “concurrently” but IANAL.

Sure, there’s a technical difference and likely a slight performance benefit to direct fuel injection into each cylinder, but raw performance is only one aspect of the design trade-offs between performance and cost and reliability. Sharing 1 fuel injector between 2 cylinders often provides an optimum of performance/cost/reliability in internal combustion engines. Sharing 1 FPU between 2 logic cores seemingly provides an optimum of performance/cost/reliability in CPUs.

—E.K.

Thermoplastically Deformable Electronic Circuits

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Philips is testing a technology developed by imec and CMST (imec’s associated lab at Ghent University) to create low-cost 3D LED packages. As shown at last month’s International Microelectronics Assembly and Packaging Society (IMAPS 2015) meeting, these thermoplastically deformable electronic circuits are already being integrated by Philips into LED lamp carriers, a downlight luminaire, and a omnidirectional light source.

Miniature dome test vehicle with integrated low power LEDs, (a) circuit before forming, and (b) circuit after vacuum forming using a 40mm half-sphere mold. (Source: imec)

The technology is based on meander-shaped interconnects, which are patterned using standard printed circuit board (PCB) production equipment and then sandwiched between 2D thermoplastic polymer (e.g. polycarbonate) sheets. The Figure shows one example in final form after vacuum thermoforming into a 40mm half-sphere mold.
This is a glorious example of “elegant engineering” where a clever combination of materials and processes has been integrated with highly desirable characteristics: low tooling cost, low direct material cost, easily scalable from lab to fab, low product weight, and high product resilience. This seems to represent almost a new industrial product category that combines a “package” and a PCB.

—E.K.

Nowhere Near Room Temp Superconductors

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On-chip metal interconnects limit IC speed in many advanced design today, and with signal delay proportional to the product of the resistance (R) of wires and the capacitance (C) of dielectric insulation, wires with R lower than that of copper (Cu) metal would significantly improve IC performance. We know of superconductors—materials with zero resistance to electrical current flow—but only at “critical temperature” (Tc) well below 77°K, and so there has been an ongoing quest by scientists to find a material with Tc above room temperature of 298°K.

Sadly, after 4 years and nearly 1000 materials tested, a team of 6 Japanese research groups led by Hideo Hosono from the Tokyo Institute of Technology found no room temperature superconductors. They did find 100 previously unknown superconductors with Tc <56°K, and they published crystal structures and phase diagrams of all materials studied to help other researchers avoid now known dead-ends (DOI: 10.1088/1468-6996/16/3/033503).

Other researchers continue to explore the possibilities of using one-dimensional (1D) carbon-based materials such as carbon-nano-tubes (CNT) or graphene as on-chip conductors. So far, there are extreme difficulties in controlling the growth of such 1D structures within interconnect patterns, and additional challenges with forming ohmic contacts between CNT and Cu lines across billions of connections in a modern IC. More science is seemingly needed to find new paths before the engineers can explore those paths to find better solutions. Meanwhile…for the next few years at least…expect Cu metal to be the continued choice for nearly all multi-level metal interconnects on chip.

—E.K.

300mm ams Fab Bet on IoT

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Leading-edge IC fab investments are multi-billion-dollar risky bets. Insufficient demand for ICs dooms the line to economic failure regardless of the quality of design and manufacturing. Thus, it is a big deal that Austrian-headquartered ams AG—world leader in production of IC sensors, RFID chips, and power-supplies—has announced plans to set up a new silicon wafer manufacturing line in up-state New York.
To date, ams’ leading fabs run 200mm diameter silicon wafers, while the new line that is planned for 2017 will run both 200mm and 300mm diameter. With ~2.4x more chips/wafer, the commitment to a 300mm line is a sign that ams expects a major increase in demand for certain products. The vision for the Internet of Things (IoT) is that ubiquitous “smart objects” will be able to connect and exchange useful information without human direction, and the foundation of smart is sensing combined with decision-making. While other companies provide logic chips to allow for decision making, ams provides chips that can sense the world in various ways.
The investment into Marcy, New York represents a bet that there will be sustained demand for analog and sensor chips to provide much of the “smarts” for the IoT. Thus ams is planning to spend >US$2 billion over the next 20 years on capital purchases, operating expenses, and other investments in the facility. Pete Singer provides all the details in his thorough report.
—E.K.

Cross-point ReRAM Integration Claimed by Intel/Micron

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The Intel/Micron joint-venture now claims to have successfully integrated a Resistive-RAM (ReRAM) made with an unannounced material in a cross-point architecture, switching using an undisclosed mechanism. Pilot production wafers are supposed to be moving through the Lehi fab, and samples to customers are promised by end of this year.
HP Labs announced great results in 2010 on prototype ReRAM using titania without the need for a forming step, and then licensed the technology to Hynix with plans to bring a cross-point ReRAM to market by 2013. SanDisk/Toshiba have been working on ReRAM as an eventual replacement for NAND Flash for many years, with though a bi-layer 32Gb cross-point ReRAM was shown at ISSCC in 2013 they have so far not announced production.
Let us hope that the folks in Lehi have succeeded where HP/Hynix and SanDisk/Toshiba among others have so far failed in bringing a cross-point ReRAM to market…so this may be a “breakthrough” but it’s by no means “revolutionary.” Until the Intel/Micron legal teams decide that they can disclose what material is changing resistance and by what mechanism (including whether an electrical “forming” step is needed), the best we can do is speculate as to even how much of a breakthrough this represents.
—E.K.

Single-electron Molecular Switch 4nm Across

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A molecule rotating on the surface of a crystal can function as a tunnel-gate of a transistor, as shown by researchers from the Paul-Drude-Institut für Festkörperelektronik (PDI) and the Freie Universität Berlin (FUB), Germany, the NTT Basic Research Laboratories (NTT-BRL), Japan, and the U.S. Naval Research Laboratory (NRL). Their complete findings are published in the 13 July 2015 issue of the journal Nature Physics. The team used a highly stable scanning tunneling microscope (STM) to create a transistor consisting of a single organic molecule and positively charged metal atoms, positioning them with the STM tip on the surface of an indium arsenide (InAs) crystal.
Dr. Stefan Fölsch, a physicist at the PDI who led the team, explained that “the molecule is only weakly bound to the InAs template. So, when we bring the STM tip very close to the molecule and apply a bias voltage to the tip-sample junction, single electrons can tunnel between template and tip by hopping via nearly unperturbed molecular orbitals, similar to the working principle of a quantum dot gated by an external electrode. In our case, the charged atoms nearby provide the electrostatic gate potential that regulates the electron flow and the charge state of the molecule.”

(Top) STM images of phthalocyanine (H2Pc) molecule rotated from a neutral (50 pA, 60 mV; left) to −1 charged states (50 pA, −60 mV; centre and right) on InAs(111) surface using a ~4nm across hexagonal array of charged indium adatoms surrounding the H2Pc to create rotational energy minima, and (Bottom) schematic model of H2Pc rotation relative to the InAs lattice resulting in the electrostatic gating of tunneling to an STM tip vertical to the device. (Source: Nature Physics)

The Figure shows that the diameter of the device is ~4nm, so by conservative estimation we may take this as the half-pitch of closest-packed devices in IC manufacturing, which leads to pitch of 8nm. As a reminder, today’s “22nm- to 14nm-node” devices feature ~80nm transistor gate pitches (with “10nm node” planning to use ~65nm gate pitch, and “5nm node” ICs expected with ~36nm gate pitch). Thus, these new prototypes prove the concept that ICs with densities 100x more than today’s state-of-the-art chips could be made…if on-chip wires can somehow connect all of the needed circuitry together reliably and affordably.
—E.K.

Electronic Materials Specifications and Markets

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At SEMICON West this year, July 14-16 in San Francisco, the Chemical and Gas Manufacturers Group (CGMG) Committee of SEMI have organized an excellent program covering “Contamination Control in the Sub-20nm Era” to occur in the afternoon of the 14th as part of the free TechXPOT series. Recent high-volume manufacturing (HVM) developments have shown much tighter IC control specifications in terms of particles, metal contaminants, and organic contaminants. The session will present a comprehensive picture of how the industry value chain participants are collaborating to address contamination control challenges:
1. IDM / foundry about the evolving contamination control challenges and requirements,
2. OEM process and metrology/defect inspection tools to minimize defects, and
3. Materials and sub-component makers eliminating contaminants in the materials manufacturing, shipment, and dispensing process before they reach the wafer.

Updated reports about the markets for specialty electronic materials have recently been published by the industry analysts at TechCet, including topics such as ALD/CVD presursors, CMP consumables, general gases, PVD targets, and silicon wafers. Strategic inflection points continue to appear in different sub-markets for specialty materials, as specifications evolve to the point that a nano-revolution is needed. One example is TechCet’s recent reporting that 3M’s fixed-abrasive pad for CMP has been determined to be unable to keep up with defect demands below 20nm, and is undergoing an orderly withdrawal from the market.

As in prior years, SEMICON West includes many free and paid technology sessions and workshops, the Silicon Innovation Forum and other business events, as well as a profusion of partner events throughout the week.

—E.K.

ALD of Crystalline High-K SHTO on Ge

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Alternative channel materials (ACM) such as germanium (Ge) will need to be integrated into future CMOS ICs, and one part of the integration was shown at the recent Materials Research Society (MRS) spring meeting by John Ekerdt, Associate Dean for Research in Chemical Engineering at the University of Texas at Austin, in his presentation on “Atomic Layer Deposition of Crystalline SrHfxTi1-xO3 Directly on Ge (001) for High-K Dielectric Applications.”

Strontium hafnate, SrHfO3 (SHO), and strontium titanate, SrTiO3 (STO), with dielectric constants of ~15 and ~90 (respectively) can be grown directly on Ge using atomic layer deposition (ALD). Following a post-deposition anneal at 550-590°C for 5 minutes, the perovskite films become crystalline with epitaxial registry to the underlying Ge (001) substrate. Capacitor structures using the crystalline STO dielectric show a k~90 but also high leakage current. In efforts to optimize electrical performance including leakage current and dielectric constant, crystalline SrHfxTi1-xO3 (SHTO) can be grown directly on Ge by ALD. SHTO benefits from a reduced leakage current over STO and a higher k value than SHO. By minimizing the epitaxial strain and maintaining an abrupt interface, the SHTO films are expected to reduce dielectric interface-traps (Dit) at the oxide-Ge interface.

Much of the recent conference has been archived, and can now be accessed online.

—E.K.

Bottoms-up ELD of Cobalt Plugs

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As reported in more detail at Solid State Technology, during the IEEE IITC now happening in Grenoble, imec and Lam showed a new Electroless Deposition (ELD) cobalt (Co) process that is claimed to provide void-free bottoms-up pre-filling of vias and contacts. The unit-process is intended to be integrated into flows to produce scaled interconnects for logic and DRAM ICs at the 7nm node and below. Co-incidentally at IITC this year, imec and Lam also presented on a new ELD copper (Cu) process for micron-plus-scale through-silicon vias (TSV).

The bulk resistivities of metals commonly used in IC fabrication are as follows (E-8 Ω⋅m):
Cu – 1.70,
Al – 2.74,
W – 5.3, and
Co – 5.8.
Of course, the above values for bulk materials assume minimal influence of grain sizes and boundary layers. However, in scaled on-chip interconnect structures using in today’s advanced ICs, the resistivity is dominated by grain-boundaries and interfacial materials. Consequently, the resistivity of vias in 7nm node and beyond interconnects may be similar for Cu and Co depending upon the grain-sizes and barrier layers.

The melting temperatures of these metals are as follows (°C):
Al – 660,
Cu – 1084,
Co – 1495, and
W – 3400.
With higher melting temperature compared to Cu, Co contacts/plugs would provide some of the thermal stability of W to allow for easier integration of transistors and interconnects. Seemingly, the main reason to use Co instead of W is that the latter requires CVD processing that intrinsically does not allow for bottom-up deposition.

—E.K.