By Dick James, Senior Technology Analyst, Chipworks

On the Monday afternoon at IEDM the key paper for me was the Intel/Micron talk on their 3D-NAND flash part (paper 3.3), which is currently sampling to customers. Samsung put their V-NAND flash on the market last year, but that uses charge-trap technology, whereas the Intel/Micron device has adapted conventional floating gate technology to the vertical direction.

This is the first-generation product, with 32 active tiers plus additional layers for dummy wordlines and source and drain select gates. A vertical channel surround-gate structure is used for the flash cells. The CMOS decoders and sense-amps are situated under the NAND flash array, which saves significantly on die area. It appears that this product will be a 256-Gb memory, or 384 Gb when the TLC version is introduced. Die size is 168.5 mm², giving a bit density of 1.52 and 2.28 Gb/mm² for the MLC and TLC devices.

Intel/Micron 3D-NAND flash die (Source: Intel/Micron/IEDM)

The wordlines/control gates are horizontal polysilicon layers with an ONO inter-poly dielectric, and the floating gates are also polySi. The vertical channel and tunnel dielectric are formed in holes etched through a horizontal polySi/oxide stack.

EM cross-section of vertical-channel 3D-NAND structure (Source: Intel/Micron/IEDM)

The process is shown below; the cell hole is first etched through the wordline tiers, and then the control gate is recessed back and the inter-poly dielectric is formed. The floating gate is then deposited, and etched back to form an isolated floating gate in each cell; the tunnel-oxide is formed, and the polySi channel is deposited to line the hole in the stack.

Process flow of vertical-channel 3D-NAND stack formation (Source: Intel/Micron/IEDM)

(Source: Intel/Micron/IEDM)

An image of the full stack is shown on the right; I see 38 wordline layers, plus a thick polySi layer at top and bottom of the stack, presumably for the drain and source select transistors. There are two tungsten metal layers below the stack for the decoders and sense-amps, and also the wordline drivers; and it looks like the M3 bitline is also tungsten. There is another metal level above used for power busses and global interconnects, but we don’t know if that is copper or aluminum.

Putting the wordline drivers under the array is claimed to keep the wordlines short, but it raises some questions – how are the wordlines contacted from below? Do we have the sort of staircase at the ends of the wordlines that we saw in the Samsung V-NAND, and could it be inverted? (Can’t imagine that!)

The vertical channels contact what looks like a polySi sourceline at the base of the stack; it’s a bit clearer in this schematic:

Schematic of base of 3D-NAND stack (Source: Intel/Micron/IEDM)

While the NAND cells are floating gate cells, we can see that the source and drain select devices are single gate oxide transistors.

The larger size of the cell improves the performance since it has a higher cell capacitance – more electrons can be stored, and a better natural Vt distribution (~50%) is achieved. (Note that at 20nm planar, less than 10 electrons gave 100mv Vt shift!)

Number of electrons/100mV Vt shift (left), and Vt distribution vs 20-nm planar flash (Source: Intel/Micron/IEDM)

The cell geometry also means that the cell/cell interference is reduced – again, comparing to the 20nm planar chip;

Cell/cell interference of 3D-NAND vs planar NAND (Source: Intel/Micron/IEDM)

We will see what the commercial part looks like when we get our hands on one, likely in the first few months of next year. Unfortunately there are no scale bars on any of the images, so we have no feel for what the actual dimensions are; though probably not too different from the Samsung, which is classed as a 40nm device.

There are actually not too many features in common with the Samsung chip – vertical stacking with 32 active layers, and that’s about it. Otherwise, charge-trap technology vs floating-gate; polySi wordlines vs tungsten; metallization below the stack, vs none; and maybe a completely different way of accessing the wordlines.

For now, we wait and see!

By Dick James, Senior Technology Analyst, Chipworks

In the second week of December, the good and the great of the electron device world will make their usual pilgrimage to Washington D.C. for the 2015 IEEE International Electron Devices Meeting. To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.”

That’s a pretty broad range of topics, but from my perspective at Chipworks, focused on the analysis of chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy.

In the last few weeks I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.

Saturday/Sunday

Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorials on a range of leading-edge topics:

• Electronic Control Systems for Quantum Computation, David DiVincenzo, Aachen University
• Advanced CMOS Device Physics for 7nm and Beyond, Scott Thompson, University of Florida
• Thin Film Transistors for Displays and More, Tom Jackson, Penn State University
• Nanoscale III-V Compound Semiconductor MOSFETs for Logic, Luca Selmi, University of Udine
• RF and Analog Device Technologies, Anthony Chou, GlobalFoundries
• Implantable MEMS and Microsystems for Neural Interface, Eusik Yoon, University of Michigan

The first three are from 2.45 – 4.15, and the remainder from 4.30 – 6.00. This year I hope to make it to Scott Thompson’s session on 7 nm and below, and possibly the GF tutorial on RF/analog at 4.30.

On Sunday December 14^th, we start with the short courses, “Emerging CMOS Technology at 5 nm and Beyond” and “Memory Technologies for Future Systems”.

Last year the process short course was “Challenges of 7nm CMOS Technology”, so I guess we’ve moved on a node; though I still need convincing that the 10-nm process architectures are locked down as yet – the launches seem to be sliding a bit, to the back end of 2017, based on the quarterly stock analyst meetings that I’ve perused.

The 7-nm course has been organized by Yuan Taur, UCal San Diego, winner of the J.J. Ebers Award three years ago. He introduces it bright and early, at 8.30 a.m.

The first session is a four-hander on Device Options and Tradeoffs, with Mark Lundstrom and Xingshu Sun, Purdue University, Dimitri Antoniadis, MIT and Shaloo Rakheja, NYU presenting – we’ll see how they sub-divide the topics, but this is the time to get the low-down on the I-V Theory of Nanotransistors, III-V MOSFETs, Nanowire FETs, Band-to-Band Tunnel FETs, and 2D channel Materials.

Second up is Bruce Doris of IBM, discussing Process Integration Challenges and to follow, his IBM colleague Takeshi Nogami goes into more detail about BEOL Process Challenges . Starting the afternoon Krishna Saraswat (Stanford University) looks at Emerging Interconnect Technologies, then we have Tony Yen from TSMC reviewing Advanced Lithography (maybe we’ll get a hint of when EUV will become real), and the last talk of the day is by Asen Asenov (Glasgow University/Gold Standard Simulations) on Variability and Design for Manufacturability.

It now seems that 10nm, and probably 7nm, will be silicon-based, so we’ll see what the guys predict for 5nm; new channel materials, nanowire transistors, and how will they integrate into a manufacturable process? What will be the effects on the performance of the basic logic blocks? What will device reliability be like with the potential new materials/structures? Hopefully we’ll find out here!

The era of big data, and the big systems that will result from the internet of things, will put huge demands on the associated memory systems, so a memory review and look-ahead is appropriate; Dirk Wouters of Aachen University has organized the parallel course on our Sunday.

We start at a more civilized 9.15, and at 9.30 Rob Aitken of ARM is up with a look at the System Requirements for Memories, setting the context for the subsequent sessions. The next two talks review conventional memories; DRAM by Changyeol Lee, from SK Hynix, and Flash by Youngwoo Park of Samsung Electronics, with lunch in between.

Emerging memory is split into ReRAM and PCM, with Daniel Ielmini, (Politecnico di Milano) instructing, and STT-MRAM, from Thibaut Devolder, a CNRS Research Associate, Universite Paris-Sud.

I would call both courses a full day, seeing as we finish at ~5.30 p.m., but it’s worth sticking around to the end.

If you have the stamina, at 6.00 Leti is hosting a Devices Workshop at the Churchill Hotel, across the street from the Hilton. 

Monday

Monday morning we have the plenary session, with three pertinent talks on the challenges of contemporary electronics:

• Moore’s Law at 50: Are we planning For retirement?, by Greg Yeric, ARM
• Quantum Computing in Si, by Michelle Simmons, University of New South Wales
• Silicon for Prevention, Cure and Care: A Technology Toolbox of Wearables at the Dawn of a New Health System, by Chris Van Hoof, Imec

In keeping with IEDM’s tradition of intellectual overload, after lunch we have eight parallel sessions!

Session 2 starts a track on Nano Device Technology, in this case with papers on Ge and other Group IV Devices; six presentations, including an invited paper (2.4) by Y-C Yeo (et al.) of TSMC on “Germanium-based Transistors for Future High Performance and Low Power Logic Applications”.

Session 3 gets us into the Memory Technologies track, discussing PCRAM and Flash, with the first three papers on 3D-NAND, two on PCRAM, and one on integrated one-time programmable memory (OTP). The one most likely to draw a crowd is an invited talk (3.3) by Intel/Micron about their floating-gate 3D-NAND flash (sampling at the moment, judging by their last quarterly financial call).

Samsung started shipping their V-NAND last year, but that uses charge-trap storage, in which the electrons that make up the memory bits sit on a silicon nitride layer; the Intel/Micron device uses the conventional floating-gate method used in planar flash, where the electrons are stored on a polysilicon floating gate. It’ll be interesting to see the difference!

Plan-view TEM images of Samsung V-NAND flash array

Macronix is getting into the 3D-NAND game too (3.2), but their device uses a single-gate, flat-cell thin film transistor with an ultra-thin body that they have dubbed “single-gate vertical channel” (SGVC).

The gates are horizontal, defined by layer thickness, and the channels are vertical polySi stripes; this seems to be a charge-trap device, and the theory seems to be that “the design is not as sensitive to CD variation and is said to have potentially more than four times the memory density of GAA vertical channels at the same scaling node.”

Schematic of Macronix 3D-NAND flash cells (paper 3.2)

The other 3D-NAND paper is from imec (3.1), replacing the polySi channel with InGaAs.

The two PCRAM talks (3.5, 3.6) discuss different phase-change materials, GaSb-Ge and ALD Ge-Sb-Te; and the OTP paper (3.4) from UMC/National Chiao Tung University claims a “Newly found Dielectric Fuse Breakdown” that gives “a smallest memory cell array which can be easily integrated into state-of-the-art advanced CMOS technology”.

In session 4, we take a look at Circuit Device Interactions – this is a Focus Session on Beyond von Neumann Computing, with nine presentations discussing how neuromorphic, brain-inspired computing can be implemented in our electronic world.

Session 5 starts the Modeling and Simulation track, reviewing Physical Modeling for Advanced Devices, Power Devices, and Memories, which covers off a pretty broad swath of technology, from avalanche breakdown in diamond (5.2), through GaN-on-silicon (5.3), to RRAM (5.4) and 3D-NAND (5.5, 5.6).

Integrated Thin Film Transistors (TFTs) are discussed in session 6, as part of the Display and Imaging Systems track. I didn’t know that polysilicon nanowires counted as TFTs, but we have two papers (6.1, 6.3) on that topic, and 6.2 is a study of a finTFT. We get into more conventional areas with an invited talk (6.4) on “TFT Backplane Technologies For Advanced Array Applications”, then we have three presentations on oxide-based TFTs to finish up the session.

Reliability and Characterization of Resistive RAM and BEOL Processes is the topic in session 7. In 7.1 TSMC discusses the use of on-chip charge collectors formed from antenna-coupled floating gates, used to study the actual potential on transistor gates during plasma charging stress.

SK Hynix participates in a study (7.2) on copper diffusion in through-silicon vias (TSVs), which is timely now that their High-Bandwidth Memory (HBM) has just appeared on the market.

Optical cross-cection of SK Hynix HBM stack

Wafer Level Chip Scale Package (WLCSP) stress on high precision mixed-signal ICs is discussed by NXP in 7.3, again timely given the number of these we are seeing in mobile phones these days.

TSMC reviews TDDB lifetime models for back-end structures (7.4), and the last three papers look at RRAM reliability.

Session 8 is the first of the Process and Manufacturing Technology track, on 3D Integration and BEOL. We have a study of a self-forming Ta-Mn-O copper barrier layer from IBM/GLOBALFOUNDRIES (GF) in 8.1, which may give us a clue as to what we might see in their 10-nm back end; followed by Xilinx/Tohoku U (8.2) looking at wafer/wafer bonding of over 100,000 3-µm electrodes.

Disco Corp impressed me a few years ago by showing that they could thin wafers down to 7 µm thick – now they are claiming 2.6 µm in 8.3. They have looked at thinning effects on DRAM performance; 5.6 µm is OK, 2.6 µm is not.

TSMC also examine performance effects with thinned wafers and backside through-vias (8.4), and STMicroelectronics contributes to the next two papers, an invited talk (8.5) on 3D integration, and at the transistor end of the scale, a low-k spacer aimed at FDSOI technology (8.6).

The last two presentations are on monolithic 3D integration, where front-end layers are stacked rather than completed wafers, an intriguing concept, but with significant thermal challenges.

Session 9 reviews Advanced Compound RF and Power Devices; I could go through these in detail, but for the sake of brevity I’ll just say that five of the six papers discuss GaN devices, and the exception is about a vanadium oxide-on sapphire RF switch with a record switching cut-off frequency of 26.5THz (9.3).

Then in the evening we have the conference reception at 6.30, through until 8 pm. This year is the International Year of Light, plus the 50th Anniversary of Moore’s Law, so IEDM is celebrating with a special laser light show – should be fun!

Tuesday

In the morning we have another seven parallel sessions, starting at 9 am, with session 10 on RRAM in the Memory Technology track. The first paper (10.1, from Micron) is an invited discussion of “Non Volatile Memory Evolution and Revolution”. Judging by the authors, most of the papers are research, but in 10.5 Tsing-hua U/TSMC report an RRAM that uses a FinFET transistor for the “select” gate and an adjacent FinFET’s HfO₂-based dielectric film for a storage node of the RRAM cell, in a 16nm process; and 10.7 is a consideration of RRAM use for security applications from GF.

Schematics and TEM Cross-section of finFET RRAM (10.5)

Session 11 is the second Circuit Device Interaction session, this time on CMOS Scaling and Circuit/Device Variability. It kicks off with a paper by Renesas on 8T SRAM design in (presumably) TSMC’s 16-nm process (11.1), followed by a discussion from GF on self-aligned double patterned (SADP) BEOL use for a sub-10nm SRAM bitcell (11.2).

Samsung is up next (11.3), with a study on BTI variation in finFET SRAMs, then TSMC discusses magnetic thin-film inductors integrated into CMOS (11.4); Cadence gives an invited talk on the simulation of the variability of reliability of IC design (11.5); imec looks at the self-heating effects of bulk FinFETs from the 14nm to the 7nm node (11.6); and layout dependent aging in HKMG devices is detailed by Peking U. (11.7, with heavy SMIC involvement) in the last paper.

Session 12 is another on Modeling and Simulation, this time on 2D and Organic Semiconductor Devices. Black phosphorus devices are covered off in the first two papers, (12.1, 12.2), and 2-D tunnel FETs are examined in 12.3 – 12.5. Paper 12.6 is an invited talk on “Charge Transport Modelling in Organic Semiconductors” from the University of Rome, and the last paper (12.7) discusses the nature of metal-graphene contacts.

We move into the medical arena in session 13, a focus session on Silicon-based Nano-Devices for Detection of Biomolecules and Cell Function, with six invited papers on bio-analysis and measurement.

Flash and Novel Device Characterization and Reliability is the subject of session 14, starting with an imec paper (14.1) on Scanning Spreading Resistance Microscopy (SSRM) of a finFET, using diamond-based probe tips to scrape off material as the surface is repeatedly scanned to create a 3-D resistance profile.

Tunnel FETs are studied in the next two talks (14.2, 14.3), then we have two Si nanowire papers, again from imec (14.4, 14.5). U Tokyo details work on the reliability of Ge gate stacks in 14.6, and NAND flash reliability is the topic of 14.7 and 14.8.
Session 15 is the second in the Process and Manufacturing Technology track, this time on Moore and More; the first three presentations (15.1 – 15.4) discuss Ge and III-V devices, then we have an invited talk (15.5) on nanocarbon interconnects. Paper 15.6 reports on a photonic BiCMOS process, and in the last paper we hear about thin RF-SOI CMOS on flexible substrates (15.7).

Diamond-shaped Ge nanowire (paper 15.4)

30µm-thick RF-SOI CMOS circuits laminated on a flexible substrate (paper 15.7)

The speaker at the conference lunch will be Pat Tang, VP of Product Integrity, Amazon, presenting on “Working backwards from the Customer to Physics of Failure in Consumer Electronics Reliability”. This talk will examine a product integrity vision based on 3 technical strategies:

1. Working backwards from the customer to physics of failure
2. Design for reliability through simulation tools;
3. Development of customer-use centric standards using stress-strength analysis.

Pat joined Amazon in 2010 to lead Product Integrity and is responsible for the architectural integrity and product reliability of Amazon’s Kindle Fire tablets, e-readers, Fire TV and Fire Phone products. He was at Apple before that, where he was the reliability manager responsible for the qualification of Mac products such as the Macbook Pro, Macbook Air, iMac, MacPro, AppleTV and the first prototypes of iPad, so familiar with many of the products that have changed our lives in the last decade.

Session 16 is a focus session on Advances in Wide Bandgap Power Devices, part of the Power and Compound Semiconductor Devices track. As such we have eight invited talks, beginning with a review of “State-of-the-Art GaN Vertical Power Devices” (16.1) from Toyota.

Then imec looks at “200mm GaN-on-Si Epitaxy and e-mode Device Technology” (16.2), followed by Intel (16.3) discussing high-k GaN MOS-HEMTs. Paper 16.4 also reviews GaN power devices, and in 16.5 CEA-Leti steps back a bit to examine GaN epi on silicon and packaging topologies in the context of power electronics.

In 16.6 MIT details recent work on GaN-only normally-off transistors, HRL Labs talks about increasing the switching frequency of GaN HFET converters in 16.7; and the session finishes with STMicroelectronics giving a (presumably) more commercial survey of “SiC- and GaN-based Power Devices: Technologies, Products and Applications” (16.8).

Session 17 looks at Neuromorphic Computing Techniques in the circuit/device interaction track; definitely at the academic end of the scale for me, although seven of the eight papers use phase-change or resistive memory as synapses, so if this style of computing takes off that seems to bode well for emerging memory.

M/NEMS Resonators, Sensors and Actuators are considered in Session 18, covering sensor arrays (18.2), nanowires (18.3), transducers (18.4, 18.6), resonators (18.5), and energy harvesting (18.7).

The next parallel session is another focus session, this time on Flexible Hybrid Electronics (Session 19). Mostly research reviews, but paper 19.3 details an ultrathin Si-based flexible NAND flash memory, and 19.4 describes changing advanced CMOS electronics into a flexible and stretchable form.

Transistor Ageing, Variability and the Impact on Circuit Design is the subject of Session 20; NBTI is the topic of 20.1, off-state self-heating in scaled technologies (presumably including finFETS) is dealt with in 20.2, and more specifically self-heating in ETSOI is covered in 20.3. Paper 20.4 discusses hot-carrier aging, and “Technology Scaling and Reliability: Challenges and Opportunities” is an invited review in 20.5.

Samsung surprised me with the launch of their 14-nm finFET chip in this year’s Galaxy phone, and we get a peek at the “the extensive 14nm FinFET reliability characterization work” carried out by them in paper 20.6.

Random telegraph noise vs timing data investigated in a 32nm test chip in 20.7, and Rob Aitken of ARM gives an invited talk on “Implications of Variability on Resilient Design” in the last talk of the session (20.8).

Session 21 is the third in the Process and Manufacturing Technology track, on Advanced Modules and FinFET Devices. This looked like it might be the session where we get key papers on new production processes (such as the Samsung 14-nm), but I think we’re out of luck. Having said that, we do have some interesting papers on the program.

IBM starts off with a discussion (21.1) on “Understanding and Mitigating High-k Induced Device Width and Length Dependencies for FinFET Replacement Metal Gate Technology”. In the abstract it says that the gate fill metal is important to obtain a flat Vt-W response; given that finFET gate width is quantized, I’m curious to see what they have to report.

GLOBALFOUNDRIES gives an invited paper “Variation Improvement for Manufacturable FINFET Technology” (21.2), though it considers a 90-nm CPP process, not the Samsung-based 14-nm process now ramping up, which has a CPP of 78 nm. Gate stack, junction, and gate height variation were identified as key contributors to threshold voltage variation; I think we’ve seen that demonstrated before, but GF’s take will be of interest.

In paper 21.3 Tsing Hua U. reports on a bi-layer stacked gate dielectric, claiming improved drive current due to enhanced carrier mobility, resulting from less remote scattering caused by fewer charged oxygen vacancies.

Tokyo U. tries to clarify the SiO/HfO interaction in the common HKMG gate stack in 21.4, and in 21.5 they study “Preferential Oxidation of Si in SiGe for Shaping Ge-rich SiGe Gate Stacks”, which uses the different oxidation kinetics of Si vs Ge to optimize the gate stack.

Paper 21.6 is an imec study of Ge nFETs, looking at Si surface passivation and La band engineering; and in a joint work with Samsung (21.7) we hear about the contact resistance of Si:P source/drain epi with Ge pre-amorphization and Ti silicidation.

The last talk (21.8) is another imec joint paper, this time with ASM, detailing the use of phospho-silicate glass (PSG) to dope source/drain extensions. Last year we heard about Intel using PSG for solid-phase doping the base of the fin to reduce punch-through – now another example of this decades-old doping technique being re-used!

We go from finFETs to Steep Slope Transistors in session 22, with the first four papers discussing tunnel-FETs (TFETs), starting with an invited review by Intel (22.1). SMIC tells us in 22.2 that they’ve integrated TFETs into one of their foundry processes, and Forschungszentrum Jülich and MIT report on their TFET work in 22.3 and 22.4.

Papers 22.5, 22.6 detail studies on HfZrOx FETs, and the last presentation (22.7) describes a new type of SOI FET with a super-steep subthreshold slope of less than 6 mV/decade.

That brings us to the end of the afternoon, and Applied Materials is again hosting a panel on “The Changing Face of Non-Volatile Memory” at the Omni Shoreham Hotel on Calvert Street NW from 6.15 – 7.40 pm. They usually cater us well, so once we’re sated from the hospitality we can wander back to the Hilton for the conference evening panels:

“Is there a potential for a revolution in on-chip interconnect?”, and;

“Emerging Devices – Will they solve the bottlenecks of CMOS?”

This year we are back to two panels, but the first is portrayed as more of an election, so we have the following candidates:

• The incumbent: Rod Augur, GlobalFoundries
• We can design around it: John Wilson, nVidia
• Nano/novel materials or devices to the rescue: Azad Naeemi, Georgia Tech
• Active Interconnect: Toshi Sakamoto, NEC
• Monolithic 3D: Maude Vinot, CEA
• Multilithic 3D: Paul Enquist, Ziptronix

Moderated by Paul Franzon of North Carolina State University.

The parallel panel has Heike Riel, IBM Research as moderator, with Supriyo Bandyopadhya (Virginia Commonwealth University), Wilfried Haensch, also of IBM Research, Adrian Ionescu, EPFL, Carlo Reita, CEA-LETI, Sayeef Salahudin, UC Berkeley, and Frank Schwierz, Technical University of Illmenau as the distinguished panelists.

Wednesday

Wednesday morning has sessions 25 – 31; S25 is another Circuit Device Interaction session, with the intriguing title of “More than Moore – Value Added Technologies”. As a session, it’s bracketed by Toshiba, with two papers – the first, 25.1, reports on the use of magnetic tunnel junction (MTJ) memory for L2 and L3 cache memory in a CPU. They claim that with this technique, CPU power and chip area can be reduced 65 % and 37 % compared to conventional SRAM based CPU.

The second Toshiba talk (25.8) describes multi-gate oxide, dual work-function (MGO- DWF)-MOSFETs, with asymmetric LV-source/HV-drain junctions. This structure is reported to have an FMAX of 150 GHz, making it a contender for a low-power RF power amplifier.

We stay with RF in 25.2, but in a completely different context, as TSMC plugs their InFO fan-out packaging scheme in “High Performance Passive Devices for Millimeter Wave System Integration on Integrated Fan-Out (InFO) Wafer Level Packaging Technology”. There has been a lot of press gossip about the possible use of InFO for next year’s Apple A10 processor, so it’s a different spin to see InFO used down at the RF end of a phone.

25.3 is also an RF paper, this time discussing a reconfigurable 3/5 GHz, 0.13 μm CMOS low-noise amplifier, flip-chip integrated with a four-terminal phase-change RF switch. Intel is co-authoring this with Carnegie Mellon U. and John Hopkins U., so could this be using their EMIB co-packaging technology?

TSV-free monolithic 3D-IC stacking is the subject of 25.4, layering ultra-thin body devices and using CO2 far-infrared laser annealing (CO2-FIR-LA) technology for dopant activation. This is claimed to avoid device degradation, and a test chip with logic circuits, 6T SRAM, ReRAM, sense amplifiers, analog amplifiers, and gas sensors was fabricated to demonstrate the practicality of the scheme.

Next we have an invited review (25.5) of “New Devices for Internet of Things: A Circuit Level Perspective”; IoT had to show up somewhere!

If you know what Physically Unclonable Functions (PUFs) are, then paper 25.6 may be of interest – a “Robust and Compact Key Generator Using Physically Unclonable Function Based on Logic-Transistor-Compatible Poly-Crystalline-Si Channel FinFET Technology”.

IBM goes opto in the penultimate paper 25.7, looking at the integration of CMOS, RF and optoelectronic devices to enable low-cost O-band datacom transceivers.

In S26 we get back to memory. The first four papers, 26.1 – 26.4 detail a variety of STT-MRAMs, a 40-nm macro in 26.1, and a 28-nm macro in 26.2, while 26.3 reports a double magnetic tunnel junction device; and 26.4 studies the size dependence of the thermal stability of perpendicular STT-MRAM.

Samsung discloses some of the technology in their 20-nm DRAM in 26.5; we’ll see if it agrees with what we found in the part that we looked at! They refer to the use of “honeycomb structure and air-spacer technology” as being capable of taking us into the 1x-nm generations.

Air spacer between bitline and storage node contact in Samsung 20-nm DRAM (26.5)

Next up, SH Hynix has a talk on HKMG transistors in DRAM peripheral circuitry (26.6), something we have speculated about but not yet seen. The last paper, 26.7, reveals a one-transistor SRAM cell using a lateral MOS for access, and intrinsic vertical open-base bipolar structures for self-latch function.

Layered 2D Materials and Devices: From Growth to Applications is the topic of Session 27; from the look of the abstracts, we have seven invited talks which will give us a comprehensive review of the state of 2-D materials in electronic devices, predominantly graphene and molybdenum sulphide.

We go back into the world of Compact Modeling in session 28; the first two talks look at modeling zinc oxide and IGZO thin-film transistors (28.1, 28.2) used in displays. In 28.3 we get into finFETs with Asen Asenov’s, group, Gold Standard Simulations, examining the effects of the gate edge roughness and fin edge roughness.

Paper 28.4 looks at modeling graphene FETs for RF applications, 28.5 analyses STT-MRAMs, and the last paper (28.6) is an invited review, “Physics-based Compact Modeling of Charge Transport in Nanoscale Electronic Devices”.

Session 29 is an example of IEDM broadening its take on electron devices, since this session considers Devices for In Vitro Bioanalytics and In Vivo Monitoring. So for me there are new concepts such the field-effect control of ions in nanofluidic transistors (NFTs) in 29.1, ion-sensitive FETs (29.2, in this case fabricated in SOI-CMOS), and pH imaging sensors using CCDs (29.3).

We also have disposable ‘electronic microplates’ in 29.4 that use mechanically-flexible interconnects and TSVs to connect the electrodes on a CMOS biosensor to the electrodes on the electronic microplate, while keeping physical separation, and a CMOS-based “High Density Optrode-electrode Neural Probe” (29.5).

The last two papers report on “an ultra-thin (5um) implantable system using organic light emitting diodes and organic photodetectors in a reflectivity monitoring system suitable for hemodynamic measurement of the brain” (29.6), and a microbubble blood pressure sensor mounted on an acupuncture needle in 29.7.

A completely different world from chips in mobile phones, though I don’t doubt that app’s will be developed for some of them!

Advanced Imagers and Photodetectors are dealt with in session 30; Olympus is first up (30.1), with “Multi-storied Photodiode CMOS Image Sensor for Multiband Imaging with 3D Technology”, using two stacked imagers that function individually for optimized performance.

Olympus stacked image sensor with RGB light imager on top and IR sensor below (30.1)

Panasonic reports on an organic photoconductive film sensor in 30.2, then we have an invited paper from NHK Labs (30.3), also on an organic photoconductive image sensor.

A “BSI Image Sensor with Stacked Grid Structure” is discussed by TSMC in 30.4, and 30.5 is a photo-detector paper demonstrating a GeSn multiple-quantum-well-on-Si avalanche photodiode. A “Selenium/CMOS Hybrid Digital X-ray Imager” is described in 30.6; another stacked sensor, this time with a CMOS image sensor overlaid with a chlorine-doped crystalline selenium photo-conversion layer, is detailed in 30.7.

We return to power and compound semiconductor devices, in the form of III-V: FETs, Photonics, Si Integration in session 31. The first paper, 31.1, is on “Gate-All-Around InGaAs Nanowire FETS”, by imec et al., then we have “Vertical InAs Nanowire MOSFETs on Si” from Lund University (31.2), followed by an MIT talk (31.3) on “Quantum-size Effects in sub 10-nm fin width InGaAs FinFETs”.

Lund University returns in 31.4 with “Single Suspended InGaAs Nanowire MOSFETs”; followed by an invited paper by U. Tokyo discussing “CMOS Photonics Technologies Based on Heterogeneous Integration of SiGe/Ge and III-V on Si” (31.5).

MIT is back with a report on an InGaSb p-channel FinFET in 31.6, and the last paper of the session (31.7) is from imec again, on an InGaAs TFET with claimed superior SS reliability over a MOSFET.

After the morning sessions, the IEDM Entrepreneurs Lunch features Abbie Gregg, President of Abbie Gregg, Inc. (AGI), an engineering consultancy specializing in microelectronics process analysis and the design, startup and operations of clean laboratories and manufacturing facilities.

We are back to the Nano Device Technology track – Beyond CMOS Technologies in S32 after lunch, and U. Texas/Austin has the first paper in 32.1, looking at 2D nanomaterials, which would seem ideal for flexible electronics, in this case fabricating RF transistors.

32.2 describes a transition-metal dichalcogenide (TMD) body FinFET with back-gate control, postulated as a possible candidate for 2-nm technology, and 32.3 details a single-layer CVD molybdenum disulphide FET.

The next talk (32.4) is not a device report; it describes a method for separating semiconducting carbon nanotubes (CNTs) from metallic CNTs. The last two papers have spintronics as the topic, with an invited talk on “Spintronic Majority Gates” (32.5), and a demonstration of spintronic switch prototypes that encode information in a magnetic domain wall (32.6).

Session 33 has Emerging Nanodevices and Nanoarrays as the subject, beginning with two papers on vacuum nanoelectronics. MIT has fabricated (33.1) nanoscale cold cathodes (tiny electron guns) built from arrays of nanowire (NW) field emitters, with a current density of >100 A/cm². Each emitter (6-8nm tip diameter) sits atop a vertical silicon nanowire (10µm tall, 100-200nm in diameter). The nanowire acts as a current limiter to protect the emitter from possible damage from heating and arcing.

Top – schematic of field-emission array. Bottom left – SEM cross-sectional view of Si NW current limiter with gate oxide removed to show details; right, emitters are shown

33.2 is a simulation study of proximity effects on transmission efficiency and crosstalk in field emission vacuum microelectronic devices.

Next up is a MEMS plasma generator (33.3) designed for use in liquids, followed by an invited review (33.4) of “Nanoarrays for Disease Detection via Volatolomics” – it appears that volatolomics is the profile analysis of volatile organic compounds which are by-products of metabolic and pathological processes, and are emitted from various body fluids including breath, skin, urine, blood, and others.

Flexible graphene Hall sensors are described in 33.5, then “Suspended AlGaN/GaN Membrane Devices … for Ultra-low-Power Air Quality Monitoring” (33.6) finishes the session.

Modeling of III-V and Ge Materials and Alternative CMOS Device Architecture are dealt with in session 34. Intel gives the first presentation, discussing “CMOS Performance Benchmarking of Si, InAs, GaAs, and Ge Nanowire n- and pMOSFETs” (34.1), hopefully a summary of some of the wide-ranging R&D they have been doing in the last few years.

The next paper (34.2, U. Tokyo) discusses the intrinsic properties of Ge films in terms of phonon and electronic structures, providing critical parameters for device modeling. In 34.3, IBM looks at replacement metal gate resistance in FinFETs, coming to the conclusion that TiN gate fill is better than TiN/W for highly scaled gate lengths.

Process variation effect (PVE), work function fluctuation (WKF), and random dopant fluctuation (RDF) in 10-nm high-k/metal gate gate-all-around silicon nanowire MOSFET devices are studied in 34.4 (National Chiao Tung U.); with the result that the NW device has greater immunity to RDF, while suffering from PVE and WKF.

Intel is back in 34.5, in a “Study of TFET Non-ideality Effects for Determination of Geometry and Defect Density Requirements for Sub-60mV/dec Ge TFET”; and finally, ETH Zurich discusses InAs-GaSb/Si heterojunction TFETs in 34.6.

The last session (numerically), session 35, covers GaN Material and Device Interactions. MIT/Synopsys start the session off (35.1) with “Design Space and Origin of Off-State Leakage in GaN Vertical Power Diodes”, in which dislocations were identified as the main off-state leakage mechanism for GaN vertical diodes on different substrates; the authors claim that “designed GaN vertical diodes demonstrate 2-4 orders of magnitude lower leakage current while supporting 3-5 times higher electric field, compared to GaN lateral, Si and SiC devices.”

The next paper (35.2, ON Semi et al.) reports on the correlation between the off-state vertical leakage of 650V rated GaN-on-Si power devices and the dynamic Ron.

In 35.3, HKUST demonstrates a power FET with photonic-ohmic drain (PODFET) using a HEMT-compatible process on a conventional AlGaN/GaN-on-Si power electronics platform. It appears that photons are synchronously generated with the switching channel current, and they pump electrons from deep surface/bulk traps, improving the device dynamic performance.

Imec/ON Semi have been looking at how different parts of AlGaN/GaN buffers on Si contribute to the observed current collapse in devices, comparing three different types of buffers, namely stepped buffers, low temperature AlN interlayer buffers, and superlattice buffers (35.4).

Infineon et al. (35.5) report on AlGaN/GaN MIS-HEMTs with a fluorine-passivated dielectric/AlGaN interface, causing a modification of the “native” surface donors, leading to a fundamentally different device and defect behavior; potentially a new direction for reducing VTh drifts or defect engineered devices.

We finish the session with an invited review of “Steep Subthreshold Swing TFETs: GaN/InN/GaN and Transition Metal Dichalcogenide Channels” (35.6, U. Notre Dame et al.).

Chronologically the last papers are due at 3.40 pm – by then a lot of attendees will have headed for home, especially West-coasters who want to get home today.

I will definitely be suffering from information overload and becoming brain-numb, but with 230 papers and an average of six parallel sessions at any one time, plus the offsite events, that’s not really surprising. On the other hand, where else do we go to get all this amazing stuff?

Time to unwind, maybe do a little holiday shopping, and go for an indulgent meal.

By Dick James, Senior Technology Analyst, Chipworks

Back in April the Apple watch appeared in our labs, and of course we pulled it apart to see its contents. That set us some challenges, since inside the case we have the S1 “chip” (as Jony Ive called it in the launch last year). As you can see, it occupies most of the space inside the case, so it’s a pretty large chip; normally only the likes of IBM or Nvidia make chips this large.

Actually, we knew that there had to be multiple chips inside the S1, because we did a pseudo-teardown last year, based on Apple’s promo video at the time. It turns out that the S1 is actually an assembly of chips on a dedicated printed circuit board (PCB) substrate, with over 30 chips plus many passive components. So it is more accurately described as a System-in Package (SiP).

This was confirmed when we took the S1 out of the case and x-rayed it;

And we identified many of them;

This gave us the teardown information that we needed to find what chips were used, but the S1 is so different from any of the other wearables that we have looked at, that we had to go in and see how it was put together. So cut it in two and then onto the polishing wheel, and we get an idea of what Apple’s assembly house has done for them.

Actually, we did two cross-sections along the lines shown here;

This is section P1AS2;

On the left is the Dialog PMU; in the centre is the Apple APU (APL0778), with an Elpida DRAM co-packaged; and at the right is the Sandisk 64-Gb flash, including the controller chip and a spacer die. There seemed to be a wide-spread assumption that the APL0778 would be in a Package-on-Package (PoP) stack with the memory, as in the iPhones, but here it is in a straight-forward two-die stacked package.

If we look closer, we can see that the S1 uses conventional assembly techniques, but once all the components are on the 4-layer PCB, the whole thing has been over-molded with more molding compound, and then plated with metal to give the stainless-steel looking finish. A close-up of the right edge shows what I mean;

There are two 32-Gb flash dies in a conventional package with its own substrate, which is flip-bonded onto the PCB, covered with the SiP over-molding, and the exterior is metallized, giving the silver finish.

Section P1AS1 has the Broadcom BCM4334 in the centre, and the AMS NFC booster chip on the right. At left is a co-axial RF test socket.

Again, if we look closely, we can see that underfill has been used across the whole PCB before the over-molding was performed. Another feature of note is the I-shaped EMI shielding on the right of the BCM die, molded into the SiP – this is the first time we have seen this in any sort of package. In the x-ray image above, it surrounds the BCM chip, separating it from the other components. Here we are in close-up;

In effect the complete S1 assembly has EMI shielding since (with the exception of the accelerometer/gyro) the whole thing has a metal coat, mostly copper with a skin of iron/chromium. Such a coating will also inhibit moisture ingress, a good thing since I’ve heard tales of folks showering while wearing a Watch, and wrists can get a bit sweaty anyway.

A big question for us is – who supplied such an innovative package? Press commentary has identified the provider as ASE (Advanced Semiconductor Engineering Inc.) of Taiwan; and I presented at an IMAPS wearables workshop back in June, and when I got to the Watch analysis the attendees from ASE shared a few knowing looks.

The last quarterly analyst call from ASE also included this graphic, which details quite nicely the SiP concept, and includes details such as the EMI shielding:

ASE has also had more revenue from SiP this quarter, “In terms of overall, the SiP revenue accounted for about 22% in the second quarter, up from 15 a quarter ago because of the EMS SiP product ramp up.” Interestingly, they are also running below break-even on the SiP product (In response to a question as to whether all SiP projects are losing money, or just the one; “Thank God it is. It’s only this particular project that is running below break-even. Other things are moving very nicely.”).

Given these comments, I’m inclined to believe the press on this one – ASE is the supplier.

Another nugget comes from perusing the transcript of the call – “What kind of application and what kind of customers you are working with for the new SiP projects?

Tien Wu replied, “I don’t think I’d comment specifically but I’m pretty sure you will find some new products that have come out pretty soon. Sorry.”

He also noted, “We promise each other will never come out specific customers. So I will give you a non-qualifying, non-specific answer. We are expanding the SiP coverage to the cellphone, to the tablet in that particular arena. Hopefully, we can report more revenue, more penetration.”

I take that to mean that we may well see this style of SiP in the new iPhone and iPad later this year – more fun!

By Dick James, Senior Technology Analyst, Chipworks

The Confab started on Tuesday last week, an industry get-together organised by Solid State Technology (part of Extension Media), which they promote it as the “Semiconductor Manufacturing & Design Industry’s Premier Conference and Networking Event”.

The conference portion started with an afternoon panel session, “Exploring the Edges of Semiconductor Technology and Business”; I had the pleasure of kicking it off with a presentation on the state of the art in the business, as seen by Chipworks, then we got together on the podium for the panel part of the discussion.

Pete Singer moderated, and the other panelists were my co-blogger Phil Garrou, and Gopal Rao, ex-Intel and now an independent consultant. Pete had a set of pre-prepared questions on where we thought the business was going, the progress of 3DIC, and what we thought the impact of IoT (internet of things) might be.

Left to right: Phil Garrou, Dick James, Gopal Rao

We did our best to answer these and other questions from the floor, but Phil brought up a point that resonated with me; in the major segments of our industry we’re now down to three players, and that’s a sign that those segments have probably consolidated as much as they can. In the same way the auto industry has consisted of three significant players in each continental market (three in North America, three in Europe, etc). It’s a bit of an arm-wavy argument, but I think that it’s at least arguable.

So in DRAM we have Samsung, Micron, and SK-Hynix; in flash we have Samsung, Micron, SK-Hynix, and Toshiba/Sandisk: and in leading-edge logic we have Samsung+GLOBALFOUNDRIES, Intel, and TSMC.

Subramani Kengeri from GLOBALFOUNDRIES gave a good illustration of this a couple of years ago in an ASMC keynote speech:

And Tom Caulfield (also GLOBALFOUNDRIES) followed it up at this year’s ASMC, specifically in the DRAM space:

This is a point also made by Bill McClean of ICInsights in recent years, but he continues the logic to argue that now we are a mature industry, the business will tend to follow the world economic cycle rather than the capacity-based boom/bust cycles that we have seen in the first few decades.

Which makes sense from the mile-high perspective – we have all seen the changes in the customer base from the defence and computer industries, through the PC era, to a largely consumer-driven set of products – Apple is now the largest buyer of silicon chips in the world, after all.

Bill bracketed the Confab sessions neatly by giving the final presentation – “Are IC industry cycles dead or just sleeping?” His conclusion was that they are likely sleeping, but the trigger has changed from chip-making overcapacity or shortage, to whether world GDP goes positive or negative. To support that contention, he showed the correlation between worldwide GDP and IC market growth is now better than 0.9, compared with 0.35 back in the eighties.

This trend is likely a result of the consolidation of companies that we’ve seen and will continue to see, combined with the move to fabless and fab-lite, and its consequent tighter control over Capex; and, last but not least, the lack of disruptive new entrants to build mega-fabs and add over-capacity. China has had its play, India does not seem to want to get into that end of the business, and the Russian economy doesn’t seem to be up to it.

So, while we will see periods of growth and recession as always happens, likely amplified for our business since we are now so tied to consumer cycles, hopefully we won’t see the disruptive/destructive ups and downs that old-stagers like me have seen every three – five years in the last four and a half decades.

Having said that, there will be challenges, and it’s hard to see beyond 2020. We are now in the 14nm era in logic processes, and in five years (assuming a two-three year gap between generations) we will be ramping up seven-nm and heading for five.

In DRAM, Samsung has three 1x-nm nodes in their roadmap, possibly spread over five years, and flash is already at 14 – 16nm and moving to vertical – but how long will that last? Theoretically, I guess v-NAND could shrink from its current ~40nm node down to ~15nm, with more layers stacked together.

(That gives us the prospect of multi-Terabits on a single die, and I guess server farms would likely love such a product. On the consumer side, it does make me wonder if there is actually a market for (say) a 16-TB MicroSD card. On the whole, it starts to make my brain hurt.)

Those thoughts left me leaving the Confab actually wondering where these mainstream products are going to be in the early twenties, or if the technology is going to run out of steam. I know we’ve had these thoughts before, mostly due to mis-perceived lithography limits, but now we’re getting to the point where there may not be enough atoms or electrons to do what we want to do using current techniques.

Of course the research consortia are busy looking at ways of getting past this apparent impasse, it’s just that there seem to be quite a few options and no clear winner at the moment. And all the above doesn’t even consider the possible introduction of EUV and/or 450mm wafers.

Time will tell, and I may be retired by then, but we do live in interesting times, and it’s not going to change..

By Dick James, Senior Technology Analyst, Chipworks

The much anticipated Samsung Galaxy S6 made an early appearance in our teardown labs last week,  thanks to the diligent skills of our trusted logistics guru. We got our hands on the 4G+ version, the SM-G920I, with what Samsung claims is the world’s first octa-core 64 bit operating system. There is a wide array of industry buzz surrounding this flagship smartphone, but from my process-oriented point of view the focal point has to be on the Exynos 7420 application processor.

Samsung Galaxy S6 Teardown

Galaxy S6 Motherboard

Samsung Exynos 7420 Application Processor

The Samsung Exynos 7420 application processor is reportedly fabbed in Samsung’s 14 nm FinFET process. This is what Samsung has shown so far.

Which is not exactly specific! To start with, here’s the package marking of the package-on-package:

The layout of this is quite unusual – normally the memory marking (SEC 507 etc.) is in lines of text above the APU marking (7420 etc.), not in a diagonally opposed block. Which leads me into the speculation that maybe the 7420 is out of GLOBALFOUNDRIES, rather than a Samsung fab in Korea or Texas. Could ALB be short for Albany (NY)? Is the G in the lot code short for GLOBALFOUNDRIES? That all seems rather unlikely, but if Samsung wants to switch on the volume quickly in anticipation of huge volumes for the S6, what better way than to use three fabs? They did sound very confident in their last quarterly analyst call, saying that they expect 14-nm to be 30% of the LSI line capacity by year end. And there are lots of rumours about Qualcomm using the Samsung 14-nm process.

The die photograph and the die mark confirm the use of the Exynos 7420:

The functional die size is ~78 mm2, which compares well with the ~118.3 mm^2 of the Snapdragon chip used in the Galaxy S5, and the 113 mm^2 size of the 20-nm Exynos 5433. If the 7420 was a straight shrink of the 5433, we’d expect it to be 55 – 60 mm^2, but the back-end metallization stack is reported to be similar to the 20-nm planar process, so a full 50% shrink is unlikely (and the analog regions never shrink as well as digital anyway). We’ll have to wait until we see the floorplan to see how much functionality the two parts have in common.

Our guys in the lab made their usual exceptional effort in enabling us to see what the process looks like – within a few hours of getting the phone in-house, we have a decapsulated part and a cross-sectional sample under the microscope.

The Exynos 7420 uses 11 layers of metal, as you can see from the die seal cross-section above. Now let’s look at the transistors:

And we do have finFETs! This section is parallel to the fins, and across the gates. The bottoms of the contacts approximately indicate the top edge of the fin, and we are seeing the gates wrapped over and further down the sidewalls of the fin than the contacts appear to go. We will need another section orthogonal to this one to see if we have the type of epi growth in the source-drains that Intel uses.

This makes Samsung the second in line to get finFETs into volume production; they have successfully taken their 20-nm, first-generation, gate-last, high-k, metal-gate stack and adapted it to a first generation fin structure. We will need more detailed images to see whether the fins have vertical or sloped sidewalls, and how close to the Intel model they are, but those will come in the fullness of time when we have completed our full analysis and published our report.

Meanwhile, keep an eye on the blog!

By Dick James, Senior Analyst, Chipworks

In my conference preview blog last week, I mentioned that session 3 on the Monday afternoon would be a hot session, with three finFET papers, by TSMC, Intel, and IBM. I was right – even though they were given in the Grand Ballroom, it was full.

Paper 3.1 from TSMC disclosed what looks like their 16FF+ 16nm finFET technology, advanced from the 16FF reported last year – although they don’t actually call it that in the paper. A 15% speed boost and 30% power reduction is claimed, or 40% speed gain and 60% power saving compared to the 20nm process.

Gossip in the industry has it that 16FF was not advanced enough for TSMC’s customers, so they did some transistor engineering and cranked up the performance; 16FF is not even mentioned on the website these days, and 16FF+ is now in risk production, with endorsements by Avago, Freescale, LG Electronics, MediaTek, Nvidia, Renesas and Xilinx.

The 48nm fin pitch and 90nm contacted gate pitch announced last year were maintained, as is the 1x metal pitch of 64nm. This level uses “advanced patterning scheme” – presumably self-aligned double patterning (SADP), whereas the other 80/90 nm pitch metals are done with single patterning. The low-k dielectric stack has been optimized relative to the 16FF process to give almost 10% capacitance  improvement, and  they have also added a planar high-k MIM capacitor (>15 fF/um²) for on-chip noise reduction.

At the transistor level, we have a dual-gate oxide process, replacement metal gate (gate-last), dual epitaxial raised source/drains, and tungsten local interconnect – but NO PICTURES! Lots of plots, but no transistor images, as in last year’s 16FF paper, and we were out of luck in the live presentation as well.

So we still have no idea of what the TSMC finFETs will look like. I guess that’s good for me and Chipworks, since we’ll have to wait until they actually show up in the real world sometime next year.

Intel gave a late news paper (3.7) describing their 14nm finFET (note – finFET, not trigate) process at 4.05 pm. Being late news, there were only 15 minutes for Sanjay Natarajan to describe what looks like a technology that is distinctly changed from the 22nm process. AND there were images!

As announced back in August, fin pitch is reduced to 42nm, contacted gate pitch to 70nm, and 1x metal to 52nm, and we confirmed these in our blog on the Broadwell chip that we pulled out of a Panasonic laptop. In addition to the fins, the gates and the minimum metal levels use SADP, making for complex front-end lithography.

The fins have been modified from the 22nm process to have a more vertical profile, slimmed down to 8nm wide, and Intel also claims a “novel sub-fin doping technique” using “solid-source doping to enable better optimization of punch-through stopper dopants.” Sanjay’s presentation revealed that the solid-source doping uses a doped glass; now it’s down to us to work out when and where it’s used for punch-through inhibition. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over 22nm, and Idlin by 30% for NMOS and 38% for PMOS.

Changes have also been made to the back end – low-k dielectrics are used in the first eight levels, and significantly we see the first use of air-gaps in the M4 and M6 levels (80 and 160nm pitch).  This is Intel’s SEM image from the paper:

And here’s a TEM image from our analysis:

can see from the spacing of the gaps and the profile of the barrier layer over the copper that a patterned approach has been taken, as described in the IITC 2010 paper [1], using a mask step after the formation of the metal seal layer.

Intel likes to point out their history – this is the second generation finFET, fourth generation HKMG, and sixth generation strained silicon; will their 10nm be the third, fifth, and seventh generations?

I’m now inclined to think so, since at an Applied Materials event in the evening, when asked about the delay in the 14nm launch, Mark Bohr was heard to say “We won’t have similar problems at 10nm”. Mark does not make such comments lightly, so to me that implies two things – the 10nm process is pretty well locked down already, and it’s unlikely that there are huge structural changes from the 14nm generation. Indeed, the aggressive shrink from 22nm to 14nm puts them well on the way to the predicted 10-nm feature sizes.

Immediately after Intel’s talk IBM had their 15 minutes of IEDM advanced CMOS fame, describing their 14nm technology. This has their fourth generation embedded DRAM, but is the first-gen finFET, and the first-gen gate-last process (and I’ve lost count of the SOI generations).

IBM claims a “unique dual workfunction process applied to both NFETs and PFETs” and sub-20nm gate lengths, which will be the smallest we’ve seen if we ever get a sample. Being IBM, the intended product will be over 600 mm² and have 15 metal levels, presumably their Power9 server chip.

Fin pitch is the same as Intel at 42nm, but contacted gate pitch is 80nm, and 1x metal is 64nm. Here the fins are completely isolated since they are on the buried oxide, so no punch-through implants are needed at the base of the fin as on a bulk silicon substrate.

We do have pictures – these are really fuzzy, but we can see the gate wrapped over the fin with slightly raised source/drains on either side, and some nice facets on the source/drain epi.

During the presentation there were (of course) no details of the work-function materials, but it was stated that two masks were used to make the dual work-function structure; so presumably two slightly different material sets for the different work-functions. Another tidbit was that the pass-gate transistors

In the e-DRAM had a different Vt than the logic transistors, but not achieved by a workfunction change.

I’d missed it, but the IBM alliance gave a paper at the VLSI conference back in June [2], where they describe a 10nm finFET process; this look likes the same process, backed off to 14nm and with the e-DRAM added.

The e-DRAM introduces some challenges in connecting the trench capacitor plate to the fin of the pass gate. In the planar 22nm version there is a polySi strap from the polySi in the trench to the SOI on the buried oxide; in the finFET design the polySi strap is still used, but it is formed as a plug on the trench fill connecting to the SOI layer before fin definition, and the plug is etched into a fin during the fin etch. The epi module has been tuned to minimise the strap resistance and therefore the effect on access time.

Cell size of the eDRAM is now 0.0174 μm²; and if the trench capacitors are coupled together without the select gates, they can provide on-chip decoupling capacitors with a value of 450 fF/um².

In the back-end IBM has their fifteen layers of metal ranging from 1x – 40x, and the section shows that the 40x is seriously thick, to take the power needed to run a chip this size!

That made for an eventful afternoon, with a bit of a disappointment from TSMC; we’ll look forward to seeing both their finFET and the Power9 next year. Of course we have a suite of reports on the Intel Broadwell, for those who want a detailed analysis of the part!

References

[1]   H.J. Yoo et al., “Demonstration of a reliable high-performance and yielding Air gap interconnect process”, IITC 2010, pp. 1-3

[2]   K-I Seo et al., “A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI”, VLSI Tech 14, pp. 12-13

By Dick James, Chipworks

Later this month, the good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2014 IEEE International Electron Devices Meeting.  To quote the conference web front page, IEDM is “the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. The conference scope not only encompasses devices in silicon, compound and organic semiconductors, but also in emerging material systems. IEDM is truly an international conference, with strong representation from speakers from around the globe.”

That’s a pretty broad range of topics, but from my perspective at Chipworks, focused on the analysis of chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

In the last few days I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order.  As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.

Saturday/Sunday

Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorials on a range of leading-edge topics:

• Physical characterization of novel materials and devices for logic and memory, W.Vandervorst, imec
• Power Semiconductor Device Basics: History, Application, and Physics, Ichiro Omura, Kyushu Institute of Technology
• Optoelectronics of Graphene and other 2D materials, Phaedon Avouris, IBM Research, T.J. Watson Research Center
• Reliability characteristics of CMOS transistors post Si/SiO2/poly-Si gate stack scaling, Eduard Cartier, IBM Research, T.J. Watson Research Center
• Power Electronics for a Smart Energy Future, Johan Driesen, KU Leuven, ESAT-ELECTA
• Nonvolatile Memories: old and new, Jan Van Houdt, imec

The first three are from 2.45 – 4.15, and the remainder from 4.30 – 6.00.  This year I hope to make it to my old friend Wilfried Vandervorst’s session on characterisation, and possibly the other imec tutorial on memories at 4.30.

Wilfried gave an impressive talk at the imec symposium at Semicon West, and this time he has an hour and a half instead of 45 minutes, so hopefully a good bit more detail on what we can see, now that we are counting atoms in transistor analysis.

On Sunday December 14^th, we start with the short courses, “Challenges of 7nm CMOS Technologies” and “3D System Integration Technology”. Last year the short course was “Challenges of 10nm and 7nm CMOS Technologies”, so I guess we’ve moved on a bit; though I still need convincing that the 10-nm process architectures are locked down as yet.

Hidenobu Fukutome of Samsung has organised the former, and we have some impressive speakers – Greg Yeric, Senior Principal Design Engineer of ARM, (Circuit application requirements), Peide Ye, Purdue University (Device challenges), Guido Groeseneken, KU Leuven & imec, (Reliability challenges), Eric Karl, Intel, (On-die memory challenges), and Tsutomu Tezuka, Advanced LSI Technology Laboratory, Toshiba (Process and integration challenges). With 14-nm product on the market now, we need to look ahead, so this is appropriate – on the Intel clock, 7-nm is only four – five years away!

It now seems that 10-nm will be silicon-based, so we’ll see what the guys predict for 7-nm; new channel materials, nanowire transistors, and how will they integrate into a manufacturable process? What will be the effects on the performance of the basic logic blocks? What will device reliability be like with the potential new materials/structures? Hopefully we’ll find out here!

Eric Beyne of imec has set up the other short course; 3D is a very hot topic these days, both finFET and die stacking – here we are talking about die stacking.

Denis Dutoit of Cea-Leti looks at 3D System Design – Challenges for 3D Integration; I have the distinct impression that the manufacturing technology is in place, but design and test still have a way to go.

Next up is Kangwook Lee, Tohoku U, on Enabling Technologies: TSV Technology; again TSV technology is being promoted as here by both foundries and OSATs, and some products such as the Xilinx 2.5D FPGAs are out there, and stacked memories such as the Hybrid Memory Cube are sampling.

After lunch we have 3D evangelist extraordinaire Subu Iyer from IBM, talking about Enabling technologies: 3D integration for the Memory subsystem. IBM has been embedding DRAM into their products for several generations now, and as noted above, we are starting to see 3D-packaged memory come on to the market.

Wafer-to-wafer bonding is an essential part of 3D stacking, and that’s the topic of James Lu from Rensselaer Polytechnic. The last session is on 3D Reliability and Impact of 3D Integration on Devices, with Kristof Croes of imec discussing the device effects of the additional processing needed to make a 3D stack.

So some good solid stuff – although the courses make a long Sunday, from 9 a.m. to 5.30 p.m., but it’s worth sticking around to the end.

Sunday evening has some extra sessions; Sematech is holding a session on “Materials & Technologies for Beyond CMOS” at an as-yet unnamed location; and Leti will host a workshop on their “vision for silicon nano-technologies in the next 10 years” from 5.30 – 8.30 pm at the Nikko Hotel, across the street from the Hilton.

Monday

Monday morning we have the plenary session, with three pertinent talks on the challenges of contemporary electronics:

• SiC MOSFET Development for Industrial Markets, John Palmour, Cree Inc. – broadening the range of uses for silicon carbide?

• Are 3D atomic printers around the corner? Enrico Prati, CNR IMM (Italy’s Institute for Microelectronics and Microsystems) – now that 3D printers are becoming consumer goods, can we push the idea into the atomic scale? That sounds like the potential for everything from drugs design to the ultimate version of Moore’s law..
• Research into ADAS with Driving Intelligence for Future Innovation, Hideo Inoue, Toyota – Automated Driver Assistance Systems; moving towards the self-driving car?

After lunch we have seven parallel sessions coming up!

Session 2 is a focus session on power devices, with a kick-off paper by John Baliga of NCSU, on the Social Impact of Power Semiconductor Devices (2.1). John invented the IGBT in his time at GE back in the 80’s, and claims that the technology has reduced global carbon dioxide emissions by 75 trillion pounds over the last 30 years. He speculates that this can only increase with the introduction of new power devices. Papers 2.3 – 2.5 and 2.7 look like reviews of high-power switch technologies, and Si-, SiC and GaN-based power devices, respectively, while 2.2 and 2.6 look at specific SiC JFET and GaN HEMT devices.

Session 3 is the hot Advanced CMOS Technology group of papers with late news additions by Intel (3.7) and IBM (3.8), both on 14-nm finFET technologies, which even triggered their own press release.

The Intel finFET (note – not trigate!) device features “a novel subfin doping technique” to minimise fin doping and leakage under the fins, and air-gaps in two metallisation levels. This is the first use of air-gaps in a production logic part that I know of; we’ve seen them in memory chips for a while. Intel had a persuasive paper on this at the 2010 IITC conference [1], and I was wondering if we would see implementation at this node.

If you hunt hard in Intel’s August 14-nm announcement, you can find the air-gaps in the M5 level:

And we did find them in the M5 and M7 levels, but I will leave any detailed comment until a later blog. The IITC paper [1] speaks of using a mask step to define specific air-gap locations, and we can confirm that masking has indeed been used to define specific locations.

Now that we are analysing the Intel part, it would be remiss of me not to show an early shot of the fins, and they are clearly different from the 22-nm variety. There has been an obvious reduction in the width of the fin from its initial etched dimension, and it is tempting from this image to say that the NMOS fin is wider than the PMOS, but again more thorough discussion will have to wait.

IBM’s finFET is on SOI (of course, this is IBM!) and has a “unique dual workfunction process” which allows multi-V_t versions of both NMOS and PMOS, and claims sub-20 nm gate lengths. The process also includes fifteen metal layers and the latest version of their e-DRAM technology.

With all the Intel/IBM hype, I have become out of order here, because paper 3.1 from TSMC discloses what looks like their 16FF+ 16-nm finFET technology, advanced from the 16FF reported last year. A 15% speed boost and 30% power reduction is claimed, or 40% speed gain and 60% power saving compared to the 20-nm process.

Gossip in the industry has it that 16FF was not advanced enough for TSMC’s customers, so they did some transistor engineering and cranked up the performance; 16FF is not even mentioned on the website these days, and 16FF+ is now in risk production, with endorsements by Avago, Freescale, LG Electronics, MediaTek, Nvidia, Renesas and Xilinx, .

It will be interesting to see if any of the dimensions have changed from the 48 nm fin pitch and 90 nm contacted gate pitch announced last year. The metal stack is stated to be the same as the 20-nm planar process with a 1x pitch of 64 nm.

Paper 3.2 is from Avago, discussing Analog Circuit and Device Interaction in High-Speed SerDes Design in 16nm FinFet Process, and Renesas presents 3.3, on 16-nm 6T SRAM macros, both presumably TSMC’s process. 3.4 again looks at SRAM, but this time on STMicroelectronics’ 28-nm UTBB FDSOI process.

Next up is a couple of academic papers (3.5 & 3.6), discussing a 28-nm integrated RF power amplifier, and a 3D-stacked light harvester on a “epi-like Ge/Si monolithic 3D-IC with low-power logic/NVM circuits”.

3.7 and 3.8 are the Intel and IBM papers, and 3.9 is another late-news paper, from STMicroelectronics, but a change of pace from the finFETs – a 55-nm SiGe BiCMOS technology this time.

And by now it’s 5pm, the end of an intense afternoon!

In session 4, we take a look at Display and Imaging Systems. STMicroelectronics starts us off discussing MOS Capacitor Deep Trench Isolation for CMOS Image Sensors (4.1) in a joint talk with CNRS and CEA-LETI.

One of the goals in image sensors has to be integrating the A/D converters on each pixel, instead of at the edge of the pixel array, and 3D stacking comes to images sensors in paper 4.2 from NHK and U Tokyo; in which SOI wafers are direct bonded so as to provide each pixel with A/D conversion.

However, we won’t be seeing this in a phone anytime soon, as it is a proof-of-concept with 60-µm square pixels, as opposed to the 1-2 µm pixel pitch in most phone cameras.

NHK (jointly with Panasonic and U Hyogo) has another stacked sensor in 4.3, this time a selenium photodiode stacked on CMOS circuitry.

The remaining four papers are academic, covering far-infrared (4.4), a stacked SOI multi-band CCD (4.5), an embedded CCD in CMOS (4.6), and the display paper is 4.7, a solid-state incandescent device.

Session 5 covers Nano Device Technology – 2D Devices, a research session; 5.5 is a review of Nanophotonics with two-dimensional atomic crystals; the other papers all cover graphene devices (5.3, 5.4 and 5.6), black phosphorus (5.2), and molybdenum disulphide and tungsten diselenide (5.1, 5.7).

Resistive RAM is discussed in session 6. CEA-Leti has three papers in the afternoon,  (6.1, 6.3, 6.5) The first (joint with Altis Semi) looks at oxygen vacancies in doped oxide/Cu-based conductive bridge RAM (CBRAM), improving the Cu filament formation in the resistive layer; 6.3 is an invited paper that takes a higher level view of CBRAM and OxRAM devices in two different applications; and 6.5 is a detailed examination of CBRAM operation.

Micron and Sony get together to build a 27-nm 16Gb Cu-ReRAM part in 6.2, with a 1T 6F² cell – definitely some DRAM technology showing up here, in the buried wordlines:

TSMC and National Tsing Hua U have a 28-nm BEOL RRAM in 6.4; Stanford U looks at thickness limits in HfO-based RRAM in 6.6; Crossbar (6.7) discusses crossbar RRAM arrays; and imec/KU Leuven finishes the session with a paper on a TiN/Si/TiN selection device for RRAM switching elements (6.8).

Modeling Simulation of Extremely Scaled Group IV and III-V FETs is the topic in session 7, looking way ahead.

In paper 7.1, imec and Synopsys look at the stress effects of 3D stacking on 7-nm devices(!); 7.2 examines mobility enhancement in sub-14nm FDSOI, by the CEA-Leti/STMicroelectronics/IMEP/IBM/SOITEC FDSOI crew; and transient electrothermal effects in nanoscale FETS are considered in 7.3., from Osaka U and Kobe U, and JST-CREST.

Victor Moroz (Synopsys) does a comparative analysis of 7-nm finFETs in different materials in 7.4 – this might be a follow-up of his talk at Semicon West back in July, in which he concluded that silicon is still the best channel material, at least for low-power mobile devices.

Samsung and Udine U also look at different material nFinFETs (7.5, 7.6), and Peking U discusses III-V ultra-thin body pMOSFETs in the last paper of the session (7.7).

NEMS (Nanoelectromechanical Systems) and Energy Harvesters are dealt with in Session 8 – six academic papers, ranging from graphene and Mo disulphide atomic-scale layers that vibrate at RF frequencies (8.1), to photoelectric hydrolysis on MIS photocathodes (8.6).

For those interested in energy storage, Intel have fabricated porous silicon capacitors (8.2) that can potentially be integrated on-die or onto solar cells, taking advantage of the extreme conformal deposition capabilities of atomic-layer deposition (ALD). The image below shows a top-down view of the porous silicon before and after ALD TiN deposition; the wall of the pore walls get thicker, but the pore structure doesn’t change. Capacitances of up to 3 milliFarads/cm² are claimed.

Then in the evening we have the conference reception at 6.30, through until 8 pm.

Tuesday

In the morning we have another seven parallel sessions, starting with session 9 on Advanced CMOS Devices for 10nm Node and Beyond, so another one I will definitely be targeting.

The first paper (9.1, from IBM/STMicroelectronics/SOITEC/CEA-Leti) is about strained 10-nm FDSOI devices, incorporating “a fully compressively strained 30% SiGe-on-insulator (SGOI) channel PFET on a thin (20nm) BOX substrate”; they also report ‘strain reversal’ in a PFET – is that so much strain that it reduces mobility? In their workshops at last year’s IEDM and Semicon West, CEA-Leti have been showing a roadmap that jumps from 28-nm to 14-nm and then 10-nm nodes – this looks like the first showing of the 10-nm technology.

That is followed (9.2) by an invited talk from Simon Deleonibus of CEA-Leti on how process technologies can move us towards the zero-power era(?).

Purdue U claims the First Experimental Demonstration of Ge CMOS Circuits (9.3) on a GeOI substrate, while TSMC details InAlP-capped Ge nFETs on Si and Ge substrates (9.4), and Ge n-finFETs on Si (9.5). Still in germanium, National Taiwan U talks Ge nanowire nFETs on SOI (9.6).

The last paper of the session (9.7) is from AIST in Japan on tunnel finFETS in a CMOS process.

Session 10 is a focus session on Novel Imagers and Specialty Imaging Applications, starting with an invited talk by Jiaju Ma (10.1) from the Thayer School of Engineering at Dartmouth, on the Quanta image sensor; as near as I can make out, this type of sensor scans the pixel array so fast that it effectively reads individual photoelectrons, and the image is formed by integrating x, y, and time.

Paper 10.2 from TU Delft discusses single-photon avalanche diodes (SPADs), which have enabled solid state range finding, fluorescence lifetime imaging, and time-of-flight positron emission tomography. The topic of 10.3 (Ritsumeikan U, TU Delft, Osaka U) is high-speed image sensors, aiming for one giga-frame per second!

Another invited talk is by Siemens (10.4), about organic photodetector imaging, and next  imec details a CMOS-compatible approach to hyper- and multispectral imaging (10.5).

In a different spin, Annette Grot of Pacific Biosciences (10.6) will discuss how high-resolution, low-noise and high-speed image sensors have enabled large amounts of DNA to be sequenced quickly and at reduced cost; and how further advances will keep on pushing productivity and cost reduction.

For the final talk, we go from chip-scale to huge – the large scale hybrid pixel detector systems used at the Large Hadron Collider experiments at CERN (10.8).

Session 11 is the second group of talks about power and compound semi technologies, this time on High Voltage and RF Devices. Five of the six papers are on GaN devices, and one (11.2) describes a diamond MOSFET good up to 400C. We have a new acronym in there – a SLCFET (Super-Lattice Castellated Field Effect Transistor), with a 3D castellated gate structure (11.5) – that should make for a couple of interesting slides!

Circuit/Device Variability and Integrated Passives Performance is the focus of session 12; the middle papers, 12.3 and 12.4 are the passives talks, on Ultra-High-Q Air-Core Slab Inductors (IBM), and Above CMOS Integrated High Quality Inductors for wireless power transmission (HONG Kong UST). The other discussions range from finFET simulations (12.1 and 12.2) through MTJs for random number generation (12.5), noise suppression by using dynamic threshold voltage MOSFETs (12.6), and finally a consideration by ARM of poly pitch co-optimization in standard cells below 28-nm (12.7).

We look ahead to TFETs and other Steep-Swing Devices in session 13. The first paper (UCal Berkeley, Toshiba) discusses a nano-mechanical relay (13.1), which inherently has zero off-state leakage and perfectly abrupt ON/OFF switching behavior, but also serious manufacturing challenges. 13.2 and 13.3 are TFET talks, the 13.4 topic is a Schottky-barrier Si FinFET, and 13.5 and 13.6 review piezoelectric negative differential capacitance effects and devices.

Advanced Memories and TSV are the subjects of session 14; the first four papers are more resistive RAM, from imec (14.1 and 14.2), Politecnico di Milano/Micron (14.3) and Politecnico di Milano/Adesto (14.4). Adesto is the only company I know actually selling CBRAM parts, although we haven’t had a chance to look at them yet.

14.5 is a follow-up paper looking at noise in Samsung’s V-NAND flash [2], and 14.6 is also a follow-up from IBM on mobile ion penetration from BEOL layers close to TSVs. IBM’s TSV process uses MEOL connection to the TSVs [3], so it’s feasible that there could be some cross-contamination. Tohoku U contributes the last discussion (14.7), testing polyimide TSV liners as a way of reducing the stress in the adjacent silicon.

More sensors and MEMS papers in session 15; the first three are from Tsinghua U, about different applications of graphene MEMS (15.2 also from Berkeley), and TSMC/U Illinois contribute 15.4, on an integrated 180-nm SOI-CMOS biosensor.

A*STAR in Singapore author the final two papers, but on very different topics. 15.5 is an optical biosensor with Ge photodetectors built in to the back end, and 15.6 details a MEMS-tunable laser combined with a photonic IC.

The speaker at the conference lunch will be T.J. Rodgers, founder, President and CEO of Cypress Semiconductor, a well-known voice in the business for decades. Given the recent news of the merger between Cypress and Spansion, he could be an illuminating speaker!

Session 16 focuses on Ge and SiGe Transistors, starting with an IBM/GLOBALFOUNDRIES report (16.1) on strained SiGe-OI finFETs with 50% Ge and fin width of 3.3 nm and gate length of ~16 nm; clearly aimed at the 10-nm node.

Looking a bit further into the future, CEA-Leti/STMicroelectronics/SOITEC (16.2) examine omega-gate CMOS nanowires, with strained SiGe-channel p-FETs and Si-channel n-FETs, integrated into a SOI-CMOS process. From the look of the pictures below they are using a gate-first approach, so there is still some life in that technology.

16.3 is another nanowire paper from National Tsing Hua U, this time with dopant-free Ge junctionless nanowire non-volatile memories as well as Si nanowire FETs; and 16.4 is a study of Ge quantum-well finFETs fabricated on a 300mm bulk Si substrate, from Penn and N. Carolina SUs with TSMC and Kurt Lesker Co.

Imec tries out replacement metal gates on Ge n-finFETs with raised NiSiGe source/drains in 16.5; AIST examines poly-Ge-OI junctionless p- and n-finFETs, fabbed by flash annealing in 16.6; and Purdue U (16.7) reports on GeOI CMOS devices with recessed S/D.

Session 17 looks at Trapping Mechanisms in AlGaN/GaN Transistors; definitely at the academic end of the scale for me, although the last paper, CMOS-Compatible GaN-on-Si Field-Effect Transistors for High Voltage Power Applications, by TSMC, seems a bit out of place (17.6).

Session 18 is the second one on circuit/device interaction, this time considering Analog and Mixed Signal Circuits. Xilinx studies the interaction between devices and analog circuits used in high-speed transceivers in both planar and FinFet processes in 18.1. Part of this will be using the TSMC 16-nm finFET process, we’ll see if it adds anything to their paper in session 3.

Broadcom looks at mismatch in HKMG transistors related to the layout, and finds sensitivity to top metal routing, in 18.2. GLOBALFOUNDRIES (18.3) looks at Analog and I/O Scaling in 10nm SoC Technology and Beyond; is it better to take an increasing proportion of the die for hard-to-shrink analog, or go with TSVs and multiple dies?

CEA-Leti has a pathfinding paper (18.4) reviewing RF front-end modules (FEMs) in the light of the increasing number of modes (GSM, WCDMA, LTE, etc) and frequency bands in mobile devices. There are now more than 40 bands worldwide, so we see multiple FEMs in the worldphones we take apart, and keeping costs down while enhancing capability is one of the understated challenges in the industry.

There is more RF from Mediatek in 18.5, this time examining Digitally-Intensive RF Transceivers in Highly Scaled CMOS; apparently, these days embedded intelligence is needed on-chip to reduce the sensitivity of circuit performance to device characteristics.

The last paper in the session (18.6) is from Keio U, discussing circuit/device interaction in the 3D context of inductive coupling between dies.

Session 19 is the third memory session, this time on MRAM, DRAM and NAND; the first three talks are focused on STT-MRAM, from imec (19.1), Hanyang U/Samsung (19.2), and LEAP (19.3). Then IBM updates on their embedded DRAM (19.4), now at the 22-nm node in their latest Power8 processor (which, being IBM, is ~650 sq. mm!).

TSMC discusses a new Self-Aligned Nitride non-volatile memory cell in 19.5, and Macronix updates us on their BE-SONOS charge-trapping NAND flash (19.6) in the last paper of the session.

Characterization and Reliability of Advanced Devices is the subject of Session 20; papers 20.1, 20.3, and 20.5 all deal with nanowire characterization; imec has two studies, on HKMG InGaAs finFETs (20.2), and ESD diodes in Si finFETS (20.4); and finally two invited reliability presentations, by Jim Stathis of IBM (20.6) and Tony Oates of TSMC (20.7), on what the challenges are in their field as we move beyond 14/16 nm.

Session 21 is a group of five papers discussing Atomistic Modeling of Device Interfaces and Materials, the first being a multi-national study of hole traps in p-MOSFETs (21.1); I had not realized that such traps had similar characteristics in different oxide dielectrics, whether it be silicon or high-k; and it appears that hydroxyl (-OH) groups could be the cause.

The next three talks (21.2, 21.3, 21.4) are also dielectric and interface studies, as is the last, but 21.5 is focused on HfO and HfAlO-based RRAM.

We go back to MEMS in session 22, actually NEMS as well, as in 22.1, which is a review of integrating NEMS with CMOS (U Grenoble Alpes, CEA-Leti, MINATEC), and 22.4, another CEA-Leti talk on polySi nanowire sensors. Tsing-hua U has two papers also, 22.2 on a nanomechanical thermal-piezoresistive oscillator, and 22.3 on CMOS-MEMS Oscillators. The final two presentations are from A*STAR, about integrating RF MEMS resonators and phononic crystals (22.5), and a 9 degree of freedom capacitive sensor.

That brings us to the end of the afternoon, and Applied Materials is hosting a panel on “The Transistor Revolution” in the Nikko Ballroom in the Nikko Hotel. In parallel Coventor is hosting an event “Survivor, Variation in the 3D Era” in the Carmel Room, also at the Nikko Hotel. They both usually cater us well, so once we’re sated from the hospitality we can wander back to the Hilton for the conference evening panel:

“60 Years of IEDM and Counting: Did we push silicon based devices for integrated electronics to the ultimate and what does the future hold?”

Usually there are two panels, having one avoids conflicts this year; and there are some distinguished panelists – Krishna Saraswat from Stanford University, with two colleagues, Yoshio Nishi and Philip Wong, Chenming Hu (UCal Berkeley), Hiroshi Iwai Tokyo Institute of Technology), Jesus del Alamo (MIT), and Kurt Petersen, co-founder of six MEMS companies, and a member of the Band of Angels.

Wednesday

Wednesday morning has sessions 25 – 31; S25 on III-V for Logic; MIT has two papers, on InGaAs Quantum-Well MOSFETs (25.1), and InGaAs/InAs heterojunction single nanowire vertical tunnel FETs (25.5).

25.2 is an invited review of “High-Performance III-V Devices for Future Logic Applications”, by Dae-Hyun Kim of GLOBALFOUNDRIES; 25.3, by IBM, is more high-performance self-aligned InGaAs-channel MOSFETs; 25.4 (UCal, Santa Barbera) is also InGaAs, but with InP Recessed Source/Drain Spacers; and 25.6 discusses an InAlN/AlN/GaN triple T-shape fin-HEMT (Nanyang TU, Ohio State U, Institute of Materials Research and Engineering).

S26 covers Thin Film Transistors for Display and Large Area Electronic Applications. Imec demonstrates an ultra-low power organic 8 bit transponder chip in 26.1, followed by IBM with heterojunction field-effect thin-film transistors (TFTs) with crystalline Si channels, and gate regions comprised of hydrogenated amorphous silicon or organic materials (26.2).

CBRITE is next up (26.3), on High Performance Metal Oxide TFTs, then a change of pace to carbon nanotubes with sputtered and spray-coated.

Metal oxides to form complementary inverters, from the Swiss Federal Institute of Technology, Imperial College London, and U Würzburg (26.4).

Believe it or not, Delft U has worked out a way to put silicon TFTs on paper or other soft substrates:

“The Delft team made the devices by casting a quantity of liquid polysilane onto a substrate, and forming a thin film from it by “doctor-blading,” or skimming it with a blade. High-performance polysilicon channel regions then were formed by laser annealing, using short pulses of coherent light to selectively crystallize the disordered film. The maximum temperature required was only 150ºC, making the TFTs suitable for paper and plastic substrates such as PET and PEN.” (26.5)

Tsing Hua U finishes up the session with the last two papers – a study of “Ultra-Thin Body (2.4nm) Poly-Si Junctionless Thin Film Transistors with a Trench Structure”, claimed to be useful for displays and 3DICs; and more poly-Si channel junctionless  FETs, but this time with a poly fin (26.6, 26.7).

Hybrid and 3D Integration is the topic of Session 27; TSMC starts off with a review paper about wafer-level system integration technologies (27.1), followed by Nikon, demonstrating their precision-aligning Cu-Cu bonding system for 3DICs (27.2); then TSMC adds high-k metal-insulator-metal capacitors to their CoWoS interposers (27.3).

Stanford U pushes the boundaries in paper 27.4 by integrating traditional silicon-FETs with RRAM and carbon nanotube-FETs, to form four vertically-stacked circuit layers (logic layer followed by two memory layers followed by a logic layer).

CEA-Leti has been working on monolithic 3D integration for a while, and here they consider the thermal budget of the bottom layers (27.5). The last paper has KAIST transferring SOI silicon nanowire SONOS memory onto a plastic substrate, after thinning down to the buried oxide (27.6).

We have more emerging memory papers in session 28, together with a couple on heterogeneous integration. Toshiba starts the session discussing high density STT-MRAM for cache memory (28.1), using MTJs embedded in the back-end stack. Tohoku U and NEC look at hybrid MTJ/CMOS logic in 28.2 to make ultra-low-power logic LSI, and Rambus investigates surge current control in RRAM arrays in 28.3.

Paper 28.4 is a CEA-Leti (et al.) study of pattern recognition using convolutional neural networks made from HfO₂ based OxRAM devices as binary synapses. National Chiao Tung U is also researching synaptic use of RRAM for neuromorphic computation in 28.5.

Tohoku U returns with a 3-D stacked multicore processor module made from a 4-layer 3-D stacked multicore processor chip and a 2-layer 3-D stacked cache memory chip (28.6), and using backside TSVs to enable multichip-on-wafer 3D integration. Below is an X-ray tomograph of the TSV stacks, the processor on the left and the memory on the right:

In 28.7, Penn State U et al. demonstrate coupled hybrid vanadium dioxide FET oscillators in a platform for associative computing, claiming ~20x power reduction compared with CMOS; and the last paper from UCal Berkeley (28.8) integrates NEMS into a CMOS back-end stack for ultra-low power applications.

Session 29 continues the memory theme, discussing PCM and Neural Networks, and kicked off (29.1) by Micron Italy (et al.) looking into different GeSbTe PCM cell architectures.

29.2 is from the Japanese LEAP consortium, describing a new type of PCM, “topological-switching random-access memory,” (TRAM). It differs from conventional PCM in that the latter works by the rapid heating of a chalcogenide material, which shifts it between its crystalline and amorphous states; whereas TRAM stores data by movement of germanium atoms within a GeTe/SbTe crystal superlattice:

The authors claim up to 20x reduction in programming energy, achieving a set/reset current as low as 55 µA.

We have an invited paper in 29.3, “Phase Change Memory and its Intended Applications”, by Chung Lam of IBM, followed by a statistical study of PCM to optimize memory capacity (29.4, UCal Berkeley et al.). We get back to PCM-based neural networks in 29.5, again from IBM, and Politecnico di Milano/Micron look at PCM set-transition energies (square vs triangular pulse) in 29.6.

IBM again takes the podium in 29.7, examining access devices for crossbar resistive memories, and they are a co-author with Macronix and National Tsing Hua U in the last paper, detailing a PCM recovery method – apparently a local anneal can be done on-chip to recover the phase-change properties if they degrade due to too many cycles (29.8).

Simulation of Novel Materials and Devices for FETs are considered in session 30; Toyota Tech Institute, Osaka U, and U Tsukuba (30.1) show that random dopant fluctuation in the source region causes a noticeable variability in the on-current of Si nanowire transistors, and its impact is found to be much larger than that of random telegraph noise (RTN).

30.2 is a review of Tunnel-FETs for future low-power technology nodes, by imec; 30.3 (U Florida) simulates Mo-disulphide-WTelluride vertical tunneling transistors; 30.4 (ETH Zurich) is another Mo-disulphide transistor study, as is 30.5, but also evaluates W-diselenide (UCal Santa Barbara); and the session finishes with a simulation of a (B-N) co-doped graphene TFET by Hong Kong UST/NanoAcademic Technologies (30.6).

The last focus session is session 31, Sensors, MEMS, and BioMEMS. It opens with a display of bio-MEMS for handling single molecules, including silicon nano tweezers, arrays of micro chambers, and chips with linear bio molecular motors (31.1, U Tokyo). The specific application is the use of MEMS technology on the molecular scale to conduct studies of DNA degradation and protein mutation related to Alzheimer’s disease. MEMS tweezers were used to trap bundles of DNA molecules to study them for stiffness and viscosity, which are markers of DNA degradation.  Here we have an electron microscope image of a DNA molecular bundle between the tips:

Next up, U Bologna/U Southampton research the use of AC nanowire sensing that can capture both magnitude and phase information of the device response (31.2); 31.3 is a review of “MEMS for Cell Mechanobiology” (Stanford U); and 31.4 is also a review, of “Organic Electrochemical Transistors for BioMEMS Applications”, from Ecole Nationale Supérieure des Mines.

U Cincinnati (et al.) follows, with a tempting look at a “novel multimodality lab-on-a-tube smart catheter”, which can accurately track multiple parameters in an injured brain (31.5); 31.6 (Ritsumeikan U) shows off another medical device, an all polymer pneumatic balloon actuator, fabricated from polymers such as polyimide and polydimethylsiloxane that we are familiar with in the chip business. Paper 31.7 from MC10 completes the session by demonstrating examples of skin-based systems that incorporate physiological sensors and actuators configured in stretchable formats.

After the morning sessions, the IEDM Entrepreneurs Lunch is back for a third year, featuring a presentation by Kathryn Kranen, Former President and CEO of Jasper Design Automation.

Also at lunchtime ASM is hosting their regular IEDM seminar (Wednesday this year, instead of the Monday as of last year) on “14nm & Beyond – Fins all Around”, at the Nikko Hotel across the street from the Hilton. There’s no website, so interested parties should contact Rosanne de Vries, by replying to [email protected]. And there’s a bit of self-promotion here, since I’m one of the guest speakers!

We are back to Process and Manufacturing Technology in S32 after lunch, with a focus on Advanced Process Modules. IBM details some of its work on finFETs formed by Directed Self Assembly (DSA) in 32.1, achieving 29 nm fin pitch, and maybe giving us more evidence that EUV may never happen..

In 32.2 Samsung discusses their 10-nm interconnect strategy; judging by the abstract, we might be moving to Cu+Ru liner by the time we get to 10 nm. An imec/Micron/Hynix joint paper (32.3) reveals a new front-end scheme (gate and diffusion replacement), which allows high-thermal budget processes for applications such as control logic for memory (e.g. DRAM periphery).

Paper 32.4 is from Albany CNSE and its sponsors, examining the contact resistivity on n+ InGaAs fin sidewall surfaces; U Tokyo discusses oxygen effects in Ge MOSFETs in 32.5; 32.6 is a review of ion implantation techniques and capabilities by Applied Materials, from doping to materials engineering; and 32.7 covers “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing”. The lead authors are from National Nano Device Laboratories, National Chiao Tung U, and National Cheng Kung U, but Michael Current and Evans Analytical are also involved, so at the least there should be some interesting analytical data included.

Session 33 has Exploratory Devices as the subject, inevitably academic in nature – Carnegie Mellon starts off (33.1) showing a four-terminal spintronic device, followed by Tohoku U, investigating 1x-nm perpendicular-anisotropy CoFeB-MgO based MTJs (33.2). Then we have a two-sided graphene oxide doped silicon oxide based RRAM (33.3) from National Sun Yat-Sen U, Peking U, and Stanford U; and a new material raises its head in (33.4) – iodostannane, basically tin activated with iodine, in a new kind of transistor, the topological-insulator field-effect transistor.

National Nano Device Laboratories, et al., present CMOS-compatible Mo-disulphide 3DFETs in 33.5, and Stanford U end the session with a review of carbon nanotube transistors.

Reliability: BTI, HCI and Breakdown are dealt with in session 34. A SMIC-sponsored work on NBTI in HKMG is covered in 34.1, co-authored by Peking U, Liverpool John Moores U, and UCal Berkeley. Liverpool John Moores U and imec look at NBTI of Ge pMOSFETs (34.2), and AIST has researched PBTI in n-fin-TFETs in 34.3; imec is back in 34.4, reviewing BTI reliability in “beyond-silicon devices”; and 34.5 covers RTN in both SiON and HKMG devices, by Peking U and SMIC.

Samsung (34.6) studies hot carrier induced dynamic variation in nano-scaled SiON/Poly, HK/MG and finFET devices, and the final paper of the session is from IBM and SRDC, discussing breakdown mechanisms in dielectric BEOL stacks (34.7).

The last session (numerically), session 35, covers Compact Modeling of devices. MIT and Purdue U get together to present a new model for FETs, which uses only a few physical parameters and is consistent with the virtual source model (35.1). They demonstrate its accuracy by comparison with measured data for III-V HEMTs and ETSOI Si MOSFETs.

NXP/UFRGS have a new noise (RTN/LFN) model for MOSFETS in 35.2, followed by IBM discussing several width dependent transistor current characteristics (35.3). We jump to TSVs in 35.4, with a CEA-Leti (et al.) study of thermal dissipation in 3D ICs and an associated model; IMECAS presents a surface potential-based compact model for a-IGZO TFTs in RFID applications in 35.5; and Purdue U/GLOBALFOUNDRIES model MTJs in 35.6.

Chronologically the last papers are due at 4.05 pm – by then a lot of attendees will have headed for home, especially since this year’s conference is so close to the Christmas break.

I will definitely be suffering from information overload and becoming brain-numb, but with 218 papers and an average of six parallel sessions at any one time, plus the offsite events, that’s not really surprising. On the other hand, where else do we go to get all this amazing stuff?

Time to unwind, maybe do a little holiday shopping, and go for an indulgent meal.

References:

[1]     H.J. Yoo et al., “Demonstration of a reliable high-performance and yielding Air gap interconnect process”, IITC 2010, pp. 1-3

[2]     J. Jang, et al., “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High density NAND Flash Memory” VLSI 2009, pp.192-193

[3]     M. G. Farooq et al., “3D Copper TSV Integration, Testing and Reliability”, IEDM 2011, pp.143-146

By Dick James, Chipworks

Earlier last week, a couple of laptops arrived from Japan using the Core M version of Intel’s Broadwell processor. Straight into the lab, and within a few hours the first sight of the die structure, confirming that it is indeed the 14nm technology.

The first image below is an image of a die that was given a bevel polish, so that we can look at the transistors in plan view. It’s a bit fuzzy, due to the high magnification, and construction we have going on next door; but we have measured ten contacted gate pitches as you can see, and that looks pretty close to the 70nm that was announced by Intel back in August.

On another part of the bevel we can see the fins, and here we have counted 20 pitches (third image above). Which agrees with the 42nm pitch in the Intel webcast. So far, so good!

If we look at the cross-section (fourth image), Intel has stayed with their thick top metal that they have been using since the 65-nm node, which means that we have to squint awfully hard to see THIRTEEN layers of metal, and a MIM-cap layer under the top metal.

A look at the edge seal (fifth image), which doesn’t have the top metal or the MIM-cap, makes it easier to count twelve layers. We are used to seeing twelve-plus metal layers in IBM chips (their 22nm Power8 has fifteen!), but Intel has been using nine for the last few generations, going up to eleven in the Baytrail SoC chip.

Intel quoted 52 nm interconnect pitch, but we see 54nm (sixth image). Although that is within measurement error, and we may not have sectioned the most tightly packed part of the die.

As yet we don’t have any detailed TEM imaging to look at the transistors or fins in close-up, so we can’t verify if the fins have vertical walls or not, as shown by Intel (seventh image).

The cross-section seems to show that essentially the 14nm process is a shrink of the 22nm technology, with the modified fins; the gate metallisation looks similar to the 22nm, with tungsten gate fill as in the earlier process. (As an aside, this will make it the fourth generation replacement metal gate process – this technology has legs!)

Intel and IBM are giving late news papers at IEDM in December, and apparently there are air gaps in the back-end dielectric stack – we have not found those yet. We have confirmed the SRAM cell size in the cache memory is ~0.058 µm2.

Our analysis is ongoing, and we look forward to some great images!

By Dick James, Senior Technology Analyst, Chipworks

Two weeks ago, we posted about the TSMC 20nm product that we had in-house; now after waiting for a year since Samsung’s announcement of V-NAND production, we have that in the lab and can start to see what it looks like.

The vertical flash was first released in an enterprise solid-state drive (SSD) last year, in 960 GB and 480 GB versions, but with no model number, so essentially for sampling only to established customers. Then in May this year they announced a second-generation V-NAND SSD, with a stack of 32 cell layers.

However, on July 1 at this year’s Samsung SSD Global Summit they unveiled the SSD 850 Pro, aimed at high-end PCs and workstations, and said to be available in July. Of course we immediately put out feelers and got some on pre-order.  They showed up last week and we have the first few images.

First, though, let’s think about what the changes are from the conventional planar NAND. Samsung posted a slick video which gives a summary of the technology. The first thing to note is that we have gone from the ETOX floating-gate charge storage that we have seen in the last umpteen generations of flash, to charge-trap storage (CTF – Charge Trap Flash) in which the charge is stored on a silicon nitride layer (otherwise known as a SONOS cell – Si/SiO/SiN/SiO/Si).

The SONOS stack is then oriented vertically, using a polysilicon cylinder as the substrate silicon, and wrapping the other layers around the central cylinder.

Fig. 1 Cell structure transition from planar to V-NAND stack

The wordlines (control gates) become a horizontal layer, and the bitlines are connected to the top of the polySi cylinder; the select gates are formed by the top and bottom conductive layers [1]. Samsung describes the use of a tungsten replacement metal gate [1], and 24 wordline layers plus 2 dummy wordlines and two select gates for a total of 28 layers [2].

Fig. 2 Schematic of V-NAND cell stack

We also see in Fig.2 a “blocking layer” in between the metal gate and the SiN, which at least implies the use of a high-k dielectric instead of an oxide layer for the capacitative coupling layer, as used in their CTF parts from 2006.

One of the many challenges using a vertical stack such as the V-NAND is etching through a stack of many dissimilar layers, to etch the holes for the polySi cylinder channels,  the slots through the stack to separate the wordlines, and the vias down to the wordlines (etching holes down to a staircase of extended wordlines). In fact, the whole stack is a big etching problem – see Fig.3.

Fig. 3 Schematic of etching steps in V-NAND stack

Now that we have the production part, Samsung have clearly solved those problems. Let’s take a first look at what’s inside. Fig. 4 is a photo of the die, and Fig. 5 shows the die mark – the “A” on the end denoting the second-generation product. Interestingly, the “DG” in the part number normally denotes a 128-Gb die, but this part is actually ~86 Gb, since we have twelve flash dies in our 128-GB solid-state drive.

Fig.4 Die photo of Samsung K9ADGD8S0A V-NAND flash device

The part described in the ISSCC paper [2] was an actual 128-Gb device, with a chip size of ~133 sq. mm. Our 86-Gb die has shrunk to ~85 sq.mm., slightly increasing the bit density from 0.96 to 0.99 Gb/sq.mm.

Fig. 5 Die mark

When we cross-section the chip, the staircase shown in Fig. 3 shows up nicely:

Fig. 6 SEM cross-section of Samsung V-NAND stack

In this first shot, we don’t appear to have sectioned through any of the vias to the wordline layers; the vertical features appear to be polySi cylinders drilled into the outer edges of the stack. If we look closer at the edge of the array, that does appear to be the case (Fig. 7).

Fig. 7 Edge of V-NAND flash array

On the left side of the image we can see the array proper. SEM images can always be confusing, but it appears that the polySi bitline cylinders are staggered, and the slots between wordlines are filled with tungsten to contact the substrate for the lower select transistors. Fig. 8 shows things in a little more detail, and we can clearly see that the bitline contacts are staggered. We can also see that there are 38 layers in the stack; 32 wordlines, plus four dummy wordlines, plus the select transistors at top and bottom.

Fig. 8 Close-up image of V-NAND flash array

At the moment, that’s as far as we’ve got; we don’t yet have any materials analysis, but my guess is that the three interconnect layers are tungsten, copper and aluminum, as in a lot of other Samsung memory chips.

We will of course being preparing a report on this seminal part, so for more details contact Chipworks, or keep an eye on my Twitter account, @ChipworksDick.  Once the dust has settled, I hope to get into a bit more detail in a future blog in a few months time.

[1] J. Jang et al., “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory“, Dig. Symp. VLSI Tech., pp. 192-193, June 2009

[2] K-T Park et al., “Three-Dimensional 128Gb MLC Vertical NAND Flash-Memory with 24-WL Stacked Layers and 50MB/sHigh-Speed Programming“, Proc. ISSCC, pp. 334-335, Feb. 2014