Tag Archives: R&D

SAQP Specs for 7nm finFETs

As discussed in my last Ed’s Threads, lithography has become patterning as evidenced by first use of Self-Aligned Quadruple Patterning (SAQP) in High Volume Manufacturing (HVM) of memory chips. Meanwhile, industry R&D hub imec has been investigating use of SAQP for “7nm” and “5nm” node finFET HVM, as reported as SPIE-AL this year in Paper 9782-12.
The specifications for pitches ranging from 18 to 24 nanometers are as follow:

7.0nm Critical Dimension (CD) after etch,
0.5nm (3sigma) CD uniformity (CDU), and
<1nm Line-Width and Line-End Roughness (LWR and LER) assuming 10% of CD.

“Pitch walk”—variation in final pitch after multi-patterning—results in different line widths, and can result in subsequent excessive etch variation due to non-uniform loading effects. To keep the pitch walk in SAQP at acceptable levels for the 7nm node, the core-1 CDU has to be 0.5nm 3sigma and 0.8nm range after both litho and etch. In other presentations at SPIE-AL this year, the best LER after litho was ~4nm, improving to ~2nm after PEALD smoothing of sidewalls, but still double the desired spec.

The team at imec developed a SAQP flow using amorphous-Carbon (aC) and amorphous-Silicon (aSi) as the cores, and low-temperature Plasma-Enhanced Atomic-Layer Deposition (PEALD) of SiO2 for both sets of spacers. Bilayer DARC (SiOC) and BARC were used for reflectivity control. Compared to SAQP schemes where the mandrels are only aSi, imec claims that this approach saves 20% in cost due to the use of aC core and the elimination of etch-stopping-layers.

—E.K.

Litho becomes Patterning

3 Replies

Once upon a time, lithographic (litho) processes were all that IC fabs needed to transfer the design-intent into silicon chips. Over the last 10-15 years, however, IC device structural features have continued to shrink below half the wavelength of the laser light used in litho tools, such that additional process steps are needed to form the desired features. Self-Aligned Double Patterning (SADP) schemes use precise coatings deposited as “spacers” on the sidewalls of mandrels made from developed photoresist or a sacrificial material at a given pitch, such that after selective mandrel etching the spacers pitch-split. SADP has been used in HVM IC fabs for many years now. Self-Aligned Quadruple Pattering (SAQP) has reportedly been deployed in a memory IC fab, too.

An excellent overview of the patterning complexities of SAQP was provided by Sophie Thibaut of TEL in a presentation at SPIE-AL on “SAQP integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications.” Use of a spacer-on-spacer process flow—enabled by clever combinations of SiO2 and TiO2 spacers deposited by Atomic Layer Deposition (ALD)—requires the following unit-process steps:
1 193i litho,
2 ALD spacers,
2 wet etches, and
4 plasma etches.

Since non-litho processes dominate the transfer of design-intent to silicon, from first principles we should consider such integrated flows as “patterning.” Etch selectivity to remove one material while leaving another, and deposition dependent on underlying materials determine much of the pattern fidelity. Such process flows are new to IC fabs, but have been used for decades in the manufacturing of Micro-Electrical Mechanical Systems (MEMS), though generally on a patterning length scale of microns instead of the nanometers needed for advanced ICs. R&D labs today are even experimenting with Self-Aligned Octuple Patterning (SAOP), and based on the legacy of MEMS processing it certainly could be done.

—E.K.

CMOS-Photonic Integration Thermally Sensitive

Leave a reply

As published in the journal Nature, CMOS transistors have been integrated with optical-resonator circuits using complex on-chip sensors and heaters to maintain temperature to within 1°C. While lacking the laser-source, these otherwise-fully-integrated solutions demonstrate both the capability as well as the limitation of trying to integrate electronics and photonics on a single-chip. The Figure shows a simplified schematic cross-section of the device.

Full chip cross-section (not to scale) from the silicon substrate to the C4 solder balls, showing the structures of electrical transistors, waveguides, and contacted optical devices. (Source: Nature)

Lead author Chen Sun—affiliated with UC Berkeley and MIT, as well as with commercial enterprise Ayar Labs, Inc.—developed the thermal tuning circuitry, designed the memory bank, implemented the ‘glue-logic’ between various electronic components, and performed top-level assembly of electronics and photonics. The main limitation is the temperature control, since deviation by more than 1°C results in loss of coupling that otherwise provides for P2M/M2P transceivers:

* Waveguide Loss – 4.3 dB/cm,
* Tx and Rx Data Rate – 2.5 Gb/s,
* Tx Power – 0.02 pJ/bit,
* Rx Power – 0.50 pJ/bit, and
* Ring Tuning Control Power – 0.19 pJ/bit, so
* Total power consumption = 0.71 pJ/bit.

The Register reports that this prototype has a bandwidth density of 300 Gb/s per square millimetre, and needs 1.3W to shift a Tb/s straight from the die to off-chip memory. A single chip integrates >70 million transistors and 850 photonic components to provide microprocessor logic, memory, and interconnect functions.

—E.K.

Apple Fab Speculation

Leave a reply

Apple Corp. recent purchased an old 200mm-diameter silicon wafer fab in San Jose capable of creating as small as 90nm device features. Formerly owned and operated by Maxim, the US$18.2M purchase reportedly includes nearly 200 working fab tools. Some people outside the industry have speculated that Apple might use this fab to do R&D on the A10 or other advanced logic chips, but this old tool-set is completely incapable of working on <45nm device features so it’s useless for logic R&D.

As reported at EETimes, this old fab could be used for the R&D of “mixed-signal devices, MEMS and image sensors and for work on packaging.” Those who know do not speak, while those who speak do not know…I do not know so I’m free to join the public speculation. Mixed-signal and MEMS processing would require major re-tooling of the line, but this 15-20 year-old tool-set is nearly turn-key for wafer-level packaging (WLP). With minimal re-tooling, this line could produce through-silicon vias (TSV) or through-mold vias (TMV) as part of Fan-Out WLP (FO-WLP).

Our friends at ChipWorks have published a detailed tear-down analysis of the System-in-Package (SiP) used in the first generation Apple Watch; it contains 30 ICs and many discretes connected by a 4-layer printed circuit board (PCB). Significant power and performance improvements in mobile devices derive from stacking chips in such dense packages, and even greater improvements can found in replacing the PCB with a silicon interposer. With Apple pushing the limits on integrating new functionalities into all manner of mobile devices, it would be strategic to invest in WLP R&D in support of application-specific SiP design.

—E.K.

EUV Cost at 1000 Daily Exposures

Leave a reply

On October 14, 2015, ASML Holding N.V. (ASML) published its 2015 third-quarter results: Q3 net sales of €1.55 billion with gross margin of 45.4% (in line with guidance), and guided Q4 2015 net sales at approximately €1.4 billion and a gross margin of around 45%. Due to mismatched financial analyst expectations, Bloomberg reported that ASML’s stock price dropped ~7% in a single day of trading, despite the company also reporting upgrades to both the TWINSCAN NXT 193nm-immersion (193i) and the NXE Extreme Ultraviolet (EUV) tools. In particular, a new record of 1000 wafer exposures in a single day was set by one EUV tool.

The science of controlling the 13.54nm wavelength electromagnetic radiation that we like to call “Extreme Ultra-Violet” or “EUV” (instead of the colloquial scientific term “soft x-ray”) is inherently challenging. The engineering of EUV Lithography is not just challenging but bordering on inherently impossible: from exploding tin plasma source, to all-reflective lenses that absorb energy, to the trade-offs in mask pattern protection. The team at ASML working on the exposure tool—along with the different specialist organizations still working on improved sources, masks, and resists—deserve the industry’s unwavering admiration for the important work they do every day.

In a prepared statement, ASML President and Chief Executive Officer Peter Wennink said, “We have proven the capability both to expose 1,000 wafers per day and, in a manufacturing readiness test, to expose 15,000 wafers in four weeks. We have also achieved a four-week average availability of more than 70 percent at multiple customer sites. The first shipment of our fourth-generation EUV lithography system, the NXE 3350B, is in progress, with two more expected to ship in Q4.”

Still, progress along desired EUV roadmaps continues to be slow, and the competitive target shifts when the 193i exposure tool gains a 10% throughput improvement to 275 wafer-passes/hour (wph). When the 193i tool gains a 30% overlay improvement, that means double-patterning based on litho-etch-litho-etch (LELE) process flows gain in pattern fidelity. Since ASML provides both technologies, delays in orders for EUV just means more sales of 193i tools.

Let’s play with the numbers here…275 wph x 20 hours x 30 days = 165k wafer-passes/month for the NXT:1980. The NXE:3350B can current handle 15k wafer-passes/month. So even if the tools were equally priced, just based on tool depreciation each EUV exposure today costs >10x that of a 193i exposure, which is why pitch-splitting multi-patterning 193i continues to dominate.

—E.K.

Leti Shows MEMS on 300mm Wafers

Leave a reply

As reported by EETimes from the European MEMS Summit last month, French research institute CEA-Leti has manufactured accelerometer MEMS devices on 300mm-diameter wafers. This technology is currently being transferred to Tronics Microsystems SA (Grenoble, France), which currently only manufactures on 200mm wafers. Since CEA-Leti has long functioned as the R&D group for STMicroelectronics (ST), and previously led the way for ST to produce MEMS chips on 200mm-diameter wafers, we may expect that 300mm-wafer MEMS processing is now on ST’s internal roadmap.
Moving production to larger wafers makes sense when either the chip-size or the manufacturing volume increase in size. Much of the growth in demand for MEMS is for so-called “combo” sensors that combine multiple sensor technologies, such as CEA-Leti’s piezo-resistive silicon nanowire technology which allows the accelerometer, gyroscope, magnetometer, and pressure sensor capability to be integrated on the same chip.
The compatibility of Leti’s 200mm-developed technologies with 300mm wafer fabrication, “shows a significant opportunity to cut MEMS production costs,” said Leti CEO Marie Semeria in a press release. “This will be especially important with the worldwide expansion of the Internet of Things and continued growing demand for MEMS in mobile devices.” Sensors of all sorts will be needed for all of the different “Things” to be able to capture new useful information, so we may expect that demand for combo MEMS devices will continue to increase.
—E.K.

Cross-point ReRAM Integration Claimed by Intel/Micron

Leave a reply

The Intel/Micron joint-venture now claims to have successfully integrated a Resistive-RAM (ReRAM) made with an unannounced material in a cross-point architecture, switching using an undisclosed mechanism. Pilot production wafers are supposed to be moving through the Lehi fab, and samples to customers are promised by end of this year.
HP Labs announced great results in 2010 on prototype ReRAM using titania without the need for a forming step, and then licensed the technology to Hynix with plans to bring a cross-point ReRAM to market by 2013. SanDisk/Toshiba have been working on ReRAM as an eventual replacement for NAND Flash for many years, with though a bi-layer 32Gb cross-point ReRAM was shown at ISSCC in 2013 they have so far not announced production.
Let us hope that the folks in Lehi have succeeded where HP/Hynix and SanDisk/Toshiba among others have so far failed in bringing a cross-point ReRAM to market…so this may be a “breakthrough” but it’s by no means “revolutionary.” Until the Intel/Micron legal teams decide that they can disclose what material is changing resistance and by what mechanism (including whether an electrical “forming” step is needed), the best we can do is speculate as to even how much of a breakthrough this represents.
—E.K.

Electronic Materials Specifications and Markets

Leave a reply

At SEMICON West this year, July 14-16 in San Francisco, the Chemical and Gas Manufacturers Group (CGMG) Committee of SEMI have organized an excellent program covering “Contamination Control in the Sub-20nm Era” to occur in the afternoon of the 14th as part of the free TechXPOT series. Recent high-volume manufacturing (HVM) developments have shown much tighter IC control specifications in terms of particles, metal contaminants, and organic contaminants. The session will present a comprehensive picture of how the industry value chain participants are collaborating to address contamination control challenges:
1. IDM / foundry about the evolving contamination control challenges and requirements,
2. OEM process and metrology/defect inspection tools to minimize defects, and
3. Materials and sub-component makers eliminating contaminants in the materials manufacturing, shipment, and dispensing process before they reach the wafer.

Updated reports about the markets for specialty electronic materials have recently been published by the industry analysts at TechCet, including topics such as ALD/CVD presursors, CMP consumables, general gases, PVD targets, and silicon wafers. Strategic inflection points continue to appear in different sub-markets for specialty materials, as specifications evolve to the point that a nano-revolution is needed. One example is TechCet’s recent reporting that 3M’s fixed-abrasive pad for CMP has been determined to be unable to keep up with defect demands below 20nm, and is undergoing an orderly withdrawal from the market.

As in prior years, SEMICON West includes many free and paid technology sessions and workshops, the Silicon Innovation Forum and other business events, as well as a profusion of partner events throughout the week.

—E.K.

Nakamura on blue light history and future

Leave a reply

Nobel Laureate Shuji Nakamura provided the keynote address to the attendees at the 57th annual Electronic Materials Conference held this week in Columbus, Ohio. His talk on “The History and Developments of InGaN-based LEDs and Laser Diodes” informed and entertained the audience of materials researchers, particularly since he followed first-principles of materials science and his natural inspiration to create the world’s first commercially viable blue LEDs over 20 years ago.
Nakamura-sensei is now legendary for showing excellent GaN-based blue LED functionality in an era when ZnSe was the main material explored by almost all scientists in the world due to six orders of magnitude superior defectivity level for the latter material (due to near zero lattice mismatch between ZnSe and GaAs, instead of the extreme mismatch between GaN and sapphire). In the 57th EMC keynote, he confessed that the only reason he began work on GaN was that almost everyone else was ignoring it so he could easily get papers published on the way to earning a Ph.D., and he initially had no plans to try to create a blue LED with the material.
However, when he bought a new MOCVD reactor to grow GaN on sapphire substrates he found the capabilities of the tool to be lacking so he began daily hardware modifications and test runs, and after some months began to get surprisingly strong data. Soon his group at Nichia was reporting world record GaN optoelectronic properties, and had developed both n- and p-type GaN. However, from first principles it was known that a double-heterojunction (DH) structure would allow for band-gap and hence wavelength tuning, so he then developed the world’s first useful InGaN MOCVD process and by 1993 was able to issue a press release claiming 1000 mcd LED output. “Indium gallium nitride is the most important material, but the Nobel committee didn’t say anything about Indium gallium nitride,” reminded Nakamura.
Most of the rest of the story is well known by now, including his precedent-setting lawsuit with Nichia, move to UCSB, and founding of Soraa.
Nakamura’s vision for the the future of blue (and through integration with phosphors “white”) light can be summed up as LEDs are good but lasers are better. Relatively speaking, with lasers the current density can by many times higher, and BMW and Audi have prototype laser headlamps that can reach 2-3x farther down the road compared to the best lamps today. The challenges today are to improve efficiency and cost. Efficiency for blue LEDs are now 50-60% while lasers are only ~30%. Also, blue laser production cost is now ~10x higher than that for blue LEDs.
—E.K.

ALD of Crystalline High-K SHTO on Ge

Leave a reply

Alternative channel materials (ACM) such as germanium (Ge) will need to be integrated into future CMOS ICs, and one part of the integration was shown at the recent Materials Research Society (MRS) spring meeting by John Ekerdt, Associate Dean for Research in Chemical Engineering at the University of Texas at Austin, in his presentation on “Atomic Layer Deposition of Crystalline SrHfxTi1-xO3 Directly on Ge (001) for High-K Dielectric Applications.”

Strontium hafnate, SrHfO3 (SHO), and strontium titanate, SrTiO3 (STO), with dielectric constants of ~15 and ~90 (respectively) can be grown directly on Ge using atomic layer deposition (ALD). Following a post-deposition anneal at 550-590°C for 5 minutes, the perovskite films become crystalline with epitaxial registry to the underlying Ge (001) substrate. Capacitor structures using the crystalline STO dielectric show a k~90 but also high leakage current. In efforts to optimize electrical performance including leakage current and dielectric constant, crystalline SrHfxTi1-xO3 (SHTO) can be grown directly on Ge by ALD. SHTO benefits from a reduced leakage current over STO and a higher k value than SHO. By minimizing the epitaxial strain and maintaining an abrupt interface, the SHTO films are expected to reduce dielectric interface-traps (Dit) at the oxide-Ge interface.

Much of the recent conference has been archived, and can now be accessed online.

—E.K.