Tag Archives: materials

PCM + ReRAM = OUM as XPoint

The good people at TECHINSIGHTS have reverse-engineered an Intel “Optane” SSD to cross-section the XPoint cells within (http://www.eetimes.com/author.asp?section_id=36&doc_id=1331865&), so we have confirmation that the devices use chalcogenide glasses for both the switching layer and the selector diode. That the latter is labeled “OTS” (for Ovonic Threshold Switch) explains the confusion over the last year as to whether this device is a Phase-Change Memory (PCM) or Resistive Random Access Memory (ReRAM)…it seems to be the special variant of ReRAM using PCM material that has been branded Ovonic Unified Memory or “OUM” (https://www.researchgate.net/publication/260107322_Programming_Speed_in_Ovonic_Unified_Memory).

As a reminder, cross-bar ReRAM devices function by voltage-driven pulses creating resistance changes in some material. The cross-bars allow for reading and writing all the bits in a word-string in a manner similar to Flash arrays.

In complete contrast, Phase Change Memory (PCM) cells—as per the name—rely upon the change between crystalline and amorphous material phases to alter resistance. The standard way to change phases is with thermal energy from an integrated set of heater elements. The standard PCM architecture also requires one transistor for each memory cell in a manner similar to DRAM arrays.

Then we have the OUM variant of PCM as previously branded by Energy Conversion Devices (ECD) and affiliated shell-campanies founded by tap-dancer-extraordinaire Stanford Ovshinsky (https://en.wikipedia.org/wiki/Stanford_R._Ovshinsky). So-called “Ovonic” PCM cells see phase-changes driven by voltage pulses without separate heater elements, such that from a circuit architecture perspective they are cross-bar ReRAMs.

Ovshinsky et al. successfully sold this technology to industry many times. In 2000, it was licensed to STMicroelectronics. Also in 2000, it was used to launch Ovonyx with Intel investment (http://www.eetimes.com/document.asp?doc_id=1176621), at which time Intel said the technology would take a long time to commercialize. In 2005 Intel re-invested (http://www.businesswire.com/news/home/20051019005145/en/Ovonyx-Receives-Additional-Investment-Intel-Capital). Finally in 2009, Intel and Numonyx showed a functional 64Mb XPoint test chip at IEDM (http://www.eetimes.com/document.asp?doc_id=1176621).

In 2007, Ovonxyx licensed it to Hynix (http://www.eetimes.com/document.asp?doc_id=1167173), and Qimonda (https://www.design-reuse.com/news/15022/ovonyx-qimonda-sign-technology-licensing-agreement-phase-change-memory.html), and others. All of those license obligations were absorbed by Micron when acquiring Ovonyx (https://seekingalpha.com/article/3774746-micron-tainted-love). ECD is still in bankruptcy (http://www.kccllc.net/ecd/document/list/3153).

So, years of R&D and JVs are behind the XPoint Optane(TM) SSDs. They are cross-bar architecture ReRAM arrays of PCM materials, and had the term not been ruined by 17-years of over-promising and under-delivering they would likely have been called OUM chips. Many others tried and failed, but Intel/Micron finally figured out how to make commercial gigabit-scale cross-bar NVMs using OUM arrays. Now they just have to yield the profits…

—E.K.

EUVL Masks may need to be Tool-Specific

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Extreme Ultra-Violet Lithography (EUVL) keeps hurting my brain. Just when I can understand how it could be used in profitable commercial high-volume manufacturing (HVM) I hear something that seriously strains my brain. First it was the mirrors and mask in vacuum, then it was the resist and pellicle, then it was the source power and availability, and in each case scientists and engineers did amazing work and showed a way to HVM. Now we hear that EUVL might require fabs to park work-in-progress (WIP) lots of wafers behind a single critical tool with an idealistic 80% availability on a good day, and lots of downtime bad days. Horrors!

For “5nm-node” designs the maximum allowable edge placement-error (EPE) in patterning overlay is only 2nm. While the physics of ~13.5nm wavelength EUVL means that aberration in the reflecting mirrors appears as up to 3nm variation in the fidelity of projected patterns. This variation can be measured and compensated for at the physical mask level, but then each mask would only be good for one specific exposure tool. John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—briefly discussed this on February 26th during Nikon LithoVision held just before SPIE Advanced Lithography.

Sturtevant explained that the Zernike coefficients for EUV are inherently almost 1 order-of-magnitude higher than for DUV at 193nm wavelength, as detailed in the SemiMD article “Edge Placement Error Control in Multi-Patterning.” How the inherent physical sources of aberration must be tightened to avoid image distortion and contrast loss as they scale with wavelength was discussed by by Fenger et al. in 2013 in the article “Extreme ultraviolet lithography resist-based aberration metrology” (doi:10.1117/1.JMM.12.4.043001).

—E.K.

Photoelectric measure of atomically thin stacks

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A team led by researchers at the University of Warwick have discovered a breakthrough in how to measure the electronic structures of stacked 2D semiconductors using the photoelectric (PE) effect. Materials scientists around the world have been investigating various heterostructures to create different 2D materials, and stacking different combinations of 2D materials creates new materials with new properties.

The new PE method measures the electronic properties of each layer in a stack, allowing researchers to establish the optimal structure for the fastest, most efficient transfer of electrical energy. “It is extremely exciting to be able to see, for the first time, how interactions between atomically thin layers change their electronic structure,” says Neil Wilson, who helped to develop the method. Wilson is from the physics department at the University of Warwick.

Wilson formulated the technique in collaboration with colleagues at the University of Warwick, University of Cambridge, University of Washington, and the Elettra Light Source in Italy. The team reported their findings in Science Advances (DOI: 10.1126/sciadv.1601832).

—E.K.

China to be 15% of World Fab Capacity by 2018

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Currently there are eight Chinese 300mm-diameter silicon IC fabs in operation as 2016 comes to a close. Chinese IC fab capacity now accounts for approximately 7% of worldwide 300mm capacity, as reported by VLSIresearch in a recent edition of its Critical Subsystems report (https://www.vlsiresearch.com/public/csubs/). This will expand rapidly, as ten are now under construction and two more have been announced. China’s 300mm fabs are located in ten cities.

“Total Chinese capacity is expected to be around 13 million by end 2018,” said John West of VLSI Research. Worldwide 300mm wafer fabrication capacity will exceed 85 million wafers per year in 2018, putting China in control of 15% of worldwide 300mm capacity in 2018. While new Chinese fabs have yet to prove they can produce leading edge silicon ICs with high yields, it should be only a matter of time before they prove they stand among the world’s great semiconductor production regions.

West recently presented a China market outlook for semiconductors, original equipment manufacturers (OEM), and critical subsystems at the recent Critical Materials Council (CMC) Seminar (http:cmcfabs.org/seminars) held in Shanghai. At the same event, representatives from Intel and TI discussed supply-chain dynamics in China, and Secretary General Ingrid Shi of the Integrated Circuit Materials Industry Technology Innovative Alliance (ICMITIA) presented on “The China Materials Supply Consortium and China’s 5 Year Technology Plan.”

The 2016 CMC Seminar also saw a presentation of China’s first semiconductor-grade 300mm silicon wafer supplier: the recently unveiled Zing Semiconductor (www.zingsemi.com). Founder and CEO Richard Chang, co-founder of SMIC, has assembled a team and funding to start creating wafers in the Pudong region of Shanghai. He showed a photo of his company’s first 300mm silicon boule at the event.

[DISCLOSURE: Ed Korczynski is also Marketing Director for TECHCET CA, an advisor firm that administers the Critical Materials Council and CMC events.]

—E.K.

Dan Rose departs material realm

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Daniel J. Rose, Ph.D.
November 7, 1937 – September 20, 2016

With sadness I post that Daniel J. Rose, Ph.D.—founder of Rose Associates—passed away on September 20, 2016, due to complications of Alzheimer’s disease. Dan Rose received a Ph.D. in materials engineering from the University of British Columbia, and subsequently spent five years managing packaging manufacturing operations at Fairchild Semiconductor. He worked with and become friends with industry luminaries such as Intel’s founder Robert Noyce, and National Semiconductor’s founder Charlie Sporck.

In February of 1970, he founded Rose Associates, which initially provided engineering and manufacturing support to the semiconductor industry, establishing factories in the US and assembly plants in the Far East. In 1977, Rose Associates began conducting market research in electronic materials. In January of 1985, Rose Associates began publishing the Electronic Materials Report (EMR) monthly newsletter, and In 1986 held its first annual Electronic Materials Conference.

Dan Tracy, Ph.D.— SEMI Senior Director, Industry Research & Statistics—was one of Rose’s associates who joined the trade organization in 2000 when it acquired Rose Associates’ business. Tracy wrote a wonderfully heartfelt remembrance as a LinkedIn Pulse article (https://www.linkedin.com/pulse/dr-daniel-j-rose-phd-dan-tracy?trk=hb_ntf_MEGAPHONE_ARTICLE_POST).

—E.K.

Eloquent Executives Ecosystem Expositions

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#cmc,#confab,#namedropping

With dimensional scaling reaching economic limits, each company in the IC fab industry must rely upon trusted connections with customers and suppliers to know which way to go, and the only way to gain trusted connections is through attending live events. Fortunately, whether you are an executive, and engineer, or an investor, there is at least one must-attend event happening these days to keep you informed.

We should always start with SEMI (sponsor of SemiMD, personal friends for many years) who has always represented the gold standard for trade-shows, executive events, and manufacturing symposia around the world. I attended my first SEMICON/West in 1988, and have since attended excellent SEMICONs in Europe, Japan, Korea, China, and Singapore. This year’s SEMICON gathering in San Francisco will feature a nearly 50% increase in the number of technical sessions.

SEMI ran another excellent Advanced Semiconductor Manufacturing Conference (ASMC) in Albany this month, featuring keynotes by visionaries such as “Nanoscale III-V CMOS” by MIT Professor Jesus A. del Alamo. The panel discussion “Moore’s Law Wall vs. Moore’s Wallet, and where do we grow from here,” was moderated by industry veteran Paul Werbaneth, now with Intevac. It is clear that we will reach economic limits of scaling well before the physical limits.

Materials technology and supply-chain solutions to extend economic limits were discussed by Intel’s VP of Technology and Manufacturing Tim Hendry in a keynote at the Critical Materials Conference (CMC) held this year in Oregon in early May, as produced by Techcet CA (I am also an analyst with Techcet and co-chair of this event, while Solid State Technology was a media sponsor). David Thompson, Senior Director, Center of Excellence in Chemistry, Applied Materials showed that despite the inherent “Agony in New Material Introductions – minimizing and correlating variabilities” is possible with improved collaboration throughout the supply-chain.

The Imec Technology Forum in Brussells this month (Solid State Technology was a media sponsor) could best be described with Lake Wobegone hyperbole that all the women were strong, the men were good-looking, and everyone was above average. The big news is imec acquiring iMinds for greater synergies when integrating the latter’s algorithms with imec-ecosystem hardware for application-specific solutions. Gary Patton, now CTO and SVP of Global R&D for GLOBALFOUNDRIES, reminded everyone at ITF of the inherent speed constraints of the copper wires and low-k dielectrics needed to connect IC transistors, “As I’ve often said, It’s like you have a Ferrari but you’re towing a boat if you don’t address the interconnect delay issues.” Regardless, Patton confidently declares that, “We will continue to provide value to our customers to be able to create new products, and we will innovate in ways other than simple scaling.”

At ITF, a video was shown of imec president Luc van den Hove interviewing Gordon Moore at his beachfront home in Hawaii. Moore has always been humble and claims no special ability to forecast trends. “It would not surprise me if we reached the end of scaling in the next decade,” said Moore. “I missed the importance of the PC, and I missed the importance of the internet. Predicting the future is a difficult job and I leave it to someone else.”

Wally Rhines seemed able to predict the future when he eloquent expounded upon Moore’s Law as a special-case learning-curve in his presentation at ITF. Rhines will provide one of the keynote addresses at the ConFab in Las Vegas this year (Solid State Technology’s home event, co-sponsored by SEMI and by IEEE-CPMT). Executives from the global industry will gather to hear insights and analysis on the challenges facing all companies in the ecosystem, as we search for profitable pathways in a more complex landscape.

—E.K.

SAQP Specs for 7nm finFETs

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As discussed in my last Ed’s Threads, lithography has become patterning as evidenced by first use of Self-Aligned Quadruple Patterning (SAQP) in High Volume Manufacturing (HVM) of memory chips. Meanwhile, industry R&D hub imec has been investigating use of SAQP for “7nm” and “5nm” node finFET HVM, as reported as SPIE-AL this year in Paper 9782-12.
The specifications for pitches ranging from 18 to 24 nanometers are as follow:

7.0nm Critical Dimension (CD) after etch,
0.5nm (3sigma) CD uniformity (CDU), and
<1nm Line-Width and Line-End Roughness (LWR and LER) assuming 10% of CD.

“Pitch walk”—variation in final pitch after multi-patterning—results in different line widths, and can result in subsequent excessive etch variation due to non-uniform loading effects. To keep the pitch walk in SAQP at acceptable levels for the 7nm node, the core-1 CDU has to be 0.5nm 3sigma and 0.8nm range after both litho and etch. In other presentations at SPIE-AL this year, the best LER after litho was ~4nm, improving to ~2nm after PEALD smoothing of sidewalls, but still double the desired spec.

The team at imec developed a SAQP flow using amorphous-Carbon (aC) and amorphous-Silicon (aSi) as the cores, and low-temperature Plasma-Enhanced Atomic-Layer Deposition (PEALD) of SiO2 for both sets of spacers. Bilayer DARC (SiOC) and BARC were used for reflectivity control. Compared to SAQP schemes where the mandrels are only aSi, imec claims that this approach saves 20% in cost due to the use of aC core and the elimination of etch-stopping-layers.

—E.K.

Litho becomes Patterning

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Once upon a time, lithographic (litho) processes were all that IC fabs needed to transfer the design-intent into silicon chips. Over the last 10-15 years, however, IC device structural features have continued to shrink below half the wavelength of the laser light used in litho tools, such that additional process steps are needed to form the desired features. Self-Aligned Double Patterning (SADP) schemes use precise coatings deposited as “spacers” on the sidewalls of mandrels made from developed photoresist or a sacrificial material at a given pitch, such that after selective mandrel etching the spacers pitch-split. SADP has been used in HVM IC fabs for many years now. Self-Aligned Quadruple Pattering (SAQP) has reportedly been deployed in a memory IC fab, too.

An excellent overview of the patterning complexities of SAQP was provided by Sophie Thibaut of TEL in a presentation at SPIE-AL on “SAQP integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications.” Use of a spacer-on-spacer process flow—enabled by clever combinations of SiO2 and TiO2 spacers deposited by Atomic Layer Deposition (ALD)—requires the following unit-process steps:
1 193i litho,
2 ALD spacers,
2 wet etches, and
4 plasma etches.

Since non-litho processes dominate the transfer of design-intent to silicon, from first principles we should consider such integrated flows as “patterning.” Etch selectivity to remove one material while leaving another, and deposition dependent on underlying materials determine much of the pattern fidelity. Such process flows are new to IC fabs, but have been used for decades in the manufacturing of Micro-Electrical Mechanical Systems (MEMS), though generally on a patterning length scale of microns instead of the nanometers needed for advanced ICs. R&D labs today are even experimenting with Self-Aligned Octuple Patterning (SAOP), and based on the legacy of MEMS processing it certainly could be done.

—E.K.

Controlling Polymers to Tune TFTs

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Thin-film transistors (TFT) created using only additive process steps could create new low-cost ICs with functionalities beyond silicon, but only if we understand how to control structures at the molecular level. Thin films of conjugated polymers such as poly(3-hexylthiophene) (P3HT) can provide useful conductivity when the electron mobilities are controlled within as well as between molecules. In producing TFTs using such organic macromolecules, we must rigorously control the deposition and annealing processes so that the right molecules line up in the right order.
Peter F. Green, Professor of Chemical Engineering, Macromolecular Science and Engineering at the University of Michigan, and his team fabricated ~55 nm thin films of P3HT using resonant-infrared matrix-assisted pulsed laser evaporation (RIR-MAPLE), as well as conventional spin-casting. The films produced by MAPLE show a higher degree of structural disorder, with localized trap sites that reduce mobility out-of-plane by an order of magnitude compared to spin-cast films.

(Source: Peter Green, University of Michigan)

The Figure shows that despite the disorder of MAPLE-deposited P3HT, enhanced carrier density at the dielectric interface allows TFTs to exhibit similar in-plane mobilities to those built using conventionally spin-coated films. TFTs were top-contact, bottom-gate designs on 300nm thermal oxide on highly doped silicon. In-plane carrier mobilities of MAPLE-deposited versus spin-cast films were 8.3 versus 5.5 (×10 -3 cm2/V/s). In principle, the ability to independently control in- and out-of-plane mobilities allows for the fine tuning of TFT parameters for different applications.
—E.K.

CMOS-Photonic Integration Thermally Sensitive

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As published in the journal Nature, CMOS transistors have been integrated with optical-resonator circuits using complex on-chip sensors and heaters to maintain temperature to within 1°C. While lacking the laser-source, these otherwise-fully-integrated solutions demonstrate both the capability as well as the limitation of trying to integrate electronics and photonics on a single-chip. The Figure shows a simplified schematic cross-section of the device.

Full chip cross-section (not to scale) from the silicon substrate to the C4 solder balls, showing the structures of electrical transistors, waveguides, and contacted optical devices. (Source: Nature)

Lead author Chen Sun—affiliated with UC Berkeley and MIT, as well as with commercial enterprise Ayar Labs, Inc.—developed the thermal tuning circuitry, designed the memory bank, implemented the ‘glue-logic’ between various electronic components, and performed top-level assembly of electronics and photonics. The main limitation is the temperature control, since deviation by more than 1°C results in loss of coupling that otherwise provides for P2M/M2P transceivers:

* Waveguide Loss – 4.3 dB/cm,
* Tx and Rx Data Rate – 2.5 Gb/s,
* Tx Power – 0.02 pJ/bit,
* Rx Power – 0.50 pJ/bit, and
* Ring Tuning Control Power – 0.19 pJ/bit, so
* Total power consumption = 0.71 pJ/bit.

The Register reports that this prototype has a bandwidth density of 300 Gb/s per square millimetre, and needs 1.3W to shift a Tb/s straight from the die to off-chip memory. A single chip integrates >70 million transistors and 850 photonic components to provide microprocessor logic, memory, and interconnect functions.

—E.K.