Tag Archives: fab

PCM + ReRAM = OUM as XPoint

The good people at TECHINSIGHTS have reverse-engineered an Intel “Optane” SSD to cross-section the XPoint cells within (http://www.eetimes.com/author.asp?section_id=36&doc_id=1331865&), so we have confirmation that the devices use chalcogenide glasses for both the switching layer and the selector diode. That the latter is labeled “OTS” (for Ovonic Threshold Switch) explains the confusion over the last year as to whether this device is a Phase-Change Memory (PCM) or Resistive Random Access Memory (ReRAM)…it seems to be the special variant of ReRAM using PCM material that has been branded Ovonic Unified Memory or “OUM” (https://www.researchgate.net/publication/260107322_Programming_Speed_in_Ovonic_Unified_Memory).

As a reminder, cross-bar ReRAM devices function by voltage-driven pulses creating resistance changes in some material. The cross-bars allow for reading and writing all the bits in a word-string in a manner similar to Flash arrays.

In complete contrast, Phase Change Memory (PCM) cells—as per the name—rely upon the change between crystalline and amorphous material phases to alter resistance. The standard way to change phases is with thermal energy from an integrated set of heater elements. The standard PCM architecture also requires one transistor for each memory cell in a manner similar to DRAM arrays.

Then we have the OUM variant of PCM as previously branded by Energy Conversion Devices (ECD) and affiliated shell-campanies founded by tap-dancer-extraordinaire Stanford Ovshinsky (https://en.wikipedia.org/wiki/Stanford_R._Ovshinsky). So-called “Ovonic” PCM cells see phase-changes driven by voltage pulses without separate heater elements, such that from a circuit architecture perspective they are cross-bar ReRAMs.

Ovshinsky et al. successfully sold this technology to industry many times. In 2000, it was licensed to STMicroelectronics. Also in 2000, it was used to launch Ovonyx with Intel investment (http://www.eetimes.com/document.asp?doc_id=1176621), at which time Intel said the technology would take a long time to commercialize. In 2005 Intel re-invested (http://www.businesswire.com/news/home/20051019005145/en/Ovonyx-Receives-Additional-Investment-Intel-Capital). Finally in 2009, Intel and Numonyx showed a functional 64Mb XPoint test chip at IEDM (http://www.eetimes.com/document.asp?doc_id=1176621).

In 2007, Ovonxyx licensed it to Hynix (http://www.eetimes.com/document.asp?doc_id=1167173), and Qimonda (https://www.design-reuse.com/news/15022/ovonyx-qimonda-sign-technology-licensing-agreement-phase-change-memory.html), and others. All of those license obligations were absorbed by Micron when acquiring Ovonyx (https://seekingalpha.com/article/3774746-micron-tainted-love). ECD is still in bankruptcy (http://www.kccllc.net/ecd/document/list/3153).

So, years of R&D and JVs are behind the XPoint Optane(TM) SSDs. They are cross-bar architecture ReRAM arrays of PCM materials, and had the term not been ruined by 17-years of over-promising and under-delivering they would likely have been called OUM chips. Many others tried and failed, but Intel/Micron finally figured out how to make commercial gigabit-scale cross-bar NVMs using OUM arrays. Now they just have to yield the profits…

—E.K.

Moore’s Law Smells Funny

…maybe we need “Integrated Cleverness Law”

“Jazz is not dead, it just smells funny.” – Frank Zappa 1973
from Be-Bop Tango (Of The Old Jazzmen’s Church)

Marketing is about managing expectations. IC marketing must position next-generation chips as adding significant new/improved functionalities, and for over 50 years the IC fab industry has leaned on the conceptual crutch of “so-called Moore’s Law” (as Gordon Moore always refers to it) to do so. For 40 years the raw device count was a good proxy for a better IC, but since the end of Dennard Scaling the raw transistor count on a chip is no longer the primary determinant of value.

Intel’s has recently released official positions on Moore’s Law, and the main position is certainly correct:  “Advances in Semi Manufacturing Continue to Make Products Better and More Affordable,” as per the sub-headline of the blog post by Stacy Smith, executive vice president leading manufacturing, operations, and sales for Intel. Smith adds that “We have seen that it won’t end from lack of benefits, and that progress won’t be choked off by economics.” This is what has been meant by “Moore’s Law” all along.

When I interviewed Gordon Moore about all of this 20 years ago (“The Return of Cleverness” Solid State Technology, July 1997, 359), he wisely reminded us that before the industry reaches the limits of physical scaling we will be working with billions of transistors in a square centimeter of silicon. There are no ends to the possibilities of cleverly combining billions of transistors with sensors and communications technologies to add more value to our world. Intel’s recent spend of US$15B to acquire MobileEye is based on a plan to cost-effective integrate novel functionalities, not to merely make the most dense IC.

EETimes reports that at the International Symposium on Physical Design (ISPD 2017) Intel described more than a dozen technologies it is developing with universities and the SRC to transcend the limitations of CMOS. Ian Young, a senior fellow with Intel’s Technology Manufacturing Group and director of exploratory integrated circuits in components research, recently became the editor-in-chief of a new technical journal called the IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, which explores these new CMOS-fab compatible processes.

Meanwhile, Intel’s Mark Bohr does an admirable job of advocating for reason when discussing the size of minimally scaled ICs. Bohr is completely correct in touting Intel’s hard-won lead in making devices smaller, and the company’s fab prowess remains unparalleled.

As I posted here three years ago in my “Moore’s Law Is Dead” blog series, our industry would be better served by retiring the now-obsolete simplification that more = better. As Moore himself says, cleverness in design and manufacturing will always allow us to make more valuable ICs. Maybe it is time to retire “Moore’s Law” and begin leveraging a term like “Integrated Cleverness Law” when telling the world that the next generation of ICs will be better.

—E.K.

EUVL Masks may need to be Tool-Specific

Extreme Ultra-Violet Lithography (EUVL) keeps hurting my brain. Just when I can understand how it could be used in profitable commercial high-volume manufacturing (HVM) I hear something that seriously strains my brain. First it was the mirrors and mask in vacuum, then it was the resist and pellicle, then it was the source power and availability, and in each case scientists and engineers did amazing work and showed a way to HVM. Now we hear that EUVL might require fabs to park work-in-progress (WIP) lots of wafers behind a single critical tool with an idealistic 80% availability on a good day, and lots of downtime bad days. Horrors!

For “5nm-node” designs the maximum allowable edge placement-error (EPE) in patterning overlay is only 2nm. While the physics of ~13.5nm wavelength EUVL means that aberration in the reflecting mirrors appears as up to 3nm variation in the fidelity of projected patterns. This variation can be measured and compensated for at the physical mask level, but then each mask would only be good for one specific exposure tool. John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—briefly discussed this on February 26th during Nikon LithoVision held just before SPIE Advanced Lithography.

Sturtevant explained that the Zernike coefficients for EUV are inherently almost 1 order-of-magnitude higher than for DUV at 193nm wavelength, as detailed in the SemiMD article “Edge Placement Error Control in Multi-Patterning.” How the inherent physical sources of aberration must be tightened to avoid image distortion and contrast loss as they scale with wavelength was discussed by by Fenger et al. in 2013 in the article “Extreme ultraviolet lithography resist-based aberration metrology” (doi:10.1117/1.JMM.12.4.043001).

—E.K.

Flagello to receive Zernike Award at SPIE Advanced Lithography

Flagello-DonisDonis Flagello, president, CEO, and COO of Nikon Research Corporation of America (NRCA), will be presented with the 2017 Frits Zernike Award for Microlithography on Monday 27 February during SPIE Advanced Lithography in San Jose, California. The award, presented annually for outstanding accomplishments in microlithography technology, recognizes Flagello’s leading role in understanding and improving image formation in optical lithography for semiconductor manufacturing.

A prominent member of the industry since the early 1980s and a longtime SPIE Fellow, Flagello has primarily focused on the rigorous application of physics to lithography modeling and problem solving. Early in his career, while at IBM T.J. Watson Research Center, he developed the first practical test for measuring flare in optical lithography tools and made major contributions to high numerical aperture (NA) modeling including vector and polarization effects, and radiometric correction. At ASML he played an important role in providing analysis of aberrations for new systems and high-NA imaging effects due to polarization.

Another notable aspect of his career, Flagello’s presentations at lithography conferences and papers in various journals have inspired a better understanding of optics and resist behavior and helped drive optical lithography forward, colleagues said. “His presentations are known for their combination of humor with a deep understanding of the complex interactions between physical optics and lithographic process technology,” said David Williamson, an NRCA Fellow and previous Frits Zernike Award winner. “His combined theoretical and practical production experience and knowledge are rare in this field.”

—E.K.

XMC becomes YRST or Changjiang Storage

As reported by Digitimes, a major enterprise in Wuhan, China has broken ground on the first of three mega-fabs to produce 3D-NAND chips. The final fab name-plate may ultimately read XMC or YMTC or YRST or possibly Changjiang Storage (not to be confused with GuangDong ChangJiang Storage Battery), but it is over half owned by the Chinese government’s Tsinghua Unigroup.

Total investment in XMC/YRST by Tsinghua Unigroup is reported by Digitimes to be US$24 billion. In 2015 Tsinghua Unigroup bid US$23 billion to buy Micron Technology Corp, but the company was not for sale.

In 2013 as reported at EETimes, the fab re-branded itself as XMC from the former Wuhan XinXin Semiconductor Manufacturing (WXIC). Dr. Simon Yang was CEO of WXIC/XMC from 2012 to last November when he resigned to become the CEO of Yangtze Memory Technologies Co. Ltd.

Two months later the new company is reportedly to be called Yangtze River Storage Technology (YRST), according to DIGITIMES. Meanwhile, Nikkei Asian Review reports that YRST is also known as Changjiang Storage.

High-Volume Manufacturing (HVM) in the first fab is planned for 2018, and the third fab on the campus is expected to bring 300k 300mm wafer-starts-per-month online by 2020. Rick Tsai the ex-CEO of Taiwan Semiconductor Manufacturing (TSMC) and Shih-Wei Sun the ex-CEO of United Microelectronics (UMC) have both reportedly joined Tsinghua Unigroup.

—E.K.

China to be 15% of World Fab Capacity by 2018

Currently there are eight Chinese 300mm-diameter silicon IC fabs in operation as 2016 comes to a close. Chinese IC fab capacity now accounts for approximately 7% of worldwide 300mm capacity, as reported by VLSIresearch in a recent edition of its Critical Subsystems report (https://www.vlsiresearch.com/public/csubs/). This will expand rapidly, as ten are now under construction and two more have been announced. China’s 300mm fabs are located in ten cities.

“Total Chinese capacity is expected to be around 13 million by end 2018,” said John West of VLSI Research. Worldwide 300mm wafer fabrication capacity will exceed 85 million wafers per year in 2018, putting China in control of 15% of worldwide 300mm capacity in 2018. While new Chinese fabs have yet to prove they can produce leading edge silicon ICs with high yields, it should be only a matter of time before they prove they stand among the world’s great semiconductor production regions.

West recently presented a China market outlook for semiconductors, original equipment manufacturers (OEM), and critical subsystems at the recent Critical Materials Council (CMC) Seminar (http:cmcfabs.org/seminars) held in Shanghai. At the same event, representatives from Intel and TI discussed supply-chain dynamics in China, and Secretary General Ingrid Shi of the Integrated Circuit Materials Industry Technology Innovative Alliance (ICMITIA) presented on “The China Materials Supply Consortium and China’s 5 Year Technology Plan.”

The 2016 CMC Seminar also saw a presentation of China’s first semiconductor-grade 300mm silicon wafer supplier:  the recently unveiled Zing Semiconductor (www.zingsemi.com). Founder and CEO Richard Chang, co-founder of SMIC, has assembled a team and funding to start creating wafers in the Pudong region of Shanghai. He showed a photo of his company’s first 300mm silicon boule at the event.

[DISCLOSURE:  Ed Korczynski is also Marketing Director for TECHCET CA, an advisor firm that administers the Critical Materials Council and CMC events.]

—E.K.

Reliable ICs from unreliable devices

In an article published in the most recent issue of imec’s online magazine (http://magazine.imec.be/) titled “Chips must learn how to feel pain and how to cure themselves,” researchers Francky Chatthoor and Guido Groeseneken discuss how to build reliable “5nm-node” ICs out of inherently unreliable transistors. Variability in “zero time” and “over time” performance of individual transistors cannot be controlled below the “7nm-node” using traditional guard-banding in IC design.

“Maybe it means the end of the guard-band approach, but certainly not the end of scaling,” says Groeseneken in the article. “In our research group we measure and tried to understand reliability issues in scaled devices. In the 40nm technology, it is still possible to cope with the reliability issues of the devices and make a good system. But at 7nm, the unreliability of the devices risks to affect the whole system. And conventional design techniques can’t stop this from happening. New design paradigms are therefore urgently needed.” These researchers predict that industry will have to manufacture self-healing chips by the year 2025.

Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec)

Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec)

The ultimate goal of imec and its academic partners is to develop a fully proactive parametric reliability mitigation technique with distributed monitors, a control system and actuators, fully preventing the consequence of delay faults and potentially also of functional faults. Said Catthour, “the secret to the solution lies in the work load variation of the system. Based on a deterministic predictor of the future, you determine future slack and use this to compensate for the delay error at peak load. Based on this info on the future, you change the scheduling order and the assignment of operations.” The Figure shows how self-healing chips can use future slack to compensate for delay error and mitigate at peak load.

—E.K.

Dan Rose departs material realm

Daniel J. Rose, Ph.D. November 7, 1937 – September 20, 2016

Daniel J. Rose, Ph.D.
November 7, 1937 – September 20, 2016

With sadness I post that Daniel J. Rose, Ph.D.—founder of Rose Associates—passed away on September 20, 2016, due to complications of Alzheimer’s disease. Dan Rose received a Ph.D. in materials engineering from the University of British Columbia, and subsequently spent five years managing packaging manufacturing operations at Fairchild Semiconductor. He worked with and become friends with industry luminaries such as Intel’s founder Robert Noyce, and National Semiconductor’s founder Charlie Sporck.

In February of 1970, he founded Rose Associates, which initially provided engineering and manufacturing support to the semiconductor industry, establishing factories in the US and assembly plants in the Far East. In 1977, Rose Associates began conducting market research in electronic materials. In January of 1985, Rose Associates began publishing the Electronic Materials Report (EMR) monthly newsletter, and In 1986 held its first annual Electronic Materials Conference.

Dan Tracy, Ph.D.— SEMI Senior Director, Industry Research & Statistics—was one of Rose’s associates who joined the trade organization in 2000 when it acquired Rose Associates’ business. Tracy wrote a wonderfully heartfelt remembrance as a LinkedIn Pulse article (https://www.linkedin.com/pulse/dr-daniel-j-rose-phd-dan-tracy?trk=hb_ntf_MEGAPHONE_ARTICLE_POST).

—E.K.

Broadening Scope of SEMICON

Once upon a time, SEMICONs were essentially just for semiconductor manufacturing business and technology, and predominantly CMOS ICs. Back when we followed public roadmaps for technology to maintain the cadence of new manufacturing nodes in support of Moore’s Law, it was sufficient to focus on faster transistors connected with tighter wires. Now in an era that is at least partially “More-than-Moore”—as we like to refer to heterogeneous integration of non-CMOS technologies into commercial ICs—SEMICON West 2016 will focus on technologies beyond silicon CMOS such as MEMS and flexible organic semiconductors.

Alissa Fitzgerald, founder and managing member of AM Fitzgerald & Associates, will present on some of these themes Wednesday afternoon during the “What’s Next in MEMS and Sensors: Innovations to Drive the Next Generation of Growth” session (Track 2) of SEMICON’s Advanced Manufacturing Forum. Much of that growth is expected to be in sensors, microprocessors, ultra-low-power supplies, and communications chips to support the Internet of Things (IoT) connected by high-speed 5G data networks.

Flexible/Hybrid Electronics Forum at SEMICON West this year includes two full days of excellent presentations on new technologies that include thinned device processing, device/sensor integrated printing and packaging, and reliability testing and modeling. The following is the full list of forums this year:

  • Advanced Manufacturing,
  • Advanced Packaging,
  • Extended Supply-Chain,
  • Flexible/Hybrid Electronics,
  • Silicon Innovation,
  • Sustainable Manufacturing,
  • Test, and
  • World of IoT.

Partner programs include focused forums discussing trends in technology, markets, and the business of commercial IC fabrication. The industry’s default center of “More Moore” R&D is now imec in Belgium, and invited attendees of the imec technology forum (ITF) in San Francisco happening on July 11th the day before the start of SEMICON West will learn about the latest results in CMOS device shrinking from finFETs to nanowires. The next evening, French R&D and pilot manufacturing center CEA-Leti will lead a workshop detailing how to partner with the organization to bring sensor-based “More-than-Moore” technologies to market. Thursday morning will feature the Entegris Yield Breakfast Forum discussing the need for new materials handling solutions due to “Yield Enhancement Challenges in Today’s Memory IC Production.”

As the official event website summarizes:  We’ve deepened our reach across the full electronics manufacturing supply chain to connect you with more key players — including major industry leaders like Cisco, Samsung, Intel, Audi, Micron, and more. New players, demand generators, systems integrators, and emerging industry segments — all connecting in one place. Keynote presentations will be provided by Cisco Systems, Kateeva, and Oracle.

—E.K.

Eloquent Executives Ecosystem Expositions

#cmc,#confab,#namedropping

With dimensional scaling reaching economic limits, each company in the IC fab industry must rely upon trusted connections with customers and suppliers to know which way to go, and the only way to gain trusted connections is through attending live events. Fortunately, whether you are an executive, and engineer, or an investor, there is at least one must-attend event happening these days to keep you informed.

We should always start with SEMI (sponsor of SemiMD, personal friends for many years) who has always represented the gold standard for trade-shows, executive events, and manufacturing symposia around the world. I attended my first SEMICON/West in 1988, and have since attended excellent SEMICONs in Europe, Japan, Korea, China, and Singapore. This year’s SEMICON gathering in San Francisco will feature a nearly 50% increase in the number of technical sessions.

SEMI ran another excellent Advanced Semiconductor Manufacturing Conference (ASMC) in Albany this month, featuring keynotes by visionaries such as “Nanoscale III-V CMOS” by MIT Professor Jesus A. del Alamo. The panel discussion “Moore’s Law Wall vs. Moore’s Wallet, and where do we grow from here,” was moderated by industry veteran Paul Werbaneth, now with Intevac. It is clear that we will reach economic limits of scaling well before the physical limits.

Materials technology and supply-chain solutions to extend economic limits were discussed by Intel’s VP of Technology and Manufacturing Tim Hendry in a keynote at the Critical Materials Conference (CMC) held this year in Oregon in early May, as produced by Techcet CA (I am also an analyst with Techcet and co-chair of this event, while Solid State Technology was a media sponsor). David Thompson, Senior Director, Center of Excellence in Chemistry, Applied Materials showed that despite the inherent “Agony in New Material Introductions – minimizing and correlating variabilities” is possible with improved collaboration throughout the supply-chain.

The Imec Technology Forum in Brussells this month (Solid State Technology was a media sponsor) could best be described with Lake Wobegone hyperbole that all the women were strong, the men were good-looking, and everyone was above average. The big news is imec acquiring iMinds for greater synergies when integrating the latter’s algorithms with imec-ecosystem hardware for application-specific solutions. Gary Patton, now CTO and SVP of Global R&D for GLOBALFOUNDRIES, reminded everyone at ITF of the inherent speed constraints of the copper wires and low-k dielectrics needed to connect IC transistors, “As I’ve often said, It’s like you have a Ferrari but you’re towing a boat if you don’t address the interconnect delay issues.” Regardless, Patton confidently declares that, “We will continue to provide value to our customers to be able to create new products, and we will innovate in ways other than simple scaling.”

At ITF, a video was shown of imec president Luc van den Hove interviewing Gordon Moore at his beachfront home in Hawaii. Moore has always been humble and claims no special ability to forecast trends. “It would not surprise me if we reached the end of scaling in the next decade,” said Moore. “I missed the importance of the PC, and I missed the importance of the internet. Predicting the future is a difficult job and I leave it to someone else.”

Wally Rhines seemed able to predict the future when he eloquent expounded upon Moore’s Law as a special-case learning-curve in his presentation at ITF. Rhines will provide one of the keynote addresses at the ConFab in Las Vegas this year (Solid State Technology’s home event, co-sponsored by SEMI and by IEEE-CPMT). Executives from the global industry will gather to hear insights and analysis on the challenges facing all companies in the ecosystem, as we search for profitable pathways in a more complex landscape.

—E.K.