Before we get started in this weeks ECTC topic, I wanted to mention that old friend John Lau from ITRI pulled me aside at the ITRI booth to show me a functional example of the interposer test vehicle that we discussed in IFTLE 52 ("3D and Adv Pkging at ICEP 2011). ITRI had several 3D IC focused presentations at this years conference (see below). 3D integration continues to receive considerable attention due to its envisioned potential to alleviate or reduce performance limitations in continued CMOS scaling
Details on 3D Processing Issues
Effect of Etch Rate on Scalloping During Bosch Etching – ITRI
ITRI discussed their Bosch Etching process in detail. In general, the higher the etch rates the larger the scallops; for 1μm-dia TSVs, the effect of etch rate on the scallop is very small and the scalloping ranges from 57 nm to 83 nm (etch rate 1.7μm/min – 2.13μm/min); for 10μm-dia TSVs, the scalloping ranges from 107 nm to 278 nm (etch rate 3.5μm/min – 5.8μm/min), for 20μm-dia TSVs, scalloping is sizable ranging from 93 nm to 225 nm (for etch rate 4.2μm/min – 8.8μm/min); for 30μm-dia TSVs scalloping is significant, ranging from 97 nm to 258 nm (etch rate 4.6μm/min – 9.5μm/min); and for 50μm dia TSVs scallop is large ranging from 99 nm to 235 nm (etch rate 5.2μm/min – 11μm/min).
ITRI lists the following issues to be considered for high quality etching:
Impact of Slurry in Cu CMP – ITRI
ITRI discusses the minimization of dishing during the removal of thick Cu plating overburden due to filling TSVs and backside isolation oxide CMP for TSV Cu exposure. In order to obtain a minimum Cu dishing on the TSV region, proper selection of Cu slurries and a two-step Cu polishing process was developed. The bulk of Cu is removed with the slurry of high Cu removal rate and then the Cu surface is planarized with the slurry of high Cu passivation capability at the second step. The Cu dishing can be improved up to 97% for the 10μm-diameter TSVs on a 300 mm wafer. They reached the following conclusions:
1. For Cu slurry selections for the wafer front side Cu CMP for TSVs and RDLs, the slurries of high removal rate should go along with that of high passivation capability to reduce the metal dishing. Using the slurry with high Cu removal rate to remove the thick Cu overburden on the field and changing to the slurry with high Cu passivation capability to clean the remaining Cu tends to have a much less metal dishing.
2. The Cu plating performance affects the metal/oxide dishing/erosion after CMP. Minimizing metal recess or dimple right on the patterns after Cu plating is an important indicator for reducing dishing/erosion after CMP. For TSV plating, transferring from Cu recess to Cu protrusion will lead to a much smaller post-CMP metal dishing.
3. Wafer edge trimming procedure before temporary bonding and backside grinding reduces edge chipping for the subsequent processes. 0.5 mm edge trimming can eliminate the edge chipping issue for a thinned wafer.
4. For backside oxide CMP for TSV Cu exposure, low pressure should be used to reduce edge chipping during processing.
Selection of Adhesive Materials for Temporary Bonding – ITRI
Most thin-wafer handling solutions are wafer-support-systems: the wafer to be thinned is temporarily bonded on a supporting wafer with an adhesive and thinned down to the required thickness to expose the through silicon vias TSVs. Thin-wafer handling systems can be classified by the five material solutions [Brewer Science(BSI), 3M, TOK, DuPont and Thin Materials (T-MAT),] available through equipment vendors such as EVG, Suss and TOK.
The different material vendors provide various temporary bonding and de-bonding methods which significantly influence the material selection, equipment in demand and choice of silicon vs glass carrier. De-bonding processes involve various release methods including : (a) mechanical (TMAT), (b) thermal (BSI), (c) solvent (BSI, TOK), and (d) laser (3M, DuPont). A transparent glass wafer is required to serve as the carrier for UV cure and laser release which costs more than a normal Si carrier.
ITRI has shared the following conclusions:
1. Wafer thinning and PECVD-SiO2 deposition are the most critical steps for backside processes in thin-wafer handling making it only necessary to qualify an adhesive for these two conditions.
2. Backside polymer isolation is suggested to replace the backside PECVD SiO2 step (where possible) to alleviate thin-wafer processing issues.
3. /span>No obvious change or de-lamination occurred in all the chemical resistance tests for the different adhesive options.
4. The TTV performance of composite wafers with thinner adhesive has been found to be much better than that with thicker adhesive (100μm. Good TTV control for thicker adhesive still has to be developed.
Wafer thinning and back side processing – IMEC
The temporary bonding approach followed by IMEC is based on Brewer Science WaferBond HT-10.10. After the HT 10.10 layer shows an average thickness of 16.2μm and a thickness variation of about 1μm across a 300 mm wafer. The wafer is thinned down by back grinding to a thickness typically leaving 57μm Si remaining for a TSV depth of 50μm. The total thickness variation (TTV) of the thin wafer after grinding is in the range of 1.6μm across a 300 mm wafer.
After thinning, an isotropic dry recess etch process reveals the TSVs while keeping the Cu protected in the oxide liner. The presence of the oxide liner prevents Cu oxidation that could occur during subsequent steps of the process flow. Without any CMP step during nail reveal, the TSV depth variation of about 1μm across the device wafers is measured by high resolution profilometry.
After nail reveal, a thermally compatible low temperature nitride passivation layer is deposited below 200°C. This passivation layer prevents Cu diffusion through the thin wafer to the FEOL active layers when redistribution layers or microbumps are processed on the backside prior to stacking. A nitride layer was been selected over an oxide layer based on the barrier properties of the 2 materials.
Metrology and Inspection During Bonding and Thinning – IMEC
For the in-line monitoring of the 3D wafers in the bonding and thinning module IMEC has examined the SPARK platform from NandaTech which has both brightfield and darkfield inspection capabilities.
There are several key metrology and inspection (M and I) challenges that need to be solved for successful 3D stacking of dies. The most critical steps have been identified to be TSV depth control, glue layer defects and control of the grinding process.
In the TSV module the critical metrology needs are measurements of via depth during etch and also detection of voids after via fill. If there are any depth variations over the wafer it translates to TSV height variations and this can become important during the grinding procedure. This depth variation should be feed-forwarded to the grinder so that the grinding can stop at a safe distance from the TSVs.
During the bonding of the device wafer to the carrier, glue layer defects larger than a few microns become critical. If these glue layer defects are not detected pre-thinning they propagate to the device wafer. Therefore, it is equally important to have the right in-line metrology to detect defects after bonding which would indicate the presence of glue layer defects.
During grinding it is absolutely vital to the residual Si thickness above the TSVs so that the TSVs are not prematurely exposed. The basic idea is to use a certain wavelength which will only partially penetrate the Si layer (i.e. lambda= 650 to 750 nm penetrates 1.5μm to 3.5μm) and then scan the wafer. If there is a TSV buried deeper than 3.5μm it won’t be scattering light. A map of residual Si thickness above the TSV can be generated from the image.
A proper feed-forward and a feedback system is necessary between the TSV, Bonding and Thinning modules to compensate for process variations.
Wafer Level Molding for 3D Components – Samsung
Wafer molding is carried out in the chip-to-wafer process to ensure suitable levels of mechanical strength are reached. The key to wafer level mold processing is the reduction of warpage.
Samsung has studied material issues optimized the wafer molding process to reduce warpage. CTE mismatch between 50um thinned wafer and mold compounds is the primary challenge. Test vehicles (bottom wafers, top chips) were fabricated on 300 mm wafers. A top chip of 8×8 mm2 size was designed and the bottom chip (including TSVs) was designed to a 12×12 mm2 size with 50um thickness. Before wafer molding, a supporting carrier was attached to the backside of the bottom wafer for wafer processing, backside via exposure and pad finishing. The top chips were then stacked on the wafer. After molding, the carrier wafer was detached and diced. The molded unit device’s warpage after dicing was measured by shadow moiré from room temperature to 240°C.
Molding material modulus, CTE, mold thickness and top chip thickness appear to be the parameters that drive the results. The size of the top chip was the dominant factor for warpage. Warpage variation was mainly found at the overhang area where no top chip is present, which meant that the mold CTE mismatch was worse than inside the top chip area. Thus, a narrow overhang design is important for wafer molding.
Mold compound composition also had a strong influence on warpage as shown in the table below.
Conclusions include:
1. Warpage decreased with increasing bottom chip thickness, and smaller chip size. This was directly related to the stresses encountered by the CTE mismatch between the mold material and silicon chip.
2. Warpage decreased by decreasing the CTE and modulus of the mold material. Low modulus levels decreased the overall stiffness of the package, which is not desirable given that thin wafers need to be manufactured for the TSVs (usually manufactured to under 100μm depth). The minimum modulus values vary according to the packaging process and infrastructure, which is why careful selection of this value is required.
3. Warpage levels can vary for the same mold material type depending on the filler content and resin type. By studying the effects of changing the filler content, it was found that decreasing this quantity improved warpage, as well as affecting the package reliability. The amount of shrinkage during curing of the resin also affected the stress levels in the mold material, and hence the warpage levels as well.
4. Additional research is required to reduce warpage levels at room and high temperature to 40μm and achieve the required reliability levels. Package materials needs more investigation.
For all the latest on 3D IC and advanced packaging stay linked to IFTLE…..
We are trying the address the typo errors in this blog. Please be patient while we try to locate the cause of these errors !
