Zeki Celik, principal engineer in the package design and characterization group at LSI, looked at the thermal characterization of various 2.5 and 3D package configurations. Option 3, where the logic die is not heat sinked to the lid, results in the overall highest TJ, max. Option 2, where the silicon interposer is between the memory and the logic die, can be heat sinked to the lid lowers the overall temperature, but equilibrates the temperature of the memory to the temp of the logic. Option 1, which is the silicon MCM-D option, is the overall best solution with the lowest memory temperature.
Marnie Mattei, senior director of TSV product development at Amkor Technology, examined assembly strategies for interposed products. Primary drivers for interposers, which are now pretty much stansdardized at 100μm thick, are shown below.
Product challenges include:
Die-die / Die-substrate joining
– Micro bump uniformity; method of join; materials
Die-die X-Y spacing
– Fillet sizes and pad metallurgy
– Process assy sequence; micro-join method & materials
Thermal / power management
– Use of lids, stiffeners & passives
– Underfill/resin bleed, adhesive compatibility
– Process assy sequence; micro-join method & materials
Warpage control
– Interposer warpage; substrate warpage
– Top die warpage — top die area density/distribution
Intermediate e-test points
– Process assembly sequence
Available assembly flows in Amkor include:
[tc=thermocompression, NCP=non conductive paste (preapplied underfill); CUF capillary underfill]
Sunil Patel, director of GlobalFoundries’ customer package technology group, looked at backside integration and global supply chain challenges for 2.5 and 3D. He sees some application segregation as follows:
GF’s perspective on supply chain options mimics many others, namely foundry-centric, OSAT-centric, and 3rd party-centric.
Although GF pointed towards many collaborations with customers, OSATs and institutes, no indication was given as to when and how to expect GF to begin volume manufacturing of 2.5 or 3D products. While others have recently proposed that GF manufacturing is imminent, IFTLE does not see this happening just yet; they are probably still a year or two away.
Subramanian S. Iyer is an IBM Fellow and chief technologist at the microelectronics division within IBM Systems & Technology Group, responsible for technology strategy and competitiveness, and functionally for embedded memory and three-dimensional integration. His presentation focused on prospects for 2.5 & 3D integration. Among his main messages:
– Scaling is getting more difficult and expensive and yielding less;
– Bandwidth and latency are at a premium;
– Power management, delivery, distribution, and dissipation are significant;
– Integrating large amounts of low latency memory is a major challenge for modern multi-core processor design;
– 3D achieves high performance and low power (AC); and
– Supply chain management will be the toughest nut to crack
Repeating a theme that Subu has shared at previous conferences, he showed the cross-section of an 11-level-metal, 32nm chip (below) to make the point that due to size miss match, sometimes vias-middle TSV must be connected at upper levels of metal and not at the lowest level as we usually draw them in our cartoons.
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