Eric Beyne of IMEC took a look at 3D challenges and progress. The standard IMEC TSV are 5 x 50um for 3D stacking moving in the future to 3 x 50 and for 10 x 100 for 2.5D interposers.
Beyne notes that nearly all options for debonding from carrier wafers are moving to RT solutions. The previously well accepted slide debonding has a small process window and is difficult with bumps on the glued interface. Brewer Science in conjunction with EVG and Suss Microtech are now promoting the Zonebond process which uses a RT release process.
As a cost reduction option, IMEC is studying the elimination of the CMP process for wafer thinning to 2um TTV on 300mm wafer down to 50um thickness. Beyne favors laminated WUF (wafer level underfilling) vs NUF (no flow underfill pre applied to the substrate) commenting that "Probably lamination is the way to go since it covers the fragile ubumps with UF before the assembly process so it’s better to handle." In addition one achieves lower surface topography using WUF.
Ted Tessier, CTO of Flip Chip Int (FCI) addressed their embedded die packaging JV with Fujikura. Fujikura’s “WABE” technology (Wafer And Board Level Device Embedded technology) involves stacking and lamination of multiple layers of Cu/PI printed circuit layers around embedded, thinned die and passive components and via filling with conductive paste. Packages can be fabricated in either a face up or face down orientation with backside thermal via options available for improved thermal performance. Multiple die and passive components can be integrated at die spacing as tight as 100um. Passive components can be embedded as well. Processing panel size is currently 250 x 350mm.
Low Temperature (175C deposition ) SiN Barrier is in 300mm production on CMOS image sensor. It is reportedly a dense film with <100MPa residual stress and excellent adhesion and electrical properties. Low Temperature PE-TEOS SiO2 is deposited at 175C with low leakage and high breakdown voltage. Etch and deposition are available on one or multiple platforms.
Coming up next — an extensive review of the RTI 3D ASIP Conference………
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