Time Flies When Your Having Fun with 3DIC
Seems like yesterday that the packaging world was hearing that Fujitsu, Toshiba, NEC, Oki, Renesas and others had formed a pre-competative consortium under the Association of Super Advanced Electronics Technologies to study direct connecting of chips with through silicon vias (TSV). It seems like yesterday but it was 1999, 13 years ago.
In Feb 2005 my first article on the topic “Future IC’s Going Vertical” was published in Semiconductor International predicting that the industry would eventually have to move in this direction. A short month later, March 2005 I felt like a prophet when a TSV based 3D stacking approach was described by Intel’s Justin Rattner (todays CTO) at the Spring Developer Forum, with statements like “???????.. stacked wafers and stacked dies using thru-silicon vias are showing promise in meeting the memory bandwidth challenge.”
A year later, in April 2006 headlines from Soeul read “.. Samsung has developed a new "3D" package, which reduces space requirements and increases performance capabilities of today’s multi-chip packages. The company plans to use the technology to improve its NAND Flash packaging starting in 2007” Samsung announced that its new wafer-level processed stack package (WSP) rather than using wire-bonding …. micron-sized holes that penetrate through the silicon vertically to connect circuits directly – TSV. According to Samsung the technology would enable manufacturers of mobile and consumer electronics devices to achieve better electrical performance and design slimmer and high-performance handset designs that provide improved battery time. The announced that the technology would enter mass production in 2007, for NAND Flash packages initially. And that they planned to use WSP for server DRAM stack packages sometime down the road.
A year later, in April of 2007, the headlines were “ IBM has announced that they’re relatively close to going commercial with a "through silicon via" (TSV) technology that will enable them to create high-bandwidth connections between two or more chips in a stacked packaging format." The big news about IBM’s design is that the company intends to start shipping product samples based on this technology in the second half of this year, with full production coming in 2008. "Looks as if TSV will be here faster than anyone previously thought."
Now, thirteen years later ASET is in its 3rd incarnation “the Dream Chip program” , it is obvious that DRAM will be stacked before NAND flash hopefully in HVM by 2013 (not 2007) , IBM has announced a major memory program with Micron (though not in 2008) and we are still awaiting any word of commercialization from Intel. Certainly it’s fair to say that this is taking a bit longer than we all thought, even those of us who were trying to be ultra conservative.
Micon / IBM HMC – further details
IFTLE has been sent a few messages asking for further details on the Hybrid memory cube production.
Micron has announced that they will be manufacturing the memory layers and have contracted with IBM to manufacture the logic layer. Micron will be doing the assembly of the layers at a yet to be disclosed location. For now we can assume they are doing the initial production in Boise. For our initial discussions on this technology see IFTLE 74, “The Micron Memory Cube consortium”.
The technology described by M. G. Farooq of IBM last December at the IEEE IEDM [ see IFTLE 82 “3DIC at the 2011 IEDM???????”] is the technology being used to create the logic layer in the HMC stack (blue layer).
As noted in IFTLE 82, TSVs are integrated at “fatwire” (upper level metal) levels to optimize wire-ability and process complexity with 4 to 12 metal levels including low-k interlevel dielectric (ILD). TSV of < 100 µm depth were etched with near vertical sidewalls at a minimum pitch of 50 µm. An example of this is shown below. It is believed that the Micron logic layers are being done in SOI technology.
The logic layer for the HMC parts will be manufactured at IBM’s advanced semiconductor fab in East Fishkill, N.Y., using the company’s 32nm, high-K metal gate process technology [link]
Chipworks has concluded that “ it appears that the TSVs are annular. Once the lower metal/dielectric stack is formed (including the via dielectric for the metal layer that contacts the TSVs), the TSVs are drilled through to the silicon, and then a Bosch etch is used to drill the vias about 100 µm into the substrate, with a minimum pitch of 50 µm. After drilling, a conformal oxide is deposited, the barrier and seed layers are sputtered in, the copper fill is plated in, and any excess copper is CMP’d off. The dielectric for the contact level metal is put down, and then the top fat-wire metal levels are conventionally defined.” [link]
TEL acquires Nexx
Tokyo Electron Limited (TEL) has acquired semiconductor packaging equipment supplier NEXX. Nexx advanced deposition equipment, including electrochemical deposition (ECD) and physical vapor deposition (PVD) tools will be added to the TEL line of products aimed at back end packaging applications and 3DIC.
Looks a lot like the front end heavy weights Applied, LAM and TEL are going to buy up all the pieces they need to become the 3 heavyweights in packaging and 3D. Consolidation will continue because with fewer and fewer players moving to 22 nm and beyond packaging is a natural evolution for some of these big front end equipment vendors.
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Shin-Etsu Joins EVG Temp Adhesives open platform
Shin-Etsu’s adhesives will be entering qualification trials on EVG’s EZR® (Edge Zone Release) and EZD® (Edge Zone Debond) modules, which support the new ZoneBOND??????? room temperature debonding process. Shin-Etsu is the first participant to announce for the program since its inception late last fall [ see IFTLE 76, “ Adv Pkging at IMAPS 2011: recent 3D Announcements”.
EVG’s ZoneBOND temporary bond / debond solutions and open materials platform include: the use of silicon, glass and other carriers; compatibility with existing, field-proven adhesive platforms; and the ability to debond at room temperature with virtually no vertical force being applied to the device wafer. To support grinding and backside processing at high temperatures and to allow for low-force carrier separation, the concept defines two distinctive zones on the carrier wafer surface with strong adhesion in the perimeter (edge zone) and minimal adhesion in the center zone. For further description of the technology see IFTLE 90 "Highlights from the IEEE 3DIC 2012 Japan" and refs therein.
For all the latest on 3DIC and advanced packaging stay linked to IFTLE???????????????????????????????????..
