Part 4, the last in our updates of the RTI 3D-ASIP conference.
Altera
Arif Rahman, co-chair of the program, gave a presentation on the status of Altera 2.5D FPGA program with TSMC. They will combine FPGAs with a variety of technologies enabled by a high-speed chip-to-chip interface. Altera’s 20nm product portfolio will include die stacking capabilities. They see TSV process capability in place at foundry, IDM and leading OSATs.

Altera sees silicon interposer technology requirements:
– 1-4K chip-to-chip interconnects (2-4X in future)
– Micro-bumps: 30-50 micron pitch
– Interposer: 2-3 Cu damascene layers, optional backside RDL, up to reticle size, option for integrated passive components Rahman has looked at alternatives to the silicon 2.5D interposer technology:
High-density organic substrate ($$)
– advanced development
– 10X interconnect pitch vs. silicon interposer
– 10X interconnect pitch vs. silicon interposer
Glass interposers ($)
– In research phase No interposer ($-$$$)
– True 3D is expected to be more costly ($$$) and is currently not available&– Face-to-face stacking in wire-bond and flip-chip ($) is available
He concludes that Future stacking solutions will most likely consist of all of the above
IMEC
In the pre conference symposium Marinissen of IMEC gave an in depth look at the state of 3D stack testing .
3D stacking requires consideration of many more test points than conventional 2D testing. The extent of testing is a cost/benefit analysis which compares yield and the % of the bad product that the testing could have detected.
Most probers cannot handle thinned wafers on dicing frames. Marinissen reveals that TEL now offers automated handling and probing of 300 mm wafers on dicing frames.
Marinissen also showed the results of IMEC consortium partner TSMCs testing of logic + memory structures.
Global Foundries
Dave McCann of Global Foundries (GF) discussed 2.5/3D technical challenges and progress.
McCann compared the “open supply chain” (favored by GF) to the “Internal foundry model” favored by TSMC concluding that GF preferred to “utilize experience in the industry where it best exists”..
GF points out that memory architecture the choices in customer solutions agreeing with Amkor that 2.5D will not be a focus of smartphones.
They have gathered the following electrical data post thinning which shows little impact on electrical function.
Also of interest is their list of critical metrology and inspect steps:
Chinese Academy of Sciences
Prof. Daquan Yu of the Chinese Academy of Sciences-Institute of Microelectronics gave a presentation on “The Development of TSV Technology in China”.
Currently more than 12 companies and 10 Universities and Institutes are reportedly working on TSV related programs. A TSV consortium include foundries, packaging houses, material suppliers and institutes is examining interposer issues including:
– electrical, thermal, mechanical and reliability design guideline and simulation
– TSV interposer fabrication technology
– Assembly and reliability of TSV interposer with thin chip and substrate
– System testing methods
TSV manufacturing equipment such as TSV etcher, PVD for high AR seed dep and cleaning chambers have been developed by mainland Chinese companies and are ready or will be ready soon while some tools such as ECD are not ready yet and CMP, bond and debond are not yet available.
There are several local companies working on plating, cleaning, metal etching chemicals and CMP slurries . Xpeedic Technology was founded in 2010 to provide high performance EDA software and electronic design engineering services.
For all the latest on 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦.
