Last week, GlobalFoundries announced its first functional 20nm silicon wafers with integrated through-silicon vias (TSVs). At its Fab 8 facility in N.Y., the silicon foundry vendor manufactured TSV test wafers using their 20nm-LPM process technology, and at Fab 7 in Singapore, the company demonstrated a 65nm 32mm x 26mm interposer test vehicle for 2.5D chips. Both 2.5D and 3D are set for a 20nm introduction, full qualification by next year and non-early adopter production in 2015.

They are using a 6 x 60 um vias middle, copper TSV  as shown in the figure below. Interposer size is limited by reticle size i.e. 25-30 mm.

Intel Haswell GT3

This past fall [see IFTLE 123: Intel’s Bohr on3DIC] IFTLE reported rumors that Intel would be using TSV stacked DDR4 memory in their Haswell-EX platform for enterprise computing.

Haswell is the codename for the successor to Ivy Bridge architecture. Intel is expected to release 22nm CPUs based on Haswell around June 2013 according to leaked roadmaps. Current rumors have it that the Haswell GT3 will be the introduction point for 2.5D stacking and interposers. Semiaccurate [link] reports that Intel codename "Crystalwell" is not L4 cache on package but rather is GPU memory on an interposer. They indicate that the GT3 variants of Haswell will have 64MB of on-package memory connected through an ultra-wide bus.

Reports were that Haswell needed lower memory power consumption, higher memory bandwidth, and memory capacity that DDR3 could not provide but wide IO TSV based memory stacks could. Based on recent reports from the Semi 3D summit where ST Ericsson’s Kimmich concluded that "although 3D TSV technology appears ready for mass production, wide IO technology is not yet a fit for mainstream smartphones. LPDDR3 and LPDDR4 will be used in this application due to better thermal performance and lower cost."  [see IFTLE 134 “SEMI 3D European Summit – Isthe Wide IO Driver Dead ?”]