By Dr. Phil Garrou, Contributing Editor
Flip Chip Int (FCI)
FCI and Suss Microtec examined the use of lasers in the manufacturing of WLP.
Commercial dielectric via formation today used in WLCSP, RDL and flip-chip products typically rely on standard photolithography processing using stepper and 1x aligner equipment and processes. Interest in using laser via drilling (ablation) centers on the following reasons.
– Reduced via dimensions
– Simplified process flow
– Reduced process time
– Cost reduction
– Enable a broader range of dielectric materials (i.e., non photo dielectrics and mold compound)
– Eliminate organic solvents used in many pholithography process
With PBO via dimensions as small as 7.3um are demonstrated on PBO with an application desired sidewall angle around 60 degrees. Sidewall angles can be adjusted by changing the laser fluence and other settings.
– Higher fluence: Steeper wall-angle
– Lower fluence: Shallow wall-angle
Underlying metals (> ~1µm) can be used as a laser stop for via formation. By controlling the fluence and other settings the process has the ability to also stop at a certain depth in the dielectric without a metal backstop.
Since laser via ablation can produce smaller via dimensions compared to standard photolithography methods, using a laser via ablation technology can improve the design rules for next generation RDL layouts. In addition, the ability to utilize non-photosensitive organic dielectrics can enable better mechanical and thermal properties as the bump diameter and pitch shrink, improving end product reliability.
Global Foundries / Amkor / Open SIlicon
GF, Amkor and Open Silicon described their 2.5D ARM dual core product demonstrator which consists of 2 ARM die on a high density silicon interposer. A schematic of the module and he process flow are shown below . It was noted that “…extensive UF material development was needed” for the u-bump pitches that were used. A cumulative yield of 93.7% was achieved.
They used the following assembly flow:
Corning
Corning is beginning to show results of the multiple glass interposer programs they have instituted at sites such as RTI in RTP NC, GaTech and ITRI. One interesting proposal from Corning is that starting with 100um glass substrates should eliminate the need for backside grinding for via reveal . The 100um “Willow glass” with TSV is temp bonded to another glass layer and the TSV are filled . The interposer “panel” or wafer is then removed from the temp bonding substrate. It will be interesting to learn exactly how that is done (both the metallization and the release).
Work with RTI is showing the filled TGV can survive ( defined as less than 15% increase in initial resistance) greater than 700 thermal cycles of -55 to 125 ˚C and 20 x 20 arrays of TSV on 100um pitch are showing > 99.9% yield. The RTI team has also begun to show assembly of chip to glass using copper pillar bump technology.
Namics
Namics is developing their underfill products to meet the following roadmap for FC BGA and FC CSP.
Underfill materials can be classified as follows:
Their FEA modeling shows that Cu pillar and lead free bumps require a higher Tg underfill to protect from bump fracture during TCT, however low Tg may can assist with warpage, delamination and failure.
Modeling also showed that stress on low K of the IC is increased when using fillers that show filler separation (settling).
Underfill void elimination can be reduced by either using vacuum assisted CUF or curing in pressure oven.
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Phil, regarding the comment on thin Si strength and Young’s modulus:
“Koyonagi and co-workers have found that the Young`s modulus (E) of Si substrate begins to noticeably decrease below 50μm thickness. The Young`s modulus in 30μm thick Si is 30% of the modulus of 50μm thickness. In 30μm Si the lattice structure is highly distorted which induces the Young`s modulus reduction and consequently weakens the mechanical strength.”
No, I don’t believe that at all, and I would like to reject such ideas.
There is no reasonable explanation for lowering Young’s modulus just due to thickness reduction . Consider that Young’s modulus is physically related to the movement conditions of a Si atom inside its atomic potential- how to “flatten” the atomic potential to an extent like this?
I suspect the authors just made a simple mistake in calculations that might be due to their lack of experience in mechanics. Typical engineering formulas to extract stress and strain from measured displacements (e.g. from bending experiments), and thus to derive Youngs’s modulus, are based on underlying assumptions of geometric linearity. Due to the high flexibility of only 30 µm thin wafers and chips, these assumptions of geometric linearity are no longer valid due to the high displacements occurring in ultra- thin Si. We have seen that in our studies when dealing with chips with thickness < 100 µm. I suppose just considering "high displacement conditions" within FE modelling would lead to the "macroscopic" values again.
Best regards, Matthias