IBM/GF …the Saga Continues

Although both IBM and GF are refusing to address “rumors and speculation,” the rumors and speculation persist that the sale of IBMs semiconductor business to GlobalFoundries is imminent. The latest to comment on the expected deal is Businessweek / Bloomberg [link]

Most experts feel that GlobalFoundries is primarily interested in acquiring IBM’s engineers and intellectual property rather than the manufacturing facilities (200mm facility in Burlington VT and 300mm line in East Fishkill NY) since GF has its own state of the at capacity. GF would  act as a supplier for IBM’s semiconductor needs.

Reading the Vermont Free Press articles on the subject, it is clear that IBM employees expect GF to mothball the facility. For those of you wondering why there is a semiconductor facility in VT at all I offer you the following interesting comment “IBM opened its plant in Essex Junction in 1957, largely because the late Thomas Watson Jr., former IBM chairman and CEO, liked to ski.”

3D Integration Handbook

Mitsumasa Koyanagi, Peter Ramm and I have finished our work on Volume 3 of the 3D Integration Handbook and it is now available for sale at Wiley VCH, Amazon or you favorite textbook retailer.

Vol 3 focuses on 3D Process technology, updating the original two volumes in 2008 with all new chapters on all the relevant process steps. We have gathered many of the worlds experts to give you their insights on 2.5 / 3DIC processing and an especially strong chapter on metrology from the staff at Sematech. The bond/debond section includes chapters by Brewer, EVG, Suss, TOK , 3M and RTI. Most areas are covered by at least two different authors to give the reader a more complete perspective of what is possible. Of special interest should be the chapters “Bonding and Assembly at TSMC” by Doug Yu, “Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices” and “Implications of Stress/Strain and Metal Contamination on Thinned Die” by Kangwook Lee.

Paul Franzon of NC State, Eric Jan Marinissen and Muhannad Bakir will be editing Volume 4 which will focus on Design, Test and Thermal. We hope these volumes prove to be of value to the community.

2014 iTherm

iTherm is the Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems. The 2014 iTherm was held concurrent with the ECTC in Orlando, FL. This years General Chair was Mehdi Basheghi of Stanford and program chair was Madhusudan of Google. Attendance this year was up 50% to ~ 400.

HP

Kumari and co-workers at HP addressed “Air Cooling Limits of 3D Stacked Logic Processor and Memory Dies.” Their goal was to determine how many memory die can be integrated into a package with logic before exceeding the temp limitations of the memory die. Modeling was done for 10nm technology with 24 cores as shown below. Core power is varied from 1.5 to 3 W (red cores). Sacked memory are 0.5W DRAM.

Thermal results are shown below.

IMEC

Oprins and Beyne discussed the “Thermal Modeling of the Impact of 3D Interposer Materials and Thickness on Thermal Performance and Die-to-die Thermal Coupling.” For the test vehicle shown, they observe reducing the thermal conductivity from Si to glass results in an increase in the logic temperature and consequently a lower maximum logic power. The memory temperature at the other hand decreases for decreasing values of the conductivity since the in plane thermal coupling is reduced. This results in an increase of the allowable logic temperature. If the memory heating is included, an increase of the memory temperature can be observed for very low conductivity values.

Most applications for interposers combine high power components (logic) and temperature sensitive components (memory). Since the components are thermally coupled in the package, the logic power will be limited by either the temperature limit of the logic or memory, whichever is reached first. This means there is a trade-off between the logic self-heating and the thermal coupling which are impacted differently by the interposer material and thickness choice. It is shown that the Si interposer has a better thermal performance than the glass interposer in case only the logic temperature limit is taken into account and that the Si interposer package thermally outperforms the single chip package, the package-on-package configuration (PoP) and the 3D stacked configuration. In case the memory temperature limit and self-heating are taken into account as well, the glass interposer package has a better thermal performance for cases where the memory temperature limit memory is sufficiently lower than logic temperature limit.

For all the latest in 3DIC integration and other advanced packaging, stay linked to IFTLE…