By Dr. Phil Garrou, Contributing Editor

Rumors on the SCP Acquisition

We have discussed the Acquisition of STATSChipPAC (SCP) in recent blogs [see IFTLE 195,  “STATS in play….” and IFTLE 198, “….STATSChipPAC suitors named…”.] In late August, Bloomberg News reported that Jiangsu Changjiang Electronics (JCET) and Tianshui Huatian Technology were working on offers for SCP [link].

IFTLE continues to hear rumors from multiple credible sources that the deal with JCET is imminent and that final price is being negotiated. While denials are being floated by JCET, we all recall that similar denials were also rampant in the recent IBM / GF deal till the last minute.

IFTLE is also hearing that during these negotiations SCP, like IBM, is loosing key personnel throughout the organization. But, whereas IBM personnel movement was to ultimate acquirer GF, not so for SCP and JCET. Rumors from SCP indicate that JCET will not be retaining any key Singapore management in an effort to lower their cost position. As JCET waits to lower the ultimate acquisition price, IFTLE believes they are also lowering the overall value of SCP. A company is its people!  There are also unsubstantiated rumors of customers leaving SCP because of this chaos.

While it may be 2015 before the deal is consummated, IFTLE can see SCP falling from the #4 OSAT position and is probably already behind PTI.

Will SLIT replace TSV?

At the recent IMAPS meeting in San Diego Xilinx and SPIL presented the paper “Cost effective, high performance 28nm FPGA with new disruptive Silicon-less Interconnect Technology (SLIT).

In the traditional Xilinx silicon based FPGA module the FPGA die with microbup interconnect are connected to the 4 layers of 65nm interconenct on the silicon inerposer which then has TSV and c4 bumps to connect power/grd and other incoming sgnals.

In the new SLIT technology the same FPGA slices are mated to 65nm intrconenct on silicon but no TSV are required since ther is selective Si removal and backside contact formation along with required inline wafer warpage control. The structure is EXPECTED to give lower cost while delivering better electrical performance. The structures are compared below.

TSV “drilling and filling” are eliminated as are thin wafer handling, backside reveaand many inspect and metrology steps.

(a) traditional Xilinx FPGA with silicon Interposer; (b) FPGA without interposer

(C) SLIT in X-section

The 65nm interconnect are created on std bulk silicon The bottom most dielectric layer is selected to have high selectivity during subsequent backside etch. The top of the metallization interconnect layer is capped in 45um pitch pads and microbumps.

The FPGA die are  thinned diced and stacked onto the interconnect wafer. After reflow the ubump gap is underfilled and overmolded and the mold cmpd is ground down to expose the die top surface.

Subsequent wafer thinning is done to the dielectric etch stop layer.  Contact holes re etched in the dielectric and pads and balls are created/placed.

The main processing issue is wafer warpage, especially after the full silicon removal. Stresses are balanced with a reinforcement layer and other stress controls during the processing.

This is certainly a very interesting proposed structure and IFTLE will be keeping an eye on SLIT processing.

More from IMAPS in subsequent blogs

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