By Dr. Phil Garrou, Contributing Editor

GaTech Global Interposer Conference

The 4^th Annual Global Interposer Technology Workshop At GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon. Some of the panel discussions I have seen discussing the pros and cons of various interposer alternatives have been at this meeting due to the broad technical scope of its attendees.

Joining Rao Tummala as co-chairs were Matt Nowak of Qualcomm and Subu Iyer of IBM.

Yole

Representing Yole Developpement I presented an update on 2.5/3D focusing on thee new 3D memory architectures which have been needed for silicon interposers to really take off.

The audience was also forced to endure my lecture on packaging nomenclature which is getting completely out of hand.

Leadframes, BGA substrates and pieces of silicon with high density wiring and TSV are all interposers. The term 2.5D was a joke and the term 2.1D or others such as 5.5D similarly are jokes with no technical meaning. What the laminate community is beginning to call 2.1D is simply a higher density BGA substrate.

IBM

IBM’s Subu Iyer, an IBM Fellow, IEEE Fellow and front end practitioner for many decades has been a long time supporter of this Global Interposer Conference.

Always one to speak his mind Subu was blunt and to the point on two key issues during the panel session at this conference; (a) interposer definitions and (b) the presumed interposer cost structure.

He agreed that 2.1, 2.5D etc. has no real meaning and is only confusing non packaging practitioners. Here is the now infamous exchange with Rao Tummala [link]

Subu: “I find the whole concept of 2.5D fairly atrocious. I have banned its use [in IBM].”
Rao: “what are you going to call it?”
Subu: “Interposers, like God intended it to be.”

While nomenclature is important to keep concepts straight, even more important was the discussion on the relative costs of silicon vs glass vs laminate interposers. Subu’s point was:

“…high density interposers will all cost the same whether glass or laminate or silicon…the cost is not materials dependent but rather density dependent”

This is a point  that I have been trying to make myself for a few years now on IFTLE since the concept of the glass interposer became all the rage. As Subu said, interposer costs will all be approximately the same if the densities are equal and the equipment sets are the same.  In the chemical industry, from whence I came, the rule of thumb was that raw materials were responsible for approx. 10% of the total cost.

The key is NOT that glass is a low cost material, but rather whether one can manufacture fine features on large glass panels . Panel size and equipment set cost and throughput (yielded) will determine the cost of glass interposers not (I repeat) not the fact that window pane is cheaper than a silicon wafer.

Low cost equipment to create high density features on  large panel substrates (which obviously won’t be silicon)  IS a worthy goal for both glass and laminate providers,  lets just not loose track of what the key factors are. PANEL SIZE…EQUIPMENT SET COST…THROUGHPUT

In fact, a t the 2011 GaTech Global Interposer Conference Yole Developpement predicted that panel lines would be required for 2.5D interposers to attain a low enough cost to be widely adopted in the chip packaging community [link]

GaTech Glass Panel Consortium

At the IEEE Global Interposer Technology workshop in Nov Rao Tummala announced the formation of a “Panel based Global Glass industry Consortium” for “low cost, ultra miniaturization, high performance and Si like ultra high IO interconnections to address both small and ultra small system needs such as smartphones, wearables, IoTs and medical systems.”

Tummala continued “ we started looking at glass in 2010….today we have 50 global companies involved…GaTech can now access the complete ecosystem to develop and apply this technology to single chips, with lower cost than todays packages, multi chip in 2.5D architecture, similar in IO pitch to todays Si interposers but at much lower cost and ultimately to 3D system architectures”

GaTech continued that they “are producing advanced 2D, 2.5D and 3D system packages in its 300mm panel facility and looks forward to transferring the technology to 510mm panel fabs.”

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…