By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the key presentations at the 2014 IEEE 3DIC Conference recently in Cork, Ireland.

Global Integration Institute (GINTI) –    µ-XRD for Thermo-mechanical Stress Measurement

Copper-Through-Silicon-Via (Cu-TSV) is increasingly used for two reasons: (i) the very low resistivity of Cu as compared to that of the other TSV-fill materials that significantly reduces the (RC) delay, and (ii) the ease of Cu-electroplating to fill the TSV without any voids which enhances the production throughput.

Cu-TSV also suffers from some of the critical reliability issues such as diffusion of Cu in to active Si from back-metal contamination and the thermo-mechanical stress caused by Cu-TSV pumping.

Parasitic capacitance is approximately proportional to the size and length of the TSV. Therefore, in order to reduce the parasitic capacitance due to Cu-TSVs, one has to reduce the TSV size and length. To improve the yield of Cu-TSVs the aspect-ratio of the TSV has to be kept as small as possible. This forces one to reduce the thickness of Si thickness that leads to decrease in the mechanical strength of the 3D-LSI. The thermo-mechanical stress in 3D-LSI is widely measured using Raman spectroscopy.

In the future 3D-LSI will have TSV dia from few um down to sub um, one will no longer be able to use Raman to be used as a stress metrology tool. Micro X-ray diffraction (u-XRD) uses one order smaller diameter probe, as small as 200nm.

Ginti has studied stress values deduced from u-XRD data from LSI samples containing Cu-TSVs, whose diameter varies from 2 to 20um. It was observed that the TSV diameter has huge impact on the magnitude of resultant thermo-mechanical stress. The 20um-width Cu-TSV has induced more than -1500 MPa of stress in the vicinal Si, while the 2um-width Cu-TSV induced less than -10 MPa of compressive stress in the surrounding Si. Therefore by decreasing the TSV diameter, one can virtually eliminate the thermo-mechanical stress induced by TSV.

CEA Leti / ST Micro  – Thermal Performance of 3DICs 

Leti and ST Micro presented two papers on the thermal performance of 3DICs.

3DICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology.

There are four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs.

Heat dissipation in small hotspots is primarily diffused through the high thermal conductive silicon substrate and spreads in a semi-spherical direction, rapidly decreasing the heat density and lowering the peak temperature. In case of thinned silicon dies in a 3D stack, the inter-die interface layer acts as a thermal barrier due to its poor thermal properties, forcing the heat to spread laterally in the silicon substrate and thus resulting in a temperature distribution which approximates a cylindrical shape.

Thinned silicon dies present reduced lateral heat spreading capacity while poorly conductive adhesive materials used to bond dies together contribute to increase the vertical thermal resistance.

An increase in power density may come from higher power dissipation and/or from a reduction of the chip footprint. It means either more power needs to be removed from the same package or that the same power dissipation has to go through a reduced chip footprint. While chip footprint reduction is one of the advantages of 3D integration, it usually leads to higher temperatures for the same amount of energy dissipation when compared to single-die implementations.

Leti shows that inserting TSVs as thermal vias is of limited value. They contend that it is more important to reduce the thermal resistance between the stacked silicon dies which is due to  poor thermally conductive layers such as  BEOL metallization and underfill.

Thinned dies can present a severe thermal impediment especially to chips with hot spots. Thinned dies present high lateral thermal resistances thus forcing the heat to go through the underfill layer to the next die, which acts as a heat spreader reducing the hotspot temperature. Consequently, the thinner the die the more important is the thermal coupling between dies in case of hotspot heat dissipation.

The use of “thermal TSVs” for thermal mitigation has been routinely reported in the literature. Several thermal-aware physical optimization techniques can be found in the literature which rely on simplistic thermal models where the TSV is treated as a vertical lumped thermal resistor with thermal conductivity calculated according to its diameter and length. Such thermal models ignore the lateral heat transfer and the impact of the thin Si02 layer, which surrounds each TSV and thermally isolates TSVs from silicon substrate. The poor thermal conductivity properties of the SiO2, dominate the thermal impact of the TSVs in case of hotspot dissipation. Thus while having TSVs in the silicon substrate increases the equivalent vertical thermal conductivity at the same time it causes a lateral thermal blockage effect, especially for fine TSV pitches.

The thermal test chip is composed of two stacked dies connected through TSVs in the bottom die and μ-pillars (μ- bumps) in a face-to-back stacking configuration. Large FC Cu-pillars (bumps) are used to connect the bottom die to a BGA substrate. Gaps between layers are filled with underfill material for mechanical strength purposes.

The SiO2 layer around each TSV leads to an increase of the hotspot temperature compared to the case without TSVs (+1.9 °C). Contrary to the common expectations, TSVs have a negative thermal impact on the hotspot temperature.

Increasing the TSV density increases the vertical thermal conductivity as well as the lateral thermal blockage effect. Splitting large TSVs into smaller ones, as suggested in [4] for instance, increases the ratio of the SiO2 layer thickness to the TSV diameter and hence increases also the lateral thermal blockage effect. Considering TSV technologies with very fine pitch, where this ratio is typically 1:10, also lead to TSV arrays with higher lateral thermal blockage effect.

An explorative study including multiple TSV array configurations and power dissipation profiles shows that, contrary to the common belief, TSVs are not effective for thermal mitigation in current TSV technologies and may even provoke exacerbated hotspots. Although TSVs help to convey heat vertically, the lateral thermal blockage effect prevails over any thermal benefit arising from TSVs in the case of hotspots. In the reported investigation, TSVs placed around a small hotspot may result in peak temperatures worsened by up to 15%.

Parylene HT for 3DIC – An Alternative Opinion

Researchers at AIST reported at Cork on Parylene HT’s use as an insulator layer for copper TSV. While it certainly is true that “the capacitance of parylene liner is much lower than that of SiO2 liner. This provides benefit in minimizing the signal delay, lowering power consumption, and reducing cross-talk between neighboring paths.” No consideration was given to the mechanical properties of Parylene HT.

Parylene HT aka Parylene AF4, aka Parylene F has been reported in the literature for more than 35 years.  It was available commercially in the late 1990’s as Novellus AF4 when it  was thoroughly screened as a potential ILD Low=K replacement material. It was never implemented as a Low-K ILD for many reasons amongst which was the reactivity of the F with the Ta barrier layers in dual damascene structures.

Parylene (though not the HT product) has been examined as an insulator for 3D TSV  by the RTI group working on the DARPA VISA program since 2006 and by IMEC since 2008. The use of Parylene as a TSV insulation dielectric has been detailed in Chapter 7 of Volume 1 of the “Handbook of 3D Integration.”

[Garrou, Bower And Ramm Eds, Wiley VCH 2008]

While the Parylene family of products has found a nice niche as a protective coating for PC boards and medical components, it is NOT known for its superior mechanical properties.  While Parylene HT reportedly has superior thermal properties (vs other Parylenes) it’s mechanical properties remain poor as shown below.

So the tensile strength of Parylene HT, is ~ 50 MPa and the elongation is 2%. The yield strength, i.e. the stress at which it begins to deform plastically is 35 MPa. These are not properties that I would want encapsulating a copper TSV which is known to undergo “copper pumping” and is known to exert so much stress that it cracks SiO2 liners as it expands.

Suffice it to say that I would examine mechanical reliability tests very carefully before implementing such materials into a 3DIC process flow.

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