By Dr. Phil Garrou, Contributing Editor

Let’s continue our end of year look at presentations at the RTI ASIP Conference.

Yole Developpement

During my 2014 market Update presentation 2.5 / 3DIC for Yole Developpment, we looked at the timeline for introduction of the various new memory architectures as shown below:

Another popular slide discussed cost vs density for current available and proposed interposer solutions. While silicon clearly achieves the highest density it is at the highest cost. Laminate originates from a position of low cost, but to achieve higher density (both L/S and via dia/pad size) will processing and equipment costs be able to maintain low costs? Is large area processing or panel processing a credible concept for high density packaging? Glass while intriguing has no standardization of ground rules and no announced fabrication facilities that can supply large volume orders.

While it is clear that 1-10um L/S is a density sweet spot, it is not clear what technology will end up delivering a reliable technology at the lowest cost.

Fraunhoffer IIS / Siemens

Schneider of Fraunhoffer ISS and Siemens reported on heterogeneous integration for Sensor Systems.

One key point is that there currently is no accepted definition for heterogenous integration and it includes:

– different devise with different functions

– dies manufactured from different substrate materials

– dies manufactured with different technologies.

For example:

Unimicron

 We last discussed Unimicron’s thoughts on producing high density laminate with 2/2 (L/S) in IFTLE 223. At the RTI 3DASIP DC Hu detailed further thoughts on technologies to achieve silicon like densities on laminate substrates.

Target Line Width

• Copper trace, 2013:10/10um, 2014; 8/8, 2015: 5/5, 2016: 3/3or 2/2
• Target via size, 2013: 60um, 2014: 50um, 2015: 40um, , 2016: 30um

8/8 Lines and maybe even 5/5 can be achieved by todays lamination technology

But below 5/5um, new methods are under consideration

–  Semi additive

–  line first by embedding

– line last by embedding

–  Copper Damascening

Photo Process

– Exposure tool, Stepper, LDI, but need large panel processing

– Liquid photo resist may be required.

–  Slit coating, Spin coating of PR

Planarizaton

– Large Area CMP may be needed.

Fine Lines on Large Panel Glass Substrate

– 3/3um L/S with thickness of 5um Cu patterns can be realized on 508x508mm glass panel.

Line Embedded Line Last Technology

Line Embedded Line First Technology

New Structure – embedded high density film

– High Density Film with three metal layers can be as thin as 40 um.

–  Super thin package.

–  Low Cost

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…