By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 ECTC:

Kaiung Paik – KAIST and Jay Im – U Texas

Nancy Stoffel – GE, Chris Bower & Carl Heinz Bock –
Emerging Tech Committee Chairs & Marsha Tickman –
Exec Dir CPMT

Stress & Bowing in Passive Silicon Interposers – IMEC

Three modifications of the structure of a 4 BEOL layers with 10×100μm TSV Si interposer are proposed to mitigate the tensile stress and release the interposer warpage. The use of a thicker and more compressive PMD layer enable a wafer bowing reduction of 75% after TSV processing. By reducing the thickness of Metal1 (ground plane with 75% Cu density) from 1000 nm to 300 nm, the single contribution of the Metal1 module to wafer bowing was reduced by 37%. Finally, by using a more compressive oxide (from -170 MPa to -230 MPa) to process the Via2/Metal3/Via3/Metal4 layers (total of 8μm thickness), their contribution can change from tensile to compressive, inducing a total reduction of -120%. In total, a global bowing reduction after full front side processing of 75% was measured compared to the initial interposer structure.

Effects of Packaging on Mechanical Stresses in 3DIC – IMEC

IMEC has studied the mechanical stress induced in 3D stacks by different packaging process steps. The 3D stacks used in this work are assembled using two identical dies containing a number of stress sensors which are designed and manufactured in 65nm technology. It is observed that the contribution of the package substrate and the die-attach process to the redistribution of mechanical stress inside the 3D stacked IC is more significant than the one of the EMC and that the influence of packaging on the shape and amplitude of local stress around the micro-bumps is not significant. These observations are supported by the measurements of stress done using micro-Raman spectroscopy and are correlated with the results of finite element modeling and with optical warpage measurements of different packaging configurations.

Advanced Metallization Scheme for 3 x 50 um TSV Middle Process – IMEC

Scaling down the TSV diameter from 5μm to 3μm is very attractive for the 3D IC implementation in more advanced CMOS nodes. For instance, stress caused by the mismatch between the coefficient of thermal extension (CTE) of Si and Cu may generate strain in the Si around the TSV, degrading the device performance of transistors located close to a TSV. To reduce the impact on transistors, a so called keep-out-zone (KOZ), is generally defined around the 3D TSVs. This keepout-zone is however significantly smaller when scaling down the TSV diameter from 5μm to 3μm. When increasing the aspect ratio of the TSV from 10:1 to 17:1 (for 3μm diameter and 50μm depth), the conventional PVD barrier and seed options reach their conformality limits. Very thick barrier/seed layers need to be deposited in order to assure a continuous film at the bottom of the TSV. This not only fundamentally limits the extendibility of this integration scheme, but also increases the PVD deposition cost itself and the required CMP time, among other technical challenges. For these reasons, a new advanced and scalable TSV metallization scheme was developed.

Atomic layer deposition (ALD) has emerged as a key enabling technology for conformal film applications such as TSV oxide liner. Typical step coverage or conformality of other CVD oxide films is only 60-75% for high aspect ratio TSVs . In contrast, the VECTOR ALD oxide film shows 100% conformality.

ALD WN serves as a barrier layer and is deposited on the Altus Max tool. It is highly conformal with >90% step coverage regardless of geometry. ALD WN is deposited at 375°C and has excellent adhesion to ALD oxide and subsequent ELD NiB. The conformality of the ALD process results in a pinhole-free WN layer, as opposed to barriers deposited by PVD, which potentially struggle with pinholes at the bottom of high aspect ratio TSV.

NiB electroless deposition on WN barrier was carried out on a Lam ELD2300 tool using a plating chemistry developed at Lam. The entire deposition process was made of several sequential steps such as a brief pre-clean, activation, deposition, rinse and dry. The concentration of reducing agent and nickel ions as well as the pH and temperature are controlled to maintain optimum deposition condition for seed formation during the NiB deposition. After deposition of ELD NiB, TSV copper electrofill is processed on a Lam SABRE 3D electroplating system using an industry standard acid copper sulfate electrolyte with a Lam

exclusive organic additive package. The conductivity and corrosion resistance of the Lam ELD NiB film enable compatibility with the electrofill process on 300mm wafer scale. Bottom-up fill of the vias proceeds without the need for the additional copper seed film that has been used with other conformal metal liners (e.g. Co or Ru).

Because of the high conformality of liner, barrier and seed layers, this proposed Via-middle metallization scheme is believed to be scalable to even higher aspect ratio TSVs with 2μm diameter.

Silicon on Diamond by Low Temp Bonding – Kyushu Institute of Technology

Diamond has long been known as an excellent thermal material, but has been a hard material to process. Researchers at Kyushu Univ had recently developed a low temp diamond bonding technique. The process flow is shown in the figure below. The SOD fabrication process includes: (a) Fabrication of thermally grown SiO2 film on Si wafer as a bonding substrate. (b) Deposition nanocrystal diamond film on Si wafer as another bonding substrate. (c) Removal of big nanocrystal diamond particles. (d) Deposition of SiO2 film on the nanocrystal diamond film by CVD. (e) CMP of the SiO2 film. (f) Thinning of the CMP SiO2 film by 2.5% HF solution. (g) Surface chemical cleaning of the bonding substrates by piranha solution. (h) Surface activation by O2 plasma. (i) Bonding of the substrates.

The middle figure shows (a) the morphology of 300nm-thick of nanocrystal diamond on the wafer 525nm-thick wafer. The surface roughness of nanocrystal diamond was characterized by AFM which was 13.9nm rms approximately. Generally, the roughness of thin film from the CVD process is dependent on the substrate. Thus a surface roughness of SiO2 that we plan to deposit in the next step is probably close to 13.9nm rms.

In addition, the big nanocrystal diamond particle may be an obstruction to the thinning SiO2 before bonding. Therefore, we remove the big particles using CMP equipment before deposition of SiO2 film on it. Fig. (b) shows the morphology of CVD-SiO2 500nm thick deposited on substrate after remove big particle already. The roughness was reduced to 8.1nm rms compared with the substrate. Fig (c) shows the morphology of CVD-SiO2 after polishing by CMP. The roughness was reduced to 0.50nm rms.

An average CVD-SiO2 roughness of > 1 nm rms failed to bond, the bonding results show 95% confidence level for bonding with a roughness is 0.97±0.03nm rms.

The figure on the right shows the cross section of the stack shows the dimensions of the overall structure.

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