By Dr. Phil Garrou, Contributing Editor
This week lets finish our look at the substrate and panel level processing activities at Semicon Taiwan 2015’s Embedded and Wafer Level Package Technology Forum.
UniMicron
DC Hu reviewed Innovative Substrate Technologies including glass as a candidate material for high density substrates and interposers.
When it comes to the impact of panel level processing on the cost of high density substrates most would agree that while large glass and PCB panels are available at a reasonable cost, it is not yet clear that current equipment can produce the required densities and thus meet the low cost expectations. Never the less, it is certainly worth the effort to develop the data and sort this issue out.
For glass, one of the main questions has been can you make electrically and mechanically functional vias and fill them with conductive metals. Hu compares the current via forming capability of Va Mechanic, LPKF and Corning as is shown below. It appears that the most advanced systems are currently developing < 100um glass thickness, ~25um holes at a throughput of > 2000 holes/sec.
Laser & Electronics AG (LPKF) is a German equipment manufacturer that focuses mainly on PCB prototyping and micromachining solutions for SMT stencils. Via Mechanics, previously known as Hitachi via mechanics Ltd has been engaged in manufacturing, printed wiring board (PWB) manufacturing systems.
Unimoicron is also developing a laminate using glass as core as shown below. Glass has a 3X better flatness (R < 0.5mm) than an organic core given he same core CTE (i.e. 3 ppm/°C). Such technology is currently being demonstrated at 508 x 508mm; 100-200um glass thickness; with 8/8um L/S on ABF dielectric.
They have demonstrated sub 2/2 L/S on test vehicles.
Fraunhoffer IZM
Tanja Braun and co-workers at IZM/TUB detailed their studies on fan out panel level processing. They listed the following as the most obvious challenges:
The equipment they have put in place for ~600 x 450 panel level processing line is shown below.
J Devices Panel Level Processing (PLP)
Reasons for wanting to develop pane level processing are obvious. A 500 x 400mm panel has 3X the area of a 300mm wafer.
The standard PLP process flow is shown below:
J Devices is equipping a PCB facility to manufacture the PLP technology.
J Devices makes the point that required RDL technology depends on the application. For example Application processors require wafer photolithography while modules for RF/PMIC only require PCB photolithography.
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