By Dr. Phil Garrou, Contributing Editor
Continuing our look at the 2015 IMAPS Conference.
Unimicron
Unimicron discussed their continued development of < 5/5 L/S for polymeric interposer applications.
While silicon can meet fine line (< 5/5 L/S) requirements easily by wafer level processing, silicon processing cost is a barrier to many applications.
There are two types of processes available to meet fine line requirements on organic substrates, traditional semi-additive processing (SAP) or laser embedded technology. They are shown in xsect below. Unimicron reports that current status for SAP is 8/8.
UV YAG lasers allow for maskless ablation processes by ablating trenches and blind vias simultaneously, but the throughput becomes slow as the features get larger. Throughput of eximer lasers is independent of pattern features since they are defined by the mask. The aspect ratio (h/w) for eximer laser was 1.2 for 3/3 in build-up film with fine filler particles and for 5/5. In general, the finer the filler particle size, the deeper the trench. Since they found that eximer laser ablation was much slower than lithography, the next developments will be with photo build up dielectric to replace the laser ablation. IFTLE should note that this is how it was done during the MCM era in the mid 1990’s, like the IBM SLC technology.
Princo – System on film
In yet another chips last packaging solution, Princo described their system on film technology. Following the figure below they 200mm glass wafer that is first surface treated with a PI and then a silane release coating then another PI layer. Steps 4 to 7 are a lift of copper metallization sequence (6/4um L/S ; 11um thick). Next comes a dielectric layer ad then laser formed vias. These steps are repeated for further layers (up to 8 so far). In step 14, the structure is released from the carrier. This RDL film wafer is then flipped over and the pads are opened through the PI layer and ENIG coated. Die are flip chip mounted, underfilled, overmolded and balls attached and balls placed.
They describe two modules. Module #1 consists of a µprocessor, LPDDR SDRAM / NAND flash combo memory and power management IC on a 6 layer 20 x 17mm module. The second module consists of a µprocessor and a bluetooth 4 dual mode chip packaged in a 4 layer 9.5 x 7.3mm thin film package.
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