By Dr. Phil Garrou, Contributing Editor
Post Thanksgiving IFTLE mean an update on Maddie (L) and Hannah (R). The family spent Thanksgiving in NYC where I grew up. The rock behind them is from the meteor exhibit at the Museum of Natural history. Speaking of rocks, can anyone identify the rock on the right?
JCET [STATSChipPAC]
Lin of JCET discussed CPI (chip package interaction) for 28nm die in eWLB fan out packages. JCET proposes FOWLP as the 3rd wave of packaging:
They proposed the following current and future eWLB solutions:
They have evaluated electrical CPI and CBI (chip board interaction) for their FOWLP technologies with the following test package and found no problems.
Qualcomm
Ray of Qualcomm examined CPI (chip package interactions) in FOWLP.
IMAPS 3D-ASIP in Burlingame CA DEC 13-15
Hope to see many of you at the annual 3D ASIP conference run this year by IMAPS and held at the Burlingame Marriott. Special attention was paid to bring new viewpoints on high density packaging technology. Some of the Highlight presentations include:
“Image Sensor Technology Evolution for Sensing Era” – Tetsuo Nomoto, Sony Semiconductor Solutions
“Future Landscapes for 3D Integration: From Interposers to 3D High Density” – Jean Michailos, STMicroelectronics
“3D Stacked Image Sensors from a Chinese Perspective” – Roc Blumenthal, SMIC
“Heterogeneous SoCs” – Professor Subramanian Iyer, UCLA
“3D Heterogeneous Integration of CMOS, InP, and GaN Devices Using Hybrid Wafer Bonding” – Andrew Carter, Teledyne
“Essentials of Thermo-Compression Bonding” – Hugo Pristauz, BESI
“ Extreme Wafer Thinning to 5 µm for Low Cost Via Last” – Dave Thomas, SPTS
“Chiplet Partitioning for 3D Many Core Architectures” – Denis Dutoit, CEA-Leti
For full program details and registration see: http://3dasip.org/
For all the latest on advanced packaging, stay linked to IFTLE…
