By Dr. Phil Garrou, Contributing Editor
Consolidation in CIS Market
Remembering our IFTLE rule [ see IFTLE 241, “Simply Obeying the Laws of Economics”] that maturing markets have 3 players with > 85% of market share, we note that Gartner Assoc. has reported that the top 5 vendors accounted for 88.9% of global CIS revenue in 2016 and the top 3 companies have 78.9% of the market, up from 77.1% in 2015 so we are getting close… [link]
Teledyne / DALSA
Invensas (Experi) has announced technology transfer of its Direct Bond Interconnect (DBI) to Teledyne DALSA. This capability enables Teledyne DALSA to deliver next-generation image sensors to customers in the automotive, IoT and consumer electronics markets. Invensas and Teledyne DALSA announced the signing of a development license in February 2017. All of the major image sensor players appear to be adopting this image sensor stacking technology.
Chip Stacking for Image Sensors
Ray Fontaine at TechInsights has this to say about image sensor technology in 2017 “Chip stacking (image sensor + image signal processor) for image sensors remains an enabling technology for improved camera performance, and this year we documented Sony’s first-generation TSV-based three die stack (now adding a DRAM) in mass production. For two-die stacks, we still primarily see TSV-based chip-to-chip interconnect, although Sony has been using direct bond interconnects (Cu-Cu hybrid bonding, or DBI) since early 2016. We recently saw OmniVision and foundry partner TSMC join the hybrid bonding club and claim the new world record, based on TechInsights’ findings, of 1.8 µm diameter, 3.7 µm pitch DBI pads.” [link]
IMAPS 3D ASIP
The 14th annual 3D ASIP conference, in early December, deviated somewhat from its traditional focus on 3DIC content to cover ancillary and complimentary technologies. Below we see incoming IMAPS President Ron Huemoeller presenting plaques to Gen Chair Garrou and Tech Chairs Scannell and Koyanagi.
DARPA CHIPS
DARPA has a long history if chip integration as is depicted in the slide below showing DARPA programs and their acronyms.
IFTLE has had extensive discussions on the 2017 DARPA CHIPS program. [see IFTLE 323 “The New DARPA Program “CHIPS”…”].
In his plenary presentation, DARPA program Mgr. Dan Green pointed out that the CHIPS goal is to develop design tools, integration standards, and IP blocks required to demonstrate modular electronic systems that can leverage the best of DoD and commercial designs and technology. Particular emphasis is being placed on trying to develop a technology infrastructure that can be adopted by both the aerospace infrastructure and the commercial infrastructure.
The CHIPS grants are led, as shown below, by Boeing, Intel, Lockheed Martin, Northrup Grumman and the Univ of Michigan.
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