By Dr. Phil Garrou, Contributing Editor
This week, let’s take a look at the latest Yole update on Fan out Packaging by Jerome Azemar that was presented at the IMAPS 2018 Device Packaging Conference.
As we have discussed before, fan out packaging can be embedded in laminate or embedded in mold cmpd (EMC) . Chips can be placed face up or down with various options for interconnections.
Their look inside a smartphone gives an interesting perspective on where fan out packages are being used and where they can be used.
Yole sees automotive radars as an interesting market for fan out solutions
– fan out used in Rf and radar applications
– since 2015 Infineon has shipped > 10MM Radar IC in eWLB packages
Yole reports that technical challenges still exist for fan out as shown below:
They see high density fan out (like TSMCs InFO) fan out being in competition in the future for HPC (high performance computing) and AI (artificial intelligence) applications with silicon 2.5D solutions.
While panel production would certainly reduce costs (more units per operation) such technology is not ready and will have large capital equipment costs. They see production being mainly on wafer through 2022.
CMOS Image Sensor Market
IC Insights Optoelectronic, Sensor, and Discrete report concludes that the CMOS Image sensor market is not approx. the same size and growth rate as the LED business [link]. An interesting comparison…
For all the latest in Advanced Packaging, stay linked to IFTLE…
More of marketing type effusions from Lyon, France ( well known for the Cuisine for sure, but for Adv, Packaging ? ). They seem to be now including ( fig 1 ) even Flip Chip on a Coreless Substrate under FO WLP !! Is that because they have finally understood that their claims of eWLB being electrically superior to Flip Chip is based on an incomplete comparison ? The absence of Core Vias in Coreless substrates make the high freq. electrical performance of Flip Chip on Coreless substrates almost as good as eWLB, and in spite of bumping / assy costs slightly cheaper because of panel processing of the RDL. Note that 2+ years after intro of FO WLPs for AP by Apple there are still no other takers for FO WLPs in the AP / SoC world, as connection to coarse pitch MBs dictate larger packages ( 15 mm and above ). Apple gets its AP put inside a FO WLP by their Foundry itself so the cost penalty of doing the RDL on a 300 mm reconstituted wafer rather than on a 4x larger 500 mm panel / yield losses due to die shift etc. in face down RDL can be buried under die cost.