Insights From Leading Edge

IFTLE 5 2010 Date in Dresden

Design Automation and Test Europe (DATE) was recently held in Dresden. You may recall, last year DATE held a major track on 3-D integration [ see PFTLE 75, “Nice DATE”, 05/09/2009] . Chairs Marinissen, Guillou and Van der Plas repeated the track this year with similar excellent results.


We have recently covered 3D activities at ITRI. [see PFTLE 99, "3D IC at ITRI”,
09/24/ 2009 and PFTLE 105, “Taiwanese Focus on 3D “, 11/06/2009 ]

At the 2010 DATE Cheng-Wen Wu from ITRI gave a plenary presentation on “What We Have Learned from SOC Is What Is Driving 3D Integration” Wu reiterated what we have seen previously [ see PFTLE 121 “IC Consolidation, Node Scaling and 3D IC”, 03/03/2010 ] in terms of cost becoming a major obstacle in order to moving forward with future nodes.

When looking at the techniques being developed to ensure 3-D yield, the following slide is a great pictorial to how 2/4 redundancy gives much better odds of yielding a 3D stacked structure than simple TSV doubling.

At Semicon 2009 Ric Borges of Synopsys reported that Synopsys was ramping to provide tools in time for market adoption of 3D IC integration. [ see PFTLE 90 “MCA Delivers 3D Brightspot at Semicon”, 7/31/2009.

At DATE Min Ni of Synopsys examined the role of thermal TSVs in a 3DIC chip stack. When comparing thermal TSV vs fluidic channels they conclude:

Thermal vias & thermal TSVs
– Pros
• can utilize existing vias and TSVs
• no additional processing steps needed
– Cons
• non-scalable due to vertical heat path.
• area penalty for extra thermal TSVs
Fluidic channels
– pros
• scalable with chip area and number of tiers
– cons
• design complexity
• reliability
• needed vertical resources

They ask the question of whether extra TSV are really needed for thermal reasons and if so when should they be added since the thermal hot spots are really not known until the routing is complete.

When looking at Impact of signal/power TSV array on temperature of 3D IC
they conclude that the maximum temperature decreases as TSVs are inserted, however, the effects saturate quickly. The proximity of thermal TSV arrays to hot spots is more critical than array size. For close proximity arrays size matters but benefits from increased array size saturates quickly. It is best to place thermal TSVs in array format to minimize area penalty, close to hotspot to maximize heat conduction. It is the boundary heat transfer coefficient that dictates the steady state temperature of chips, not the amount of TSVs.

Cascade Microtech
Thomas Thärigen of Cascade Microtech examined “3D IC Test Challenges
and Probing Concepts”. He concludes that 3D IC related DFT (design for test)
Is the key success factor for testing of 3D stacked devices, since contacting 3D circuits has several limitations (see case study later) Without considering test during design phase it will be impossible to perform effective tests on 3D stacked IC’s.

For the bottom wafer:

Probe on Regular Front-side Pads
– Function can be tested
– TSVs can not directly tested
– State of the art contact technology with regular cantilevers:
high alignment speed and high contact stability
– Available for Known Good Die/Stack Test and for Engineering Test
– Can be combined with non contact techniques
– State of the Art design techniques required for testability
– Only for the first tier

Wafer on carrier: thinned and backside completed

Probe on Extra DFT Pads
– State of the art contact technology with regular cantilevers:
high alignment speed and high contact stability
– Available for Known Good Die/Stack Test and for Engineering Test
– Limited number of regular-sized pads must be added by DFT
– Execute RPCT inside die which must be designed in by EDA
– Can be combined with non contact techniques
– Medium probe force vs. adhesive stiffness is currently under investigation

Probe on Micro Bumps
– Challenge: TSV micro-bumps small (e.g. 25μm) & numerous
– Available for KGD/KGD and Engineering Test using vertical probe cards
– Access to high pin counts = high bandwidth for tests
– Normally this TSV contacts are inter-die connects
– DFT is required to have all contacts available to execute test routines for
the single die
– Can be combined with non contact techniques
– High pin count = high probe force: Probe force vs. adhesive
stiffness is currently under investigation

Probe on TSV’s
– Challenge: TSV’s very small (e.g. 5μm) and numerous
– Only for engineering purpose, no further wafer processing possible
afterwards (bonding does not work due to probe marks)
– Use of small single tips required = only very limited number of
contacts simultaneously
– Design required to implement dedicated engineering test structures

Non contact probing is limited to pitch due to antenna issues.

The complete set of presentations can be found here:

coming soon at IFTLE:

– Copper-Copper and IMC Bonding
– Stacking Chips in Vegas
– 3D IC at the IITC
– taking a look at the new ITRS roadmaps
SEMICON – I’ll be at Semicon next week gathering new information for you
Tues June 13th AM I’ll be on the panel at TechXSPOT "Bridging the Gap"
Tues June 13th PM I’ll be at the Suss workshop "3D Bonding and Thin Wafer Handling"
Wed June 14th PM I’ll be at the Alchimer workshop "TSV Metallization that Cost 80% Less"
Hope to see a lot of you at the Sematech reception on Wed night.

For all the latest on 3-D IC and advanced packaging stay linked to Insights From the Leading Edge, IFTLEâ??¦â??¦..


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