CMP, CMC and MOSIS have announced a multiproject wafer run for Jan 2011. MOSIS has been known for years as a supplier of prototype IC runs through its global network of foundry partners. CMP is a broker for IC and MEMS low volume production. CMC  is a non profit that supports microelectronics and Microsystems R&D in Canada.

The first two tier face-to-face bonded 3D IC run is based on Tezzarons SuperContact technology and GLOBALFOUNDRIES 130 nm CMOS. We had documented Tezzarons activities in 3D IC previously [ see PFTLE 115 "Semi Award Announced for 3-D IC Actvities", 01/26/2010 ]

When asked about customers potentially being hesitant to work at the 130 nm node Bob Patti, CTO of Tezzaron, replied “They all need to do something different past 28 nm to differentiate themselves. Will anyone really start learning 3D at the 28 node node which will cost hundreds of millions of dollars for design or does it make more sense to start at lower cost node ?? We think likely the latter..”

Patti indicates that the multiproject run opens the door to a lot more companies and Universities to do early development capitalizing on the design kits that have already developed. “There is enough interest already to fill 2-3 reticals with parts “ According to Patti “Tezzaron is a arranging for the Si through Global foundries and will do the assembly, the backside metals and Cu  bonding “.

Elpida Announces 3D Alliance

By now you have seen the major announcement that Elpida (Japan), UMC (Taiwan) and Powertech Technologies (Taiwan) have formed an “alliance” to speed up the development of 3D chips at the 28 nm node (link).

This makes so much sense in so many ways. Elpida has had several recent announcements indicating a strong desire to be an early player in 3D [ see PFTLE 101 “Optimism vs Reality; Semantics or Lost in Translation”, 10/11/2009; PFTLE 97 “Ginkgo Biloba”, 9/12/2009; “Elpida Preparing for 3D Commercialization” Semiconductor International, 3/30/2010]. UMC, meanwhile has been very silent about their 3D activity except for joining the ITRI Advanced Stacked- System Technology and Application Consortium (Ad-STAC) [ see PFTLE 99 “3D IC at ITRI”, 9/24/2009 ]. UMC certainly needed to get more press for their activities in order to counter the attention being paid to rival TSMC [ see PFTLE 117 “On Copper Diffusion, Gettering and the Denuded Zone” 02/06/2010; PFTLE 110 “3-D ASIP Update: TSMC & the OSATs”, 12/23/2009 ].

Takao Adachi, CTO in charge of new technology development, has stated that ELpida wants to use it’s 3D technology to “expand beyond its DRAM business and supply systems solutions developed by stacking memory with Rf sensor and logic devices that would come from partner companies” [ see “Elpida Preparing for 3D Commercialization” Semiconductor International, 3/30/2010]. This announcement brings those goals closer to reality. Memory on Logic will enable a large number of I/O between logic and DRAM which increases the data transfer rate and reduces power consumption. Such products will be based on UMC’s foundry logic, Elpida’s DRAM and Powertechs assembly technology.

DIGITIMES reports that PTI has been discussing TSV technology with Elpida for several years and it is speculated that this alliance could lead to a partnership arrangement in the future [ link].

UMC’s CTO reports they expect to be sampling 3D IC solutions using their 28 nm process technology “in mid 2011, with production slated for 2012”

To meet this tight time line IFTLE boldly predicts that 3D interposers it will be used to mate the UMC logic to the Elpida memory. Recall Elpida has extensive background on interposers from their previous work with NEC. [ see PFTLE 28 “NXP Proposes Passive Integration in 3D IC Stacks”, 04/13/2008 ] We will see what really happens shortly. You can be sure you will see updates in IFTLE.

IEEE International 3D Test Workshop

PFTLE has previously listed 3D Test as one of the “4 Horseman” [ see PFTLE 102 The Four Horseman of 3-D IC Integration, 10/14/2009]. The need for standardized 3DIC test protocols have also been documented [ see: PFTLE 108, Testing 3D IC, 12/07/2009 ]

It is therefore with pleasure that IFTLE brings to your attention the 1st IEEE workshop on testing 3D Integrated Circuits “3D – Test” It will be held in conjunction with ITC (Int Test Conf) Nov.2010 in Austin. Check out this site for further details [link]  
Leti 300 mm line

Leti has announced that it has opened a complete 300 mm fab extension dedicated to 3D applications. Equipment instillation will continue through the end of the year and an inaugural event is planned for Jan 2011. The line includes lithography, metallization, etching, dielectric dep, wet etch and packaging which will be available for Leti customers and partners.

IBM- the Rumors

In IFTLE 2 “Adv Pkging at 2010 Las Vegas ECTC”, June 2010, I reported the speculation that a TSV containing product would be introduced into their server line. According to the rumor, the product would come off the R&D line.

There are also multiple reports that that you should be aware of, IBM will divest its fab business entirely. On May 11th EE Times reported that “rumors were rampant” that the IBM Microelectronics Division was once again up for sale and that GlobalFoundries was the reported suitor. Boris Petrov, former director of strategic marketing for Chartered has reported [link] that the IBM hardware business currently accounts for ~ 10% of their yearly income. He sees IBM selling their fabs to Globalfoundries (backed by Abu Dhabi finances) and retaining their R&D operations. Under his scenario IBM would provide process and materials engineering for the worldwide GlobalFoundries fab operation. More if these rumors continue to develop.

For all the latest on 3D IC and advanced packaging stay linked to IFTLE…….

remember – for access to all the previous issues of PFTLE go to www.PFTLE.net