Insights From Leading Edge

IFTLE 100 IMAPS MINAPAD Addresses Advanced Packaging in Grenoble

"I’ve been a big fan of Phil’s ever since his first blog in August of 2007. Did you know he was born in Hell’s Kitchen in New York City? Congratulations to the world’s foremost expert on 3D integration on his 100th blog!" — Peter Singer, Editor-in-Chief, Solid State Technology

Dr. Phil Garrou has been blogging for years on the evolution of semiconductor assembly and packaging technologies. In his first 100 blog posts, he’s covered the emergence and explosion of 3D packaging, and most recently, the "2.5D" innovation of interposers.

To celebrate Dr. Garrou’s 100th post to Insights from the Leading Edge, we’ve compiled a list of his top 10 best-read recent blogs. You’ll find them at the end of this post………………

IMAPS France held the 2nd Micro/Nano-Electronics Packaging, Assembly, Design and Manufacturing Forum (MiNaPAD) in Grenoble in late April.

Jean-Marc Yannou, President of IMAPS France gave a Yole market update on 3DIC and TSV interconnects indicating that Wafer-level-packages are the fastest growing semiconductor packaging technology with more than 27% CAGR in units and 20% in wafers over the next 5 years to come.

(Click on any of the images below to enlarge them)

Yannou also repeated rumors that "Power 8 by IBM believed to be based on 3D interposers; Haswel, Intel GPU on 2.5D interposers for laptops with lots of on board memory and ultra large data bus. "
Leti gave an update on the 3DICE program being done under the European Unions 7th Framework with partners Datacon, Disco, EVG and ST Micro. Below find the unit operations that are part of the program and those responsible. They have concluded that B2F has less operations and is easier to accomplish than F2F.
Back to face attach can be done with die attach film, full sheet bonding layer or patterned bonding layer.
B2F pick and place with a Datacon 2200 can reportedly handle 20um thick die with 7um accuracy in 3 sec. Plasma stress relief allows for thin die handling by increasing die strength.
Thin die encapsulation can be accomplished in several ways i.e by conformal CVD deposition (oxide or parylene), by spin/spray coating of solutions (BCB, PI, ALX) or by film lamination. Die are bevel cut at 45 degrees to make subsequent metallization easier.
Thermo-mechanical stress in these combinations were examined.

EVG gave more details on the release process for their ZoneBond TB/DB (temp bond/debond) process.

– Adhesive ring dissolution is enhanced by magasonics                                                                                   
– Low force, room temperature separation                                                                                                        
– Compatible with both glass and Si carriers                                                                                                       
– Adhesives are (solvent)cleanable                                                                                                                    
– Platform enables use of a wide range of materials, i.e. ZoneBond Open Platform
The anti sticking layer showed a temperature stability up to 300C for 20 min. Carrier wafers were bonded and debonded 25x.
Rolf Aschenbrenner of the Fraunhoffer IZM made an in depth presentation on "Molding
technologies  – A new way for system integration" specifically looking at options for today’s transfer molding and compression molding technologies.

While transfer molding has been used for years to make plastic packaged parts, compression molding has recently become in vogue as part of the embedded chip technology package, i.e molded reconfigured wafers.

They propose the following roadmap for system integration with molding.

ST Micro presented some electromigration details on SnAgCu interconnect for WLB packages.
They find that:
 IMC induces resistance increase right after stress beginning
Electrical open is due to voiding in solder, at Cu3Sn interface, after Cu6Sn5 disappeared
Since the electrical opens are due to voids at the RDL/solder interface a solution is to insure that the enclosure around the solder ball is large enough and increase the RDL thickness as much as possible.  

We will have more MINAPAD review in next week’s IFTLE.
For all the latest in 3DIC and Advanced Packaging stay linked to IFTLE……………………..

10 Must-Read Insights from the Leading Edge:
1. Apple and TSVs, top chip makers, and "betting the ranch"

This post investigated Apple’s possible move to TSVs for its A6 chip, and compared capex numbers to the Western trope of "betting the ranch." Apple’s semiconductor roadmap, and the advanced packaging technology of TSVs combined for a compelling read. Link:

2. LED market is about to explode

While Insights from the Leading Edge covers a great deal of 3D packaging news, that doesn’t mean that there are no other very significant packaging evolutions and market opportunities going on at the same time. Certainly the LED space is one of those, Dr. Garrou said, and readers agreed.


3. Bidding Adieu to Lester Lightbulb

Lester Lightbulb has become something of a favorite character on Insights from the Leading Edge, as Dr. Garrou carries out an in-home energy/cost savings analysis of conventional incandescent lightbulbs, CFLs, and LEDs.


4. Advances in CMOS Image Sensing

In the fall of 2007, Toshiba first announced the commercialization of TSV in a CMOS image sensor (CIS). The next step of circuit repartitioning and stacking was interrupted by back side imaging, which flipped the chip over and let the light enter through the least obstructed side to let more light in per pixel. Now, we consider today’s CIS advances.


5. Cell Phones and Memory Consolidation

The cellphone continues to pull in the functionality of digital cameras, PDAs, GPS navigators, mobile TV and numerous other applications. It is quickly becoming the dominant market driver for virtually all of these functions.


6. How Xilinx fit 6.8B transistors on its 2.5D FPGA

Garrou reviews Xilinx’s new FPGA, with 10,000 connections on a silicon interposer, using "2.5D packaging."


7. MEPTEC 2.5, 3D and beyond

Reporting from MEPTEC and SEMI’s "2.5D, 3D and Beyond Bringing 3D Integration to the Packaging Mainstream" Conference in 2011, Dr. Garrou shares highlights from Amkor, GLOBALFOUNDRIES, and other presenters.


8. Fine Pitch Microjoints, Cu Pillar Bump-on-Lead, Xilinx Interposer Reliability

Dr. Garrou looks at packaging activities at the 2011 ECTC, including presentations from Qualcomm and STATS ChipPAC, Fraunhofer IZM, Xilinx (interposers!), and others.


9. TSV from 1999 to today, and more on the Micron HMC

Dr. Garrou shows us the evolution of TSV from 1999 through to today, checks in on MU’s HMC, and analyzes some recent packaging news.


10. Defining 3D, and Canon’s packaging equipment foray

Garrou explains the variety of 3D packaging terms with a little help from "Raymond J. Johnson Jr." He also notes Canon’s back-end equipment entry.


Here’s to 100 more Insights from the Leading Edge blog posts!


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