By Dr. Phil Garrou, Contributing Editor

Amkor Denying Takeover Rumors

Amkor finds itself denying rumors published in Digitimes that there is a takeover bid from Chinas Nantong Fujitsu [link]. If true, Nantong Fujitsu would become the largest OSAT in China as well as the second largest in the world, trailing only ASE.

Taiwan’s Central News Agency has also reported that there is speculation that Nantong wants to buy Amkor [link]

Nantong Fujitsu Microelectronics Co., provides IC assembling and testing services to the semiconductor industry in China. The company offers DIP, SOP; BGS, FC and WLP for automotive devices, memory products, analog ICs, microcontrollers, wireless/RF and analog devices; portable products such as cell phones, data storage systems, notebook computers, and pagers.

Nantong Fujitsu acquired an 85% share of AMDs Penang Malasia and Suzhou China packaging facilities for $371 MM earlier in 2016. [link]

Although Amkor is denying the rumor, such an offer would fit with he previously discussed China 2020 plan to become a major player in packaging [ see IFTLE 296 “…China the Wild Card…” ]

BCB Team Wins American Chemical Society (ACS) Award

The American Chemical Society (ACS) has just announced that a team of current and ex-employees of Dow Chemical have been awarded the ACS award for team innovation for their development and commercialization of Benzocyclobutene (BCB) dielectric [link].

The team, which consisted of Phil Garrou (yours truly), Bob DeVries, Carol Mohler, Eric Moyer and Ted Stokich, worked together to define and scale up a commercial product from a Central Research curiosity.

The award is for work done some 25 years ago, when the Dow team, partially under a DARPA contract, developed a photosensitive BCB formulation which was incorporated into the bumping and wafer level packaging processes developed by FCT (Flip Chip Technologies – Ultra CSP) ) and Unitive (Extreme CSP) and later licensed and practiced by most of the major Taiwan and Korean OSAT houses. At the time, current generations of PI failed to produce manufacturable processes and in the early 2000’s, before new generations of PI and PBO were developed to meet these needs, BCB based components were being used in nearly every cell phone produced in the world.

BCB also revolutionized the MANTECH defense industry by allowing Triquint, Teledyne, NGAS, Raytheon, MA-COM and many others develop multilayer interconnect for their GaAs, GaN and InP processes [link].

For those that are interested the history of BCB was summarized in the article “Development and Commercialization of BCB for Microelectronic Applications” by Garrou et. al., in The World of Electronic Packaging and System Integration , B. Michel and R. Aschenbrenner Eds., ISBN 3-932434-76-5. 

IMEC

In the July issue of IEEE Trans. CPMT (p. 983) IMEC’s Eric Beyne reviewed via middle TSV technology development [link].

This paper discusses the key technological aspects of via-middle Cu TSVs, The 3-D integration concept and the wafer front and backside process technology for a 5μm x 50μm Si TSV. A very nice review of TSV formation, exposure and the impact of TSVs on devices.

The via-middle process flow consists of two main modules: 1) the via-middle process between FEOL and BEOL processing and 2) the backside thinning and via reveal process.

Via Middle Process

The via-middle TSV process consists of integrating the TSV module between the end of the FEOL process (typically the formation of W contact metal to devices) and the first damascene Cu interconnect layers. The thermal limitation for processing is, therefore, in the range of 420 –450°C.

The IMEC baseline TSV is a 5-μm diameter, 50-μm deep Si etched TSV. The oxide liner is deposited using a TEOS/O3 pulsed CVD process with a target thickness of 200 nm at the TSV bottom.

As a Cu diffusion barrier layer, 5nm PVD Ta is used. As PVD is highly non conformal, this requires a 120–140nm thick Ta layer on the frontside of the wafer. Cu PVD is used as a Cu seed plating layer. To achieve a sufficiently thick Cu seed at the bottom of the via, an 800–1000nm thick Cu PVD deposit is required on the wafer surface area. This seed layer allows for Cu electrochemical deposition (ECD) and voidless filling of the vias.

After filling a 5 × 50μm via, the thickness of Cu deposited on the wafer surface is 3μm. The actual copper diameter is ∼4.9μm at the top and 4.3μm at the bottom of the TSV. To stabilize the Cu in the TSV and remove impurities after plating, a high temperature anneal is performed before Cu CMP resulting in Cu grain growth and a stable Cu microstructure. Finally, CMP is used to remove the Cu overburden, the Ta barrier layer, and the oxide liner.

The main challenge for scaled TSVs is, however, the deposition of a Cu diffusion barrier layer and a Cu electroplating seed layer.

Fully conformal plasma enhanced ALD oxides offer a clear advantage when scaling the TSV diameter. In addition, these dielectrics reduce the thickness of the oxide deposited on the wafer surface by 50%, greatly reducing the oxide liner CMP process time.

As the aspect ratio of the TSVs increases with diameter scaling, the use of PVD for barrier/seed deposition becomes more difficult. ALD deposited barriers are shown to be highly effective for scaled TSV since they can reduce the overall TSV process costs by reducing the deposited layer thickness on the wafer surface by ~10× and, therefore, reduce the CMP time.

Wafer Backside Flow

The Si wafer has to be thinned to enable backside contact to the embedded via middle TSV structures. This requires temporary bonding of the TSV wafer on a carrier substrate, wafer thinning, and a TSV via-reveal process.

Wafer thinning is performed by mechanical wafer grinding. Mechanical thinning results in backside silicon damage, stress, cracks, and dislocations therefore, after grinding and wafer cleaning some of

the backside Si is further thinned using either wet or dry methods. After slightly recessing the Si surface with respect to the backside revealed TSV, the oxide liner is still present on the top of the exposed TSVs. In order to avoid possible backside Cu contamination on the thin Si wafer, a backside SiO/SiN passivation layer is deposited. This has to be performed at relatively low temperatures (<200 °C) as the thin wafer is supported by a temporary carrier using a polymeric glue material.

A backside CMP process step exposes the Cu of the TSVs for further backside processing (e.g., metal redistribution, solder microbumps, and so on).

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